REV 2.3 2001/12/21
Sigma-Delta Voice CODEC
COD0418X
FEATURES
GENERAL DESCRIPTION
The COD0418X is Sigma-Delta CODEC for
speech and telephony applications. The product
contains both digital IIR/FIR filter and
smoothing filter. The normal input and output
channels have µ/A law format with 38dB signal
to distortion ratio. The input and output of this
device is compressed form(A-law, µ-law) and
16bit linear which can be easily determined by
control select pins. and it has variable gain
control block varies from -4dB to +58dB, 2dB
steps and input type of AFE is differential and
there is another analog bypass mode single
input port. An on-chip voltage reference circuit
is included to allow the single supply operation.
TYPICAL APPLICATIONS
- Speech Processing
(Recognition, Synthesis, Compression etc.)
- Telephony
- Modem
- Single chip voice line Codec (A/D, D/A converter included)
- Oversampled Sigma Delta modulator/Demodulator
- Input/Output format : 8bit µ-law/A-law and linear 16bit
* These three types are easily selectible by control pins
* When serial interface mode : 16bit linear
- ADC gain block(AFE) range : -4dB to +58dB, 2dB step
- DAC gain block rang : 0,2,3.5dB
- Analog bypass mode for substitution of AFE
- Sigma Delta ADC.
* 256X Oversampling
* On chip Decimation Filter
* On chip Smoothing Filter
- Sigma Delta DAC.
* 256X Oversampling
* On chip 256X Interpolation Filter
* On chip Analog Post Filter
- AFE has differential inputs, analog bypass mode has single
input and analog output is single.
- Sampling Rate : 8KHz
- On chip voltage reference circuitry
- Single +2.5V Power Supply
- 1.6Vpp Input/Output signal swing but with signal distortion
output swings up to 2Vpp.
- Power Consumption
* Operating Mode : 17mW Typ(2.5V)
* Powerdown Mode : 125µW Typ(2.5V)
FUNCTIONAL BLOCK DIAGRAM WITH INPUT/OUPUT APPLICATION
SYNCSDECI[1:0]TDECI SINPO[1:0]TPOST ADLCS DALCSBCK DADS ADHPBDAHPBAIG[4:0]AIS[4:0]DG[1:0]ADCPS
0.33uF Tantalum
Capacitor
- +
+
0.33uF- Tantalum
Analog ¥Ò ¥Ä
Modulator
Mux
+
0.33uF- Tantalum
Capacitor
Bypass
Mode
Input
Decimation
Filter
Serial Interface
+ Offset Calibration
1. 16bit Linear PCM
2. ¥ì -law
3. A-law
SDOUT
AFE
Offset
Calibration
DAC
Capacitor
AIG[4:0]
AFETP
AIS[1:0]
AFETN
Reference
Generation
Blocks
+
+
VREFOUT
IREF
10uF
0.1uF
APOSTOUT
Analog
Post Filter
Digital ¥Ò ¥Ä
Modulator
Interpolation
Filter
DG[4:0]
VDD25AA1VSS25AA1VDD25AD1VSS25AD1 REFL DAMUTE ADMUTE ALOOPADPWD DAPWD RST X256FS DACPS
SAMSUNG ELECTRONICS Co. LTD
SDIN
COD0418X
Sigma-Delta voice CODEC
CORE PIN DESCRIPTION
NAME
I/O
TYPE
I/O PAD
PIN DESCRIPTION
I/O TYPE ABBR.
VDD25AA1
AP
vdd2t_abb
Analog Power (+2.5V) : 10uF ceramic and 0.1uF tantalum
capacitors should be connected between VDD25AA1 and
VSS25AA1 and these two capacitors should be placed as close
as possible to two power pads. and the order of two capacitor
is described in core evaluation guide.
VSS25AA1
AG
vss2t_abb
Analog Ground (0.0V)
IREF
AO
poa_abb
Current Reference Output : this pin is for test, so normally this
pin is float.
Analog Reference Ground (0.0V) : for proper operation the end
user should supply clean ground level voltage to this pin but if
there is no other ground level source, end user can supply
analog ground level to this pin.
* Note : if there are not enough pins available, end user can
connect this pin to VASS25AA1, but in this case REFL should
be connected to "VASS25AA1 PAD"
REFL
AG
vss2t_abb
AINP
AI
pia_abb
AFE Analog Positive input : this is positive analog input pin
of Aanalog Front End gain stage. and the input impedance of
this pin is 20Kohm.
AINN
AI
pia_abb
AFE Analog Negative input : this is negative analog input pin
of Aanalog Front End gain stage. and the input impedance of
this pin is 20Kohm.
AFETP
AO
poa_abb
AFE Positive Test Output : this is a test pin of AFE block
and AFE positive output, the detailed control of this test mode
is described in pin description of AIS[1:0]
AFETN
AO
poa_abb
AFE Negative Test Output : this is a test pin of AFE block
and AFE negaitive output, the detailed control of this test
mode is described in pin description of AIS[1:0]
DAMUTE
DI
picc_abb
DAC Analog Mute select (High active) : when high state DAC
mute fuction activates
ADMUTE
DI
picc_abb
ADC Analog Mute select (High active) : when high state ADC
mute fuction activates
ALOOP
DI
picc_abb
Analog loop back select (High active) : test pin for internal
anlaog blocks only. and in normal operation, this is LOW state.
VREFOUT
AO
poa_abb
Vref output : voltage reference output of COD0418x and two
capacitors should be placed between VREFOUT and analog
ground level and one capacitor is 10uF and the other is 0.1uF
and detailed capacitor order is described in core evaluation
guide and input/output application guide.
ABIN
AI
pia_abb
Bypass Mode Analog Input : analog input of bypass mode and
detailed control of byapss mode is described in pin description
of AIS[1:0]
poa_abb
DAC Analog output : the output load of APOSTOUT is
10Kohm and maximum output of this is 1.6Vp-p but from the
request of end user the DAC gain has 3 steps, when
0dB=1.337Vpp, 2dB=1.683Vpp and 3.5dB=2.0Vpp and AC
Electical test of DAC will be performed at 0dB gain and
1.6Vpp input source for core performance test.
APOSTOUT
AO
-
AI : Analog Input
DI : Digital Input
AO : Analog Output
DO : Digital Output
AB : Analog Bidirectional
DB : Digital Bidirectional
AP : Analog Power
AG : Analog Ground
DP : Digital Power
DG : Digital Ground
NOTES
1. This pin descriptions are not fixed, but recommended.
2. The Power pin(VDD25AA1,VDD25AD1) must be connected by DIODE_SLOT2.
3. The Ground pin (VSS25AA1, VSS25AD1) must be connected by DIODE_SLOT2.
4. SDECI[1:0], TDECI -> Decimation Filter Block test pin.
5. SINPO[1:0], TPOST -> Post Filter Block test pin.
SEC ASIC
2/16
Mixed Signal Core Group
COD0418X
Sigma-Delta voice CODEC
CORE PIN DESCRIPTION (Cont'd)
NAME
I/O
TYPE
I/O PAD
PIN DESCRIPTION
ADPWD
DI
picc_abb
ADC Power Down (High active) : when high state ADC power
down activates
DAPWD
DI
picc_abb
DAC Power Down (High active) : when high state DAC power
down activates
RST
DI
picc_abb
Digital Reset (High active)
X256FS
DI
picc_abb
256*Sampling Freq.(FS) Clock : main clock of COD0418x and
it should be 2.048MHz
SYNC
DI
picc_abb
Sampling Freq.(FS) Clock
SDECI[1:0]
DI
picc_abb
ADC Digital Filter input select : test pin for internal functional
blocks, and in normal operation these are LOW states.
TDECI
DI
picc_abb
ADC Digital Filter Test input : test pin for internal functional
blocks, and in normal operation, this is LOW state.
SINPO[1:0]
DI
picc_abb
DAC Post Filter input select : test pin for internal functional
blocks, and in normal operation these are LOW states.
SDIN
DI
picc_abb
Serial Data Input : The input of DAC
TPOST
DI
picc_abb
DAC Post Filter Test input : test pin for internal functional
blocks, and in normal operation, this is LOW state.
ADLCS
DI
picc_abb
ADC Linear/Compand data select (Low/High) : when low state
ADC Linear mode selected, and high ADC Compand mode
selected.
DALCS
DI
picc_abb
DAC Linear/Compand data select (Low/High) : when low state
DAC Linear mode selected, and high DAC Compand mode
selected.
ADCPS
DI
picc_abb
ADC µ-law/A-law select (Low/High) : when high state ADC
Α-law mode selected, and low ADC µ-law mode selected.
DACPS
DI
picc_abb
DAC µ-law/A-law select (Low/High) : when high state DAC
Α-law mode selected, and low DAC µ-law mode selected.
VSS25AD1
DG
vss2t_abb
Digital Ground (0.0V) : 10uF ceramic and 0.1uF tantalum
capacitors should be connected between VDD25AD1 and
VSS25AD1 and these two capacitors should be placed as close
as possible to two power pads. and the order of two capacitors
is described in core evaluation guide.
VDD25AD1
DP
vdd2t_abb
Digital Power Supply (2.5V)
SDOUT
DO
pot2_abb
Serial Data Output : this is ADC output
BCK
DI
picc_abb
Bit Clock - Serial Interface Clock
DADS
DO
pot2_abb
DAC Modulator output : DAC sigma-delta modulator output
and this pin is for internal functional block test, and in normal
operation, this pin is floating state, but this should be muxed
out for test.
picc_abb
ADC High Pass Filter Enable (Low Active) : this pin changes
of lower side of baseband frequency response. when high state
COD0418X core will transmit very low frequency component
( from DC to 300Hz ) but when low state, high pass filter
function will be enabled, so frequencies below 300Hz will be
eliminated. this is only for ADC path.
picc_abb
DAC High Pass Filter Enable (Low Active) : this pin changes
of lower side of baseband frequency response. when high state
COD0418X core will receive very low frequency component
( from DC to 300Hz ) but when low state, high pass filter
function will be enabled, so frequencies below 300Hz will be
eliminated. this is only for DAC path.
ADHPB
DAHPB
DI
DI
SEC ASIC
3/16
Mixed Signal Core Group
COD0418X
Sigma-Delta voice CODEC
CORE PIN DESCRIPTION (Cont'd)
NAME
I/O
TYPE
I/O PAD
PIN DESCRIPTION
AFE Gain Control : this will change the AFE gain linearly.
and gain step size is 2dB
AIG[4:0]
DI
picc_abb
AIG[4:0]=00000
AIG[4:0]=00001
.
.
.
AIG[4:0]=11110
AIG[4:0]=11111
: -4dB
: -2dB
: +56dB
: +58dB
AIS[1:0]
DI
picc_abb
Analog Input Select : this is for selecting input path and AFE
test mode. refer to following description and digram below.
1. when AIS[1:0]=00 then only switch A is on, so end user
can use AFE + codec core.
2. when AIS[1:0]=01 then only switch B is on, so end user
can use analog bypass mode + codec core
3. when AIS[1:0]=10 then only switch C is on, so end user
can test AFE block only.
4. when AIS[1:0]=11 then switch B and C are on, so end user
can use analog bypass mode + code core and test AFE block
at the same time.
DG[1:0]
DI
picc_abb
DAC Gain Control : dac gain has 3 steps when DG[1:0]=00
0dB will be set, DG[1:0]=01 then 2dB and DG[1:0]=10 then
3.5dB respectively.
AIS[1:0] Analog Input Select Diagram.
Switch B
ABIN
Bypass
Mode
Input
Codec
Core
AINP
AINN
AFE
Switch A
AFETP
AFETN
Switch C
SEC ASIC
4/16
Mixed Signal Core Group
COD0418X
Sigma-Delta voice CODEC
ABSOLUTE MAXIMUM RATINGS
Characteristic
Symbol
Value
Unit
VDD25AD1
3.3
V
Digital Input Voltage
DIN
VSS25AD1 to VDD25AD1
V
Storage Temperature Range
Tstg
-45 to 125
°C
Operating Temperature Range
Topr
0 to 70
°C
Supply Voltage
NOTES
1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently.
Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each
condition value is applied with the other values kept within the following operating conditions and function
operations under any of these conditions is not implied.
2. All voltages are measured with respect to VSS(VSS25AA1 or VSS25AD1) unless otherwise specified.
RECOMMENDED OPERATING CONDITIONS
Characteristics
Symbol
Min
Typ
Max
Unit
Supply Voltage
VDD25AA1 • VSS25AA1
VDD25AD1 • VSS25AD1
2.375
2.5
2.625
V
Supply Voltage Difference
VDD25AA1 • VDD25AD1
0.1
0.0
0.1
V
Digital Input Voltage
Range
2.25
2.5
2.75
V
Analog Input Voltage
Range
-
1.6
-
Vpp
NOTES
It is strongly recommended that all the supply pins (VDD25AA1, VDD25AD1) be powered from the same source to
avoid power latch up.
DIGITAL FILTER CHARACTERISTICS
Characteristics
Filter Passband
Filter Passband ripple
Filter Stopband
Filter Stopband attenuation
SEC ASIC
Ratio
Value (Fs = 8KHz)
Conditions
0 ~ 0.4Fs
0 ~ 3.2KHz
high pass filter off
0.0375Fs ~ 0.4Fs
300Hz ~ 3.2KHz
high pass filter on
±0.5dB
±0.5dB
-
0.6Fs over
4.8KHz over
high pass filter off
0.0375Fs under,
0.6Fs over
300Hz under
4.8KHz over
high pass filter on
-1.2dB(0.425Fs)
-40dB (0.6Fs over)
-1.2dB(3.4KHz)
-40dB(4.8KHz over)
high pass filter off
-1.2dB(0.425Fs)
-40dB (0.6Fs over)
-8dB(0.0075Fs)
-25dB (0Fs)
-1.2dB(3.4KHz)
-40dB(4.8KHz over)
-8dB(60Hz)
-25dB(0Hz)
high pass filter on
5/16
Mixed Signal Core Group
COD0418X
Sigma-Delta voice CODEC
AC ELECTRICAL CHARACTERISTICS
(Measurement Bandwidth is 20Hz - 4KHz. Full scale input sine wave 1KHz, FS=8KHz, @VDD25AA1,VDD25AD1=2.5V,
Ta=25°C ,Unless otherwise specified.)
Codec Core Characteristics
Characteristics
Symbol
Min
Typ
Max
Unit
Resolution
-
16
-
Bits
Sampling rate
-
8
-
KHz
Conditions
-
Bypass Mode ADC Analog Characteristics
35
38
-
dB
0dB Input : µ/A Law compand
-
70
-
dB
0dB Input : Linear
-
dB
29.5
* Signal to Distortion Ratio
28
29
-40dB Input : A-Law compand
25
23
-40dB Input : µ-Law compand
-
dB
24
-45dB Input : µ-Law compand
-45dB Input : A-Law compand
* Signal to Noise Ratio
80
-
-
dB
0dB Input : Linear
Offset Error
-
-
±20
mV
-
Input Voltage Range
-
1.6
-
Vpp
-
DAC Analog Characteristics With 0dB DAC Gain
( Note : The performance over 1.6Vp-p output will be reduced. )
35
38
-
dB
-
-
80
dB
30
33.5
-
dB
* Signal to Distortion Ratio
29
32
25
30
0dB Input : µ/A Law compand
0dB Input : Linear
-40dB Input : µ-Law compand
-40dB Input : A-Law compand
-
dB
-45dB Input : µ-Law compand
24
27
80
-
-
dB
0dB Input : Linear
-
1.337
−
Vp-p
0 dB Gain
-
1.683
−
Vp-p
2 dB Gain
-
2
−
Vp-p
3.5 dB Gain
Output Current
-
1mA
−
Output Load
4.7
10
Offset Error
-
-
* Signal to Noise Ratio
Output Voltage Range
-45dB Input : A-Law compand
±20
KΩ
purely resistive load
mV
-
Power Supply
Power comsumption
(2.5v Operating Mode)
Analog +
Digital
-
17
-
20
-
mW
-
Power comsumption
(2.5v Powerdown Mode)
-
125
-
uW
This power down current can be
measured only when ADPWD and
PAPWD activated (both high active)
simultaneously
SEC ASIC
6/16
Mixed Signal Core Group
COD0418X
Sigma-Delta voice CODEC
AC ELECTRICAL CHARACTERISTICS (Cont'd)
(Measurement Bandwidth is 20Hz - 4KHz. Full scale input sine wave 1KHz, FS=8KHz, @VDD25AA1,VDD25AD1=2.5V,
Ta=25°C ,Unless otherwise specified.)
AFE + ADC Analog Characteristics
* Signal to Distortion
Ratio
-
70
-
dB
0dB Input : Linear
Offset Error
-
-
±20
mV
-
Input Voltage Range
-
1.6
-
Vpp
-
SEC ASIC
7/16
Mixed Signal Core Group
COD0418X
Sigma-Delta voice CODEC
Core Configuration and Pin Information For Test
AINP
AINN
ABIN
REFL
DAPWD
VSS25AD1
ADPWD
VDD25AD1
ALOOP
VSS25AA1
ADMUTE
VDD25AA1
DAMUTE
RST
IREF
X256FS
SYNC
AFETP
SDECI[1:0]
AFETN
TDECI
COD0418X
VREFOUT
APOSTOUT
SINPO[1:0]
SDOUT
SDIN
DADS
TPOST
ADLCS
DALCS
ADCPS
Red : Dedicated
DACPS
Blue : Mux Out for Test
Input Pin
Output Pin
Bidirectional Pin
(These should be very close to PADs.
And No Other signal can be cross)
BCK
ADHPB
DAHPB
AIG[4:0]
AIS[1:0]
DG[1:0]
SEC ASIC
8/16
Mixed Signal Core Group
COD0418X
Sigma-Delta voice CODEC
Pin Information For Test ( Cont'd )
I/O
TYPE
I/O PAD
Pin type for Test
VDD25AA1
AP
vdd2t_abb
dedicated
VSS25AA1
AG
vss2t_abb
dedicated
IREF
AO
poa_abb
dedicated
NAME
REFL
AG
vss1t_abb
dedicated
* But if there are not enough pins
available, the end user could connect this
pin to VSS25AA1, but in this case REFL
and VSS25AA1 should be met only at
VSS25AA1 PAD
AINP
AI
pia_abb
dedicated
AINN
AI
pia_abb
dedicated
AFETP
AO
poa_abb
dedicated
AFETN
AO
poa_abb
dedicated
DAMUTE
DI
picc_abb
controlled by customer logic
ADMUTE
DI
picc_abb
controlled by customer logic
ALOOP
DI
picc_abb
tied to Ground ("L")
VREFOUT
AO
poa_abb
dedicated
ABIN
AI
pia_abb
dedicated
APOSTOUT
AO
poa_abb
dedicated
AIG[4:0]
DI
picc_abb
accessible for codec test mode, muxed pin
AIS[1:0]
DI
picc_abb
accessible for codec test mode, muxed pin
DG[1:0]
DI
picc_abb
accessible for codec test mode, muxed pin
ADPWD
DI
picc_abb
controlled by customer logic
DAPWD
DI
picc_abb
controlled by customer logic
RST
DI
picc_abb
controlled by customer logic
X256FS
DI
picc_abb
accessible for codec test mode, muxed pin
SYNC
DI
picc_abb
accessible for codec test mode, muxed pin
SDECI[1:0]
DI
picc_abb
tied to Ground ("LL")
TDECI
DI
picc_abb
tied to Ground ("L")
SINPO[1:0]
DI
picc_abb
tied to Ground ("LL")
accessible for codec test mode, muxed pin
SDIN
DI
picc_abb
TPOST
DI
picc_abb
tied to Ground ("L")
ADLCS
DI
picc_abb
controlled by customer logic
DALCS
DI
picc_abb
controlled by customer logic
ADCPS
DI
picc_abb
controlled by customer logic
DACPS
DI
picc_abb
controlled by customer logic
VSS25AD1
DG
vss2t_abb
dedicated
VDD25AD1
DP
vdd2t_abb
dedicated
SDOUT
DO
pot2_abb
accessible for codec test mode, muxed pin
BCK
DI
picc_abb
accessible for codec test mode, muxed pin
DADS
DO
pot2_abb
accessible for codec test mode, muxed pin
ADHPB
DI
picc_abb
controlled by customer logic
DAHPB
DI
picc_abb
controlled by customer logic
dedicated : 13pins
( if end user connects VREFL to
VSS25AA1 then 12pins )
accessible for codec test mode, muxed pin : 15pin
controlled by customer logic : 11pin
SEC ASIC
9 /16
I/O TYPE ABBR.
-
AI
DI
AO
DO
AB
DB
AP
AG
DP
DG
: Analog Input
: Digital Input
: Analog Output
: Digital Output
: Analog Bidirectional
: Digital Bidirectional
: Analog Power
: Analog Ground
: Digital Power
: Digital Ground
Mixed Signal Core Group
COD0418X
Sigma-Delta voice CODEC
Core Layout Guide
VSS25AA1:G
VDD25AA1:P
VREFOUT:
VREFOUT:
IREF
IREF
REFL:
VREFOUT:
CODEC
APOSTOUT
VREFOUT:
VREFOUT
REFL:
AFETP
* There are 2 analog power/ground pairs in left-bottom
of this core and below them, there are a couple of
digital lines and PADS, so every digital lines should
be located as far as possible to analog power/ground
lines
AFETP
AFETN
AFETN
AINN
AINP
AINN
ABIN
AINP
VDD25AA1:P
VSS25AA1:G
VDD25AA1:P
VSS25AA1:G
VSS25AA1:G
VDD25AA1:P
VSS25AA1:G
VDD25AA1:P
VSS25AA1:G
VDD25AA1:P
VREFOUT:
VSS25AA1:G
DG[1]
DG[0]
AIS[1]
AIS[0]
AIG[4]
AIG[3]
AIG[2]
AIG[1]
AIG[0]
DAHPB
ADHPB
BCK
DACPS
ADCPS
DALCS
ADLCS
TPOST
SDIN
SINPO[1]
SINPO[0]
TDECI
SDECI[1]
SDECI[0]
SYNC
X256FS
RST
DAPWD
ADPWD
ALOOP
ADMUTE
DAMUTE
DADS
SDOUT
APOSTOUT
Digital
Glue Logic
ABIN
VSS25AA1
Digital PADs
VDD25AA1
- Analog core should be located to PADs as close as possible.
- Recommended Power/Ground Line Width >= 10um.
- There are only one Power PAD and only one Ground PAD respectively, but there are 6 Power Ports and 7 Ground
Ports on GDS. So each power/ground line should be connected to PADs and merged on the power/ground pad only.
- Similarly, there two REFL ports on GDS, and these two ports should be merged only on analog ground PAD.
- There are also 5 VREFOUT ports on GDS, in similar manner, these should be connect to VREFOUT PAD and
merged on that PAD.
- It’s good for analog core performance to give some space between analog core and digital glue logic, and
recommended space between analog core and digital glue logic is over 100um but if not available space, this should
be at least 50um.
NOTE
1. The layout of cod0418x consists of digital part and analog part. The digital part and the analog part should be divided.
2. It is recommended that you use thick analog power metal(>10um). when connecting to PAD, and the path should be as short as possible.
3. Digital power and analog power should be used separately.
SEC ASIC
10 /16
Mixed Signal Core Group
COD0418X
Sigma-Delta voice CODEC
- +
C3
ABIN
C3
C1
+ C2
+ -
AINP
ABIN
VREFOUT:
- +
C3
AINP
AINN
AINN
AFETN
AFETN
AFETP
AFETP
REFL:
VREFOUT
IREF
APOSTOUT
VREFOUT:
VDD25AA1:P
VREFOUT:
VSS25AA1
VSS25AA1:G
- C2
+
C1
REFL:
VDD25AA1:P
- +
IREF
- +
10K
CORE EVALUATION GUIDE
VSS25AA1:G
VSS25AA1:G
C1:10uF Ceramic Capacitor
C2:0.1uF Tantalum Capacitor
C3:0.33uF Tantalum Capacitor
COD0418X CORE
VDD25AA1:P
VDD25AA1
VSS25AA1:G
VDD25AA1:P
VSS25AA1:G
VDD25AA1:P
VSS25AA1:G
VDD25AA1:P
VSS25AA1:G
VREFOUT:
VREFOUT:
APOSTOUT
VSS25AD1:G
VDD25AD1:P
DG[1]
DG[0]
AIS[1]
AIS[0]
AIG[4]
AIG[3]
AIG[2]
AIG[1]
AIG[0]
DAHPB
ADHPB
BCK
DACPS
ADCPS
DALCS
ADLCS
TPOST
SDIN
SINPO[1]
SINPO[0]
TDECI
SDECI[1]
SDECI[0]
SYNC
X256FS
RST
DAPWD
ADPWD
ALOOP
ADMUTE
DAMUTE
DADS
SDOUT
C1
+ C2
+ -
VSS25AD1
Test Controller
...
VDD25AD1
<The Connection User Guide Line for Embedded Core Test>
NOTES
1. This core configuration is for test of analog and digital characteristics described in page 3-5 and in addition, all
digital control pins described in page 10, should be accessible for test of proper functions.
2. The analog power/ground must be separated from digital power/ground.
4. Power typical value :
VDD25AA1 = VDD25AD1 = 2.5V, VSS25AA1 = VSS25AD1 = 0.0V
SEC ASIC
11/16
Mixed Signal Core Group
COD0418X
Sigma-Delta voice CODEC
CONTROL CLOCKS CHARACTERISTICS
Characteristics
Symbol
Min
Typ
Max
Unit
X256FS Frequency
Fmck
-
2.048
-
MHz
BCK Frequency
Fbck
-
128
-
KHz
SYNC Frequency
Fsync
-
8
-
KHz
X256FS Duty cycle (H:L)
MCDuty
40:60
50:50
60:40
%
BCK Duty cycle (H:L)
BCDuty
40:60
50:50
60:40
%
SYNC Duty cycle (H:L)
SYDuty
40:60
50:50
60:40
%
X256FS Falling and BCK Edge Delay(Hold)
Tdbck
-
-
15
ns
X256FS Falling and SYNC Edge Delay(Hold)
Tdsync
-
-
15
ns
BCK Falling and SDOUT Delay
Tdsdout
-
-
15
ns
BCK Rising and SDIN Setup
Tsetup
10
15
20
ns
BCK Rising and SDIN Hold
Thold
10
15
20
ns
X256FS 0.5
VDD25AD1
SYNC 0.5
VDD25AD1
BCK
1/Fmck
0.5
VDD25AD1
1/Fbck
X256FS 0.5
VDD25AD1
1/Fsync
"H"
"L"
MCDuty
BCK 0.5
VDD25AD1
"H"
"L"
SYNC
0.5
VDD25AD1
BCDuty
"H"
"L"
SYDuty
0.5
BCK VDD25AD1
SYNC 0.5
VDD25AD1
X256FS 0.5
VDD25AD1
X256FS0.5
VDD25AD1
Tdsync
Tdbck
Thold
SDOUT 0.5
VDD25AD1
SDIN
0.5
VDD25AD1
BCK 0.5
VDD25AD1
BCK
0.5
VDD25AD1
Tsetup
Tdsdout
*Notes : BCK rising edge must NOT occur at the same time as SYNC edge.
SEC ASIC
12/16
Mixed Signal Core Group
COD0418X
Sigma-Delta voice CODEC
TIMING DIAGRAM
The frame of sync clock(SYNC) transitions determine the start of the serial data.
Input data
* All input data are clocked in by the falling edge of BCK.
* 16bit, 2's complement or 8bit A-law, µ-law data format.
Output data
*All output data are clocked out by the falling edge of BCK.
* 16bit, 2's complement or 8bit A-law, µ-law data format.
Notes
1. SYNC clock is at sampling frequency, Fs
2. 16bit linear data has 16bit serial data format, this is accomplished by 16FS ( = Fs clock x 16 )
Fs Clock
SYNC
16Fs
15
14
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
6
5
4
3
2
1
0
X
X
X
X
X
X
X
SDOUT[ADC output](Linear data)
15 ; MSB, 0 ; LSB
7
6
7 ; MSB, 0 ; LSB
5
4
3
2
1
0
X
SDOUT[ADC output](Compressed data)
15
14
15 ; MSB, 0 ; LSB
13
12
11
10
9
8
7
X : Non-valid
data
(0 insetion)
SDIN [DAC input](Linear data)
7
7 ; MSB, 0 ; LSB
13
BCK
6
5
4
3
2
1
0
X
X : Don't care data
SDIN [DAC input](Compressed data)
Codec serial interface timing diagram
Fs
SYNC
16Fs
BCK
256Fs
X256FS
Codec clock interface timing diagram
SEC ASIC
13/16
Mixed Signal Core Group
COD0418X
Sigma-Delta voice CODEC
INPUT/OUTPUT APPLICATION GUIDE
0.33uF Tantalum
Capacitor
Bypass
Mode
Input
- +
0.33uF Tantalum
Capacitor
- +
Gain
Input
- +
0.33uF Tantalum
Capacitor
0.1uF
Tantalum
Capacitor
+ -
+ -
10uF
Ceramic
Capacitor
Reference
Generators
The order of capacitors are not changeable
0.1uF capacitor should be located to chip as
close as possible
- +
Typical : 10K ohm
Minimum 4.7K ohm
Purely Resistive Load
AC Coupling Capacitor
= 1uF Tantalum
Chip Outside
SEC ASIC
14/16
Output
Amp
Chip Inside
Mixed Signal Core Group
COD0418X
Sigma-Delta voice CODEC
Core Verilog Modeling Information
COD0418X core modeling file is made by verilog XL. Basically this is a behavioral model and
just for checking of connectivity, functions and timing verification only. Because of this is a just
behavioral model, the output of this is not exactly same as output of real analog circuit. That
means the end user can't measure analog performance from output of this model and output of
this model just represents calculated output from logic in model description. And to use this
model in design, the end user should refer to annotation in the modeling file and test bench
program supplied with this model and modify them to fit their design.
Miscellaneous Informations
1. ADC Mute
ADC Mute function will be activated only when ADMUTE ( ADC MUTE Pin - High Active)
is high. and ADC mute will arise in digital section in ADC.
2. Zero Cross detector in Gain Change.
In DAC gain block, there is a zero cross detector, so only when the analog signal cross the
zero range, gain change will arise. and in ADC, no zero cross detector and controller are needed
because of cod0418x uses Σ∆ modulator in ADC, so every high frequency noise including pop
noise in ADC will be eliminated in the digital control blocks in ADC.
3. about ADHPB, DAHPB
ADHPB and DAHPB will change the frequency response of ADC and DAC path respectively.
when ADHPB is low, from 300Hz to 3.2KHz of baseband signal will be transmitted, but when
high, from 0Hz to 3.2KHz of signal will be transmitted. and when DAHPB is low, from 300Hz to
3.2KHz of signal will be received, but when high, from 0Hz to 3.2KHz of signal will be received.
Datasheet Revision History
SEC ASIC
15/16
Mixed Signal Core Group
COD0418X
Sigma-Delta voice CODEC
Version
Date
Ver 2.0
00.07.31
Core Spec has been completely modified. Every pages has been modified by new specs. So this
version is compeletely irrelevant to previous datasheet.
00.10.23
p1 : SDIN pin location of block diagram is corrected.
Power consumption changed ( 15mW ¡æ 17mW, 62.5uW ¡æ 125uW )
p2 : REFL and ALOOP pin descriptions are supplemented.
p3 : Pin descriptions of SDECI[1:0], TDECI, SINPO[1:0], SDIN, TPOST, BCK and DADS are
supplemented.
ADCPS and DACPS have been corrected. in the previous version of datasheet these had been
reversed.
p6 : power consumption changed (15mW ¡æ 17mW typical)
power down power changed (62.5uW ¡æ 125uW)
p8 : Core configuration page removed and core configuration and pin information for test are merged.
p10 : Note number 1 is added to "Core Layout Guide".
p11 : Note number 1 is amended.
p12 : BCK Frequency changed ( 256KHz ¡æ 128KHz )
Typical and minimum values of Tdbck, Tdsync and Tdsdout are removed.
Typo of timing diagram corrected ( in 4th row of 2nd column BCK -> SYNC)
p13 : Note number 2 is amended ( 14bit ¡æ 16bit ) and comments about don't care bits are removed.
MSB signs of diagram corrected ( 13 ¡æ 15 )
Comments of diagram concerning don't care bits are removed.
p15 : Miscellaneous informations about ADC mute, zero crossing, ADC and DAC high pass filter
functions are supplemented.
Ver 2.2
00.12.08
p2 : I/O Pad changed from vdd1t_abb/vss1t_abb to vdd2t_abb/vss2t_abb
p3 : - I/O Pad changed from vdd1t_abb/vss1t_abb to vdd2t_abb/vss2t_abb
- Typos corrected
p6 : Minimum output load changed from 10K ohm to 4.7ohm, typical 10k ohm
p9 : I/O Pad changed from vdd1t_abb/vss1t_abb to vdd2t_abb/vss2t_abb
p10 : Core layout guide changed
p11 : Core evaluation guide changed
p14 : Output application guide added
p15 : Typos about ADHPB and DAHPB are corrected
Ver 2.3
00.12.21
all pages ; preliminary sign eliminated
p7 : AFE+ADC performance changed to typical 70dB
p7 : total harmonic distortion item eliminated
Ver 2.1
Modified Items
SEC ASIC
16/16
Comments
Mixed Signal Core Group