ETC CS51031/D

CS51031
Fast PFET Buck Controller
The CS51031 is a switching controller for use in DC–DC
converters. It can be used in the buck topology with a minimum
number of external components. The CS51031 consists of a VCC
monitor for controlling the state of the device, 1.0 A power driver for
controlling the gate of a discrete P–channel transistor, fixed frequency
oscillator, short circuit protection timer, programmable soft start,
precision reference, fast output voltage monitoring comparator, and
output stage driver logic with latch.
The high frequency oscillator allows the use of small inductors and
output capacitors, minimizing PC board area and systems cost. The
programmable soft start reduces current surges at start up. The short
circuit protection timer significantly reduces the duty cycle to
approximately 1/30 of its cycle during short circuit conditions.
The CS51031 is available in 8 Lead SO and 8 Lead PDIP plastic
packages.
Features
• 1.0 A Totem Pole Output Driver
• High Speed Oscillator (700 kHz max)
• No Stability Compensation Required
• Lossless Short Circuit Protection
• VCC Monitor
• 2.0% Precision Reference
• Programmable Soft Start
• Wide Ambient Temperature Range:
– Industrial Grade: –40°C to 85°C
– Commercial Grade: 0°C to 70°C
5.0 V–12 V
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MARKING
DIAGRAMS
8
SO–8
D SUFFIX
CASE 751
8
1
1
8
DIP–8
N SUFFIX
CASE 626
8
20 Ω
MP1
IRF7416
VGATE
MBRS360
VC
VGATE
CS51031
AWL
YYWW
1
1
A
WL, L
YY, Y
WW, W
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN CONNECTIONS
VGATE
CIN
47 µF
51031
ALYW
1
VC
PGND
CS
COSC
GND
VCC
VFB
ORDERING INFORMATION*
D1
COSC
100 pF
COSC
CS51031
Device
PGND
CS
RVCC
10 Ω
VCC
CS
0.1 µF
CVCC
100 µF
100
GND
VFB
.01 µF
L
4.7 µH
RB
2.5 kΩ
VO
3.3 V @ 3 A
CRR
0.1 µF
RA
1.5 kΩ
CO
100 µF × 2
Package
Shipping
CS51031YD8
SO–8
95 Units/Rail
CS51031YDR8
SO–8
2500 Tape & Reel
CS51031YN8
DIP–8
50 Units/Rail
CS51031GD8
SO–8
95 Units/Rail
CS51031GDR8
SO–8
2500 Tape & Reel
*Additional ordering information can be found on
page 9 of this data sheet.
Figure 1. Typical Application Diagram
 Semiconductor Components Industries, LLC, 2001
May, 2001 – Rev. 8
1
Publication Order Number:
CS51031/D
CS51031
ABSOLUTE MAXIMUM RATINGS*
Rating
Value
Unit
Power Supply Voltage, VCC
20
V
Driver Supply Voltage, VC
20
V
Driver Output Voltage, VGATE
20
V
COSC, CS, VFB (Logic Pins)
6.0
V
Peak Output Current
1.0
A
Steady State Output Current
200
mA
Operating Junction Temperature, TJ
150
°C
Operating Temperature Range, TA
–40 to 85
°C
Storage Temperature Range, TS
–65 to 150
°C
2.0
kV
260 peak
230 peak
°C
°C
ESD (Human Body Model)
Lead Temperature Soldering:
Wave Solder: (through hole styles only) (Note 1.)
Reflow (SMD styles only) (Note 2.)
1. 10 sec. maximum.
2. 60 sec. max above 183°C.
*The maximum package power dissipation must be observed.
ELECTRICAL CHARACTERISTICS (Specifications apply for 4.5 ≤ VCC ≤ 16 V, 3.0 V ≤ VC ≤ 16 V;
Industrial Grade: –40°C < TA < 85°C; –40°C < TJ < 125°C: Commercial Grade: 0°C < TA < 70°C; 0°C < TJ < 125°C, unless otherwise specified.)
Characteristic
Oscillator
Test Conditions
Min
Typ
Max
Unit
160
200
240
kHz
VFB = 1.2 V
Frequency
COSC = 470 pF
Charge Current
1.4 V < VCOSC < 2.0 V
–
110
–
µA
Discharge Current
2.7 V > VCOSC > 2.0 V
–
660
–
µA
Maximum Duty Cycle
1 – (tOFF/tON)
80.0
83.3
–
%
Short Circuit Timer
VFB = 1.0 V; CS = 0.1 F; VCOSC = 2.0 V
Charge Current
1.0 V < VCS < 2.0 V
175
264
325
µA
Fast Discharge Current
2.55 V > VCS > 2.4 V
40
66
80
µA
Slow Discharge Current
2.4 V > VCS > 1.5 V
4.0
6.0
10
µA
Start Fault Inhibit Time
0 V < VCS < 2.5 V
0.70
0.85
1.40
ms
Valid Fault Time
2.6 V > VCS > 2.4 V
0.2
0.3
0.45
ms
GATE Inhibit Time
2.4 V > VCS > 1.5 V
9.0
15
23
ms
–
2.5
3.1
4.6
%
–
–
2.5
–
V
Fault Duty Cycle
CS Comparator
VFB = 1.0 V
Fault Enable CS Voltage
Max. CS Voltage
VFB = 1.5 V
–
2.6
–
V
Fault Detect Voltage
VCS when GATE goes high
–
2.4
–
V
Fault Inhibit Voltage
Minimum VCS
–
1.5
–
V
Hold Off Release Voltage
VFB = 0 V
0.4
0.7
1.0
V
Regulator Threshold Voltage Clamp
VCS = 1.5 V
0.725
0.866
1.035
V
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2
CS51031
ELECTRICAL CHARACTERISTICS (continued) (Specifications apply for 4.5 ≤ VCC ≤ 16 V, 3.0 V ≤ VC ≤ 16 V;
Industrial Grade: –40°C < TA < 85°C; –40°C < TJ < 125°C: Commercial Grade: 0°C < TA < 70°C; 0°C < TJ < 125°C, unless otherwise specified.)
Characteristic
VFB Comparators
Test Conditions
Min
Typ
Max
Unit
VCOSC = VCS = 2.0 V
Regulator Threshold Voltage
TJ = 25°C (Note 3.)
TJ = –40 to 125°C
1.225
1.210
1.250
1.250
1.275
1.290
V
V
Fault Threshold Voltage
TJ = 25°C (Note 3.)
TJ = –40 to 125°C
1.12
1.10
1.15
1.15
1.17
1.19
V
V
Threshold Line Regulation
4.5 V ≤ VCC ≤ 16 V
–
6.0
15
mV
Input Bias Current
VFB = 0 V
–
1.0
4.0
µA
Voltage Tracking
(Regulator Threshold – Fault Threshold Voltage)
70
100
120
mV
–
–
4.0
20
mV
Input Hysteresis Voltage
Power Stage
VCC = VC = 10 V; VFB = 1.2 V
GATE DC Low Saturation Voltage
VCOSC = 1.0 V; 200 mA Sink
–
1.2
1.5
V
GATE DC High Saturation Voltage
VCOSC = 2.7 V; 200 mA Source; VC = VGATE
–
1.5
2.1
V
Rise Time
CGATE = 1.0 nF; 1.5 V < VGATE < 9.0 V
–
25
60
ns
Fall Time
CGATE = 1.0 nF; 9.0 V > VGATE > 1.5 V
–
25
60
ns
VCC Monitor
Turn On Threshold
–
4.200
4.400
4.600
V
Turn Off Threshold
–
4.085
4.300
4.515
V
Hysteresis
–
65
130
200
mV
Current Drain
ICC
4.5 V < VCC < 16 V, Gate switching
–
4.5
6.0
mA
IC
3.0 V < VC < 16 V, Gate non–switching
–
2.7
4.0
mA
Shutdown ICC
VCC = 4.0
–
500
900
µA
3. Guaranteed by design, not 100% tested in production.
PACKAGE LEAD DESCRIPTION
PACKAGE PIN NUMBER
SO–8
DIP–8
PIN SYMBOL
1
1
VGATE
Driver pin to gate of external PFET.
2
2
PGND
Output power stage ground connection.
3
3
COSC
Oscillator frequency programming capacitor.
4
4
GND
Logic ground.
5
5
VFB
Feedback voltage input.
6
6
VCC
Logic supply voltage.
7
7
CS
Soft start and fault timing capacitor.
8
8
VC
Driver supply voltage.
FUNCTION
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3
CS51031
VC
VREF
RG
IC
Oscillator
COSC
7IC
VGATE
VGATE
Flip–Flop
+ Comparator
A1
–
G1
R
Q
F2
Q
2.5 V
–
VFB
Comparator
–
+
A6
+
0.7 V
–
+
+
–
VREF
3.3 V
–
Fault
Comp
+
G4
VREF = 3.3 V
1.15 V
CS Charge
Sense
Comparator
–
+
VCCOK
VCC
–
+
Hold Off
Comp
VCC
G3
+
A4
IT
CS
Comparator
+
A2
–
R
2.5 V
2.4 V
2.3 V
Q
F1
G5
–
+
1.5 V
–
+
IT
5
–
+
IT
55
–
+
CS
VFB
1.25 V
–
–
+
1.5 V
PGND
S
G2
–
A3
+
Slow Discharge
Comparator
S
Q
Slow Discharge
Flip–Flop
GND
Figure 2. Block Diagram
CIRCUIT DESCRIPTION
THEORY OF OPERATION
duration of the charge time. The PFET gets turned off and
remains off during the oscillator’s discharge time with the
maximum duty cycle to 80%. It requires 7.0 mV typical, and
20 mV maximum ripple on the VFB pin is required to
operate. This method of control does not require any loop
stability compensation.
Control Scheme
The CS51031 monitors and the output voltage to
determine when to turn on the PFET. If VFB falls below the
internal reference voltage of 1.25 V during the oscillator’s
charge cycle, the PFET is turned on and remains on for the
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4
CS51031
Startup
Lossless Short Circuit Protection
The CS51031 has an externally programmable soft start
feature that allows the output voltage to come up slowly,
preventing voltage overshoot on the output.
At startup, the voltage on all pins is zero. As VCC rises, the
VC voltage along with the internal resistor RG keeps the
PFET off. As VCC and VC continue to rise, the oscillator
capacitor (COSC ) and the Soft Start/Fault Timing capacitor
(CS) charges via internal current sources. COSC gets charged
by the current source IC and CS gets charged by the IT source
combination described by:
The CS51031 has “lossless” short circuit protection since
there is no current sense resistor required. When the voltage
at the CS pin (the fault timing capacitor voltage ) reaches
2.5 V during startup, the fault timing circuitry is enabled.
During normal operation the CS voltage is 2.6 V. During a
short circuit or a transient condition, the output voltage
moves lower and the voltage at VFB drops. If VFB drops
below 1.15 V, the output of the fault comparator goes high
and the CS51031 goes into a fast discharge mode. The fault
timing capacitor, CS, discharges to 2.4 V. If the VFB voltage
is still below 1.15 V when the CS pin reaches 2.4 V, a valid
fault condition has been detected. The slow discharge
comparator output goes high and enables gate G5 which sets
the slow discharge flip flop. The VGATE flip flop resets and
the output switch is turned off. The fault timing capacitor is
slowly discharged to 1.5 V. The CS51031 then enters a
normal startup routine. If the fault is still present when the
fault timing capacitor voltage reaches 2.5 V, the fast and
slow discharge cycles repeat as shown in figure 3.
If the VFB voltage is above 1.15 V when CS reaches
2.4 V a fault condition is not detected, normal operation
resumes and CS charges back to 2.6 V. This reduces the
chance of erroneously detecting a load transient as a fault
condition.
I
I
ICS IT T T
55
5
The internal Holdoff Comparator ensures that the external
PFET is off until VCS > 0.7 V, preventing the GATE flip–flop
(F2) from being set. This allows the oscillator to reach its
operating frequency before enabling the drive output. Soft
start is obtained by clamping the VFB comparator’s (A6)
reference input to approximately 1/2 of the voltage at the CS
pin during startup, permitting the control loop and the output
voltage to slowly increase. Once the CS pin charges above
the Holdoff Comparator trip point of 0.7 V, the low feedback
to the VFB Comparator sets the GATE flip–flop during
COSC ’s charge cycle. Once the GATE flip–flop is set,
VGATE goes low and turns on the PFET. When VCS exceeds
2.4 V, the CS charge sense comparator (A4) sets the VFB
comparator reference to 1.25 V completing the startup cycle.
2.6 V
VCS
S2
2.4 V
S2
S1
S3
S3
S1
2.5 V
S2
S3
S1
S3
1.5 V
0V
0V
TSTART
START
td1
NORMAL OPERATION
tFAULT
tRESTART
td2
FAULT
VGATE
1.25 V
1.15 V
VFB
Figure 3. Voltage on Start Capacitor (VGS), the Gate (VGATE), and in the
Feedback Loop (VFB), During Startup, Normal and Fault Conditions.
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tFAULT
CS51031
Buck Regulator Operation
and R2 and the reference voltage VREF, the power transistor
Q1 switches on and current flows through the inductor to the
output. The inductor current rises at a rate determined by
(VIN – VOUT)/L. The duty cycle (or “on” time) for the
CS51031 is limited to 80%. If output voltage remains higher
than nominal during the entire COSC change time, the Q1
does not turn on, skipping the pulse.
A block diagram of a typical buck regulator is shown in
Figure 4. If we assume that the output transistor is initially
off, and the system is in discontinuous operation, the
inductor current IL is zero and the output voltage is at its
nominal value. The current drawn by the load is supplied by
the output capacitor CO. When the voltage across CO drops
below the threshold established by the feedback resistors R1
L
Q1
VIN
R1
CIN
CO
D1
RLOAD
R2
Control
Feedback
Figure 4. Buck Regulator Block Diagram.
APPLICATIONS INFORMATION
CS51031 DESIGN EXAMPLE
DMAX 5.6 0.62
9.0
Specifications 12 V to 5.0 V, 3.0 A Buck Controller
• VIN = 12 V ±20% (i.e. 14.4 V max., 12 V nom., 9.6 V
•
•
•
•
•
DMIN 5.6 0.40
13.8
min.)
VOUT = 5.0 V ±2%
IOUT = 0.3 A to 3.0 A
Output ripple voltage < 50 mV max.
Efficiency > 80%
fSW = 200 kHz
2) Switching Frequency and On and Off Time
Calculations
Given that fSW = 200 kHz and DMAX = 0.80
T 1.0 5.0 s
fSW
1) Duty Cycle Estimates
TON(max) T DMAX 5.0 s 0.62 3.0 s
Since the maximum duty cycle D, of the CS51031 is
limited to 80% min., it is necessary to estimate the duty cycle
for the various input conditions over the complete operating
range.
The duty cycle for a buck regulator operating in a
continuous conduction mode is given by:
D
TON(min) T DMIN 5.0 s 0.40 2.0 s
TOFF(max) TON(min) 5.0 s 2.0 s 3.0 s
3) Oscillator Capacitor Selection
VOUT VF
VIN VSAT
The switching frequency is set by COSC, whose value is
given by:
where:
VSAT = Rds(on) × IOUT max. and Rds(on) is the value at TJ
100°C.
If VF = 0.60 V and VSAT = 0.60 V then the above equation
becomes:
COSC in pF http://onsemi.com
6
95 106
SW
3010
FSW 1 310
6
F
F
SW
3 2
CS51031
6) VFB Divider
4) Inductor Selection
The inductor value is chosen for continuous mode
operation down to 0.3 Amps.
The ripple current ∆I = 2 × IOUTmin = 2 × 0.3 A = 0.6 A.
L min (VOUT VD) TOFF(max)
I
I LMIN
5.0 V R1 R2 5.0 K
1.0 mA
5.6 V 2.0 s
0.4 A
28 H
Let R2 = 1.0 K
Rearranging the divider equation gives:
The core must not saturate with the maximum expected
current, here given by:
OUT 1.0 1.0 k5.0 V 1.0 3.0 k
V1.25
1.25
R1 R2
IMAX IOUT I2 3.0 A 0.4 A2 3.2 A
7) Divider Bypass Capacitor CRR
5) Output Capacitor
Since the feedback resistors divide the output voltage by
a factor of 4.0, i.e. 5.0 V/1.25 V= 4.0, it follows that the
output ripple is also divided by four. This would require that
the output ripple be at least 60 mV (4.0 × 15 mV) to trip the
feedback comparator. We use a capacitor CRR to act as an
AC short.
The ripple voltage frequency is equal to the switching
frequency so we choose CRR = 1.0 nF.
The output capacitor and the inductor form a low pass
filter. The output capacitor should have a low ESL and ESR.
Low impedance aluminum electrolytic, tantalum or organic
semiconductor capacitors are a good choice for an output
capacitor. Low impedance aluminum are less expensive.
Solid tantalum chip capacitors are available from a number
of suppliers and are the best choice for surface mount
applications.
The output capacitor limits the output ripple voltage. The
CS51031 needs a maximum of 20 mV of output ripple for
the feedback comparator to change state. If we assume that
all the inductor ripple current flows through the output
capacitor and that it is an ideal capacitor (i.e. zero ESR), the
minimum capacitance needed to limit the output ripple to
50 mV peak to peak is given by:
C
The input bias current to the comparator is 4.0 µA. The
resistor divider current should be considerably higher than
this to ensure that there is sufficient bias current. If we
choose the divider current to be at least 250 times the bias
current this permits a divider current of 1mA and simplifies
the calculations.
5.6 V 3.0 s
28 H
0.6 A
This is the minimum value of inductor to keep the ripple
current < 0.6 A during normal operation.
A smaller inductor will result in larger ripple current.
Ripple current at a minimum off time is
(VOUT VF) TOFF(min)
VOUT 1.25 V R1 R2 1.25 V R1 1.0
R2
R2
8) Soft Start and Fault Timing Capacitor CS
CS performs several important functions. First it provides
a delay time for load transients so that the IC does not enter
a fault mode every time the load changes abruptly. Secondly
it disables the fault circuitry during startup, it also provides
soft start by clamping the reference voltage during startup,
allowing it to rise slowly, and, finally it controls the hiccup
short circuit protection circuitry. This reduces the duty cycle
to approximately 0.035 during short circuit conditions.
An important consideration in calculating CS is that it’s
voltage does not reach 2.5 V (the voltage at which the fault
detect circuitry is enabled) before VFB reaches 1.15 V
otherwise the power supply will never start.
If the VFB pin reaches 1.15 V, the fault timing comparator
will discharge CS and the supply will not start. For the VFB
voltage to reach 1.15 V the output voltage must be at least
4 × 1.15 = 4.6 V.
If we choose an arbitrary startup time of 900 µs, the value
of CS is:
0.6 A
I
7.5F
8.0 fSW V
8.0 (200 103Hz) (50 103 V)
The minimum ESR needed to limit the output voltage
ripple to 50 mV peak to peak is:
3
ESR V 50 10
83 m
0.6 A
I
The output capacitor should be chosen so that its ESR is
less than 83 mΩ.
During the minimum off time, the ripple current is 0.4 A
and the output voltage ripple will be:
V ESR I 83m 0.4 33 mV
tStartup CS 2.5 V
ICharge
CS min http://onsemi.com
7
900 s 264 A
950 nF 0.1 F
2.5 V
CS51031
9) Input Capacitor
The fault time is the sum of the slow discharge time the
fast discharge time and the recharge time. It is dominated by
the slow discharge time.
The first parameter is the slow discharge time, it is the time
for the CS capacitor to discharge from 2.4 V to 1.5 V and is
given by:
tSlowDischarge(t) The input capacitor reduces the peak currents drawn from
the input supply and reduces the noise and ripple voltage on
the VCC and VC pins. This capacitor must also ensure that
the VCC remains above the UVLO voltage in the event of an
output short circuit. A low ESR capacitor of at least 100 µF
is good. A ceramic surface mount capacitor should also be
connected between VCC and ground to filter high frequency
noise.
CS (2.4 V 1.5 V)
IDischarge
where IDischarge is 6.0 µA typical.
10) MOSFET Selection
The CS51031 drives a P–channel MOSFET. The VGATE
pin swings from GND to VC. The type of PFET used
depends on the operating conditions but for input voltages
below 7.0 V a logic level FET should be used.
A PFET with a continuous drain current (ID) rating greater
than the maximum output current is required.
The Gate–to–Source voltage VGS and the Drain–to
Source Breakdown Voltage should be chosen based on the
input supply voltage.
The power dissipation due to the conduction losses is
given by:
tSlowDischarge(t) CS 1.5 105
The fast discharge time occurs when a fault is first
detected. The CS capacitor is discharged from 2.5 V to 2.4 V.
tFastDischarge(t) CS (2.5 V 2.4 V)
IFastDischarge
where IFastDischarge is 66 µA typical.
tFastDischarge(t) CS 1515
The recharge time is the time for CS to charge from 1.5 V
to 2.5 V.
tCharge(t) PD IOUT2 RDS(ON) D
CS (2.5 V 1.5 V)
ICharge
where
RDS(ON) is the value at TJ 100°C
where ICharge is 264 µA typical.
The power dissipation of the PFET due to the switching
losses is given by:
tCharge(t) CS 3787
PD 0.5 VIN IOUT (tr) fSW
The fault time is given by:
tFault CS (3787 1515 1.5 105)
where tr = Rise Time.
11) Diode Selection
tFault CS (1.55 105)
The flyback or catch diode should be a Schottky diode
because of it’s fast switching ability and low forward voltage
drop. The current rating must be at least equal to the
maximum output current. The breakdown voltage should be
at least 20 V for this 12 V application.
The diode power dissipation is given by:
For this circuit
tFault 0.1 106 1.55 105 15.5 s
A larger value of CS will increase the fault time out time
but will also increase the soft start time.
PD IOUT VD (1.0 D min)
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8
CS51031
ORDERING INFORMATION
Operating
Temperature Range
Package
Shipping
CS51031YD8
–40°C < TA < 85°C
SO–8
95 Units/Rail
CS51031YDR8
–40°C < TA < 85°C
SO–8
2500 Tape & Reel
CS51031YN8
–40°C < TA < 85°C
DIP–8
50 Units/Rail
CS51031GD8
0°C < TA < 70°C
SO–8
95 Units/Rail
CS51031GDR8
0°C < TA < 70°C
SO–8
2500 Tape & Reel
Device
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9
CS51031
PACKAGE DIMENSIONS
SO–8
D SUFFIX
CASE 751–07
ISSUE V
–X–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
A
8
5
0.25 (0.010)
S
B
1
M
Y
M
4
K
–Y–
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 SEATING
PLANE
–Z–
0.10 (0.004)
H
D
0.25 (0.010)
Z Y
M
X
S
M
J
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0
8
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0
8
0.010
0.020
0.228
0.244
DIP–8
N SUFFIX
CASE 626–05
ISSUE L
8
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5
–B–
1
4
DIM
A
B
C
D
F
G
H
J
K
L
M
N
F
–A–
NOTE 2
L
C
J
–T–
N
SEATING
PLANE
D
H
MILLIMETERS
MIN
MAX
9.40
10.16
6.10
6.60
3.94
4.45
0.38
0.51
1.02
1.78
2.54 BSC
0.76
1.27
0.20
0.30
2.92
3.43
7.62 BSC
--10
0.76
1.01
M
K
G
0.13 (0.005)
M
T A
M
B
M
PACKAGE THERMAL DATA
Parameter
SO–8
DIP–8
Unit
RΘJC
Typical
45
52
°C/W
RΘJA
Typical
165
100
°C/W
http://onsemi.com
10
INCHES
MIN
MAX
0.370
0.400
0.240
0.260
0.155
0.175
0.015
0.020
0.040
0.070
0.100 BSC
0.030
0.050
0.008
0.012
0.115
0.135
0.300 BSC
--10
0.030
0.040
CS51031
Notes
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11
CS51031
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CS51031/D