006 CY7C106 CY7C1006 256K x 4 Static RAM Features an active LOW output enable (OE), and three-state drivers. These devices have an automatic power-down feature that reduces power consumption by more than 65% when the devices are deselected. • High speed — tAA = 12 ns • CMOS for optimum speed/power • Low active power — 910 mW • Low standby power — 275 mW • 2.0V data retention (optional) — 100 µW • Automatic power-down when deselected • TTL-compatible inputs and outputs Writing to the devices is accomplished by taking chip enable (CE) and write enable (WE) inputs LOW. Data on the four I/O pins (I/O0 through I/O3) is then written into the location specified on the address pins (A0 through A17). Reading from the devices is accomplished by taking chip enable (CE) and output enable (OE) LOW while forcing write enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the four I/O pins. Functional Description The CY7C106 and CY7C1006 are high-performance CMOS static RAMs organized as 262,144 words by 4 bits. Easy memory expansion is provided by an active LOW chip enable (CE), The four input/output pins (I/O0 through I/O3) are placed in a high-impedance state when the devices are deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE and WE LOW). The CY7C106 is available in a standard 400-mil-wide SOJ; the CY7C1006 is available in a standard 300-mil-wide SOJ. Logic Block Diagram Pin Configuration SOJ Top View A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 CE OE GND I/O3 SENSE AMPS A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER INPUT BUFFER 512 x 512 x 4 ARRAY I/O2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A17 A16 A15 A14 A13 A12 A11 NC I/O3 I/O2 I/O1 I/O0 WE C106–2 I/O1 I/O0 POWER DOWN CE WE OE A0 A 10 A 11 A 12 A 13 A 14 A 15 A 16 A 17 COLUMN DECODER C106–1 Selection Guide Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (mA) 7C106-12 7C1006-12 12 165 7C106-15 7C1006-15 15 155 7C106-20 7C1006-20 20 145 7C106-25 7C1006-25 25 130 7C106-35 35 125 50 30 30 30 25 Cypress Semiconductor Corporation Document #: 38-05033 Rev. ** • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised July 9, 1998 CY7C106 CY7C1006 Maximum Ratings Current into Outputs (LOW) ........................................ 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Storage Temperature ................................. –65°C to +150°C Latch-Up Current..................................................... >200 mA Ambient Temperature with Power Applied............................................. –55°C to +125°C Operating Range Supply Voltage on VCC Relative to GND [1] .... –0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] ....................................–0.5V to VCC + 0.5V Ambient Temperature[2] 0°C to +70°C Range Commercial VCC 5V ± 10% DC Input Voltage[1] ................................–0.5V to VCC + 0.5V Electrical Characteristics Over the Operating Range Parameter Description Test Conditions 7C106-12 7C1006-12 7C106-15 7C1006-15 7C106-20 7C1006-20 Min. Min. Min. Max. 2.4 Max. VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage 2.2 VCC +0.3 2.2 VCC +0.3 VIL Input LOW Voltage[1] –0.3 0.8 –0.3 0.4 Max. 2.4 0.4 Unit V 0.4 V 2.2 VCC +0.3 V 0.8 –0.3 0.8 V IIX Input Load Current GND < VI < VCC –1 +1 –1 +1 –1 +1 µA IOZ Output Leakage Current GND < VI < VCC, Output Disabled –5 +5 –5 +5 –5 +5 µA IOS Output Short Circuit Current[3] VCC = Max., VOUT = GND –300 –300 –300 mA ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC 165 155 140 mA ISB1 Automatic CE Power-Down Current —TTL Inputs Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX 50 30 30 mA ISB2 Automatic CE Power-Down Current —CMOS Inputs Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V, f=0 Com’l 10 10 10 mA L 2 2 2 Notes: 1. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 2. TA is the “instant on” case temperature. 3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. Document #: 38-05033 Rev. ** Page 2 of 9 CY7C106 CY7C1006 Electrical Characteristics Over the Operating Range (continued) 7C106-25 7C1006-25 Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage Min. 7C106-35 Max. Min. 2.4 0.4 [1] Max. Unit 2.4 V 0.4 V V 2.2 VCC + 0.3 2.2 VCC + 0.3 VIL Input LOW Voltage –0.3 0.8 –0.3 0.8 V IIX Input Load Current GND < VI < VCC –1 +1 –1 +1 µA IOZ Output Leakage Current GND < VI < VCC, Output Disabled –5 +5 –5 +5 µA IOS Output Short Circuit Current[3] VCC = Max., VOUT = GND –300 –300 mA ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC 130 125 mA ISB1 Automatic CE Power-Down Current —TTL Inputs Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX 30 25 mA ISB2 Automatic CE Power-Down Current —CMOS Inputs Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V, f=0 Com’l 10 10 mA L 2 2 Capacitance[4] Parameter CIN: Addresses CIN: Controls COUT Description Input Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 7 10 10 Output Capacitance Unit pF pF pF Note: 4. Tested initially and after any design or process changes that may affect these parameters. AC Test Loads and Waveforms R1 480 Ω R1 480 Ω 5V 5V OUTPUT OUTPUT R2 255Ω 30 pF INCLUDING JIG AND SCOPE ALL INPUT PULSES 3.0V 90% R2 255Ω 5 pF INCLUDING JIG AND SCOPE (a) Equivalent to: OUTPUT (b) C106–3 GND < 3 ns 10% 90% 10% < 3 ns C106–4 THÉVENIN EQUIVALENT 167Ω Document #: 38-05033 Rev. ** 1.73V Page 3 of 9 CY7C106 CY7C1006 Switching Characteristics Over the Operating Range[5] Parameter Description 7C106-12 7C1006-12 7C106-15 7C1006-15 7C106-20 7C1006-20 7C106-25 7C1006-25 Min. Min. Min. Min. Max. Max. Max. Max. 7C106-35 Min. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 12 15 20 tDOE OE LOW to Data Valid 6 7 8 tLZOE OE LOW to Low Z tHZOE OE HIGH to High Z[6,7] tLZCE CE LOW to Low Z 12 15 12 3 3 0 [7] 3 tHZCE CE HIGH to High Z tPU CE LOW to Power-Up tPD CE HIGH to Power-Down 6 7 12 25 35 ns 10 10 ns 3 ns 10 3 10 0 20 ns 0 10 8 15 ns 3 0 ns 35 0 8 3 0 35 25 3 0 7 3 0 25 20 3 0 6 [6,7] 20 15 ns 10 0 25 ns ns ns 35 ns WRITE CYCLE[8,9] tWC Write Cycle Time 12 15 20 25 35 ns tSCE CE LOW to Write End 10 12 15 20 25 ns tAW Address Set-Up to Write End 10 12 15 20 25 ns tHA Address Hold from Write End 0 0 0 0 0 ns tSA Address Set-Up to Write Start 0 0 0 0 0 ns tPWE WE Pulse Width 10 12 15 20 25 ns tSD Data Set-Up to Write End 7 8 10 15 20 ns tHD Data Hold from Write End 0 0 0 0 0 ns 2 3 3 3 3 ns tLZWE tHZWE [7] WE HIGH to Low Z WE LOW to High Z [6,7] 6 7 8 10 10 ns Notes: 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30–pF load capacitance. 6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. The internal write time of the memory is defined by the overlap of CE and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05033 Rev. ** Page 4 of 9 CY7C106 CY7C1006 Data Retention Characteristics Over the Operating Range (L Version Only) Parameter Conditions[10] Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR[4] Chip Deselect to Data Retention Time tR[4] Operation Recovery Time Min. Max. 2.0 VCC = VDR = 2.0V, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V Unit V 50 µA 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE 4.5V VCC 4.5V VDR > 2V tR tCDR CE C106–5 Switching Waveforms Read Cycle No.1[11, 12] 1 tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID C106–6 [12, 13] Read Cycle No. 2 (OE Controlled) ADDRESS tRC CE tACE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZCE HIGH IMPEDANCE DATA VALID tPD tPU 50% ICC 50% ISB C106–7 Notes: 10. No input may exceed VCC +0.5V. 11. Device is continuously selected, OE and CE = VIL. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW. Document #: 38-05033 Rev. ** Page 5 of 9 CY7C106 CY7C1006 Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[14, 15] tWC ADDRESS tSCE CE tSA tHA tAW tPWE WE tSD DATA I/O tHD DATA VALID C106A–8 Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14, 15] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE OE tSD DATA I/O tHD DATA VALID tHZOE C106–9 Notes: 14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 15. Data I/O is high impedance if OE = VIH. Document #: 38-05033 Rev. ** Page 6 of 9 CY7C106 CY7C1006 Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW)[9, 15] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tHD tSD DATA I/O DATA VALID tLZWE tHZWE C106–10 Truth Table CE OE WE Input/Output Mode Power H X X High Z Power-Down Standby (ISB) L L H Data Out Read Active (ICC) L X L Data In Write Active (ICC) L H H High Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) 12 15 20 25 35 Ordering Code CY7C106–12VC CY7C1006–12VC CY7C106–15VC CY7C1006–15VC CY7C106–20VC CY7C1006–20VC CY7C106–25VC CY7C1006–25VC CY7C106–35VC Package Name V28 V21 V28 V21 V28 V21 V28 V21 V28 Package Type 28-Lead (400-Mil) Molded SOJ 28-Lead (300-Mil) Molded SOJ 28-Lead (400-Mil) Molded SOJ 28-Lead (300-Mil) Molded SOJ 28-Lead (400-Mil) Molded SOJ 28-Lead (300-Mil) Molded SOJ 28-Lead (400-Mil) Molded SOJ 28-Lead (300-Mil) Molded SOJ 28-Lead (400-Mil) Molded SOJ Operating Range Commercial Commercial Commercial Commercial Commercial Contact factory for “L” version availability. Document #: 38-05033 Rev. ** Page 7 of 9 CY7C106 CY7C1006 Package Diagrams 28-Lead (300-Mil) Molded SOJ V21 51-85031-B 28-Lead (400-Mil) Molded SOJ V28 51-85032-A Document #: 38-05033 Rev. ** Page 8 of 9 © Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C106 CY7C1006 Document Title: CY7C106, CY7C1006 256K x 4 Static RAM Document Number: 38-05033 REV. ECN NO. Issue Date Orig. of Change ** 106827 06/12/01 SZV Document #: 38-05033 Rev. ** Description of Change Change from Spec #: 38-00230 to 38-05033 Page 9 of 9