846 CYM1846 512K x 32 Static RAM Module Features • High-density 16-megabit SRAM module • 32-bit standard footprint supports from 16Kx32 through 1Mx32 • High-speed SRAMs — Access time of 12 ns • Low active power — 4.4W (max.) at 12 ns • Compatible with CYM1821, CYM1831, CYM1836, CYM1841, and CYM1851 JEDEC modules • Available in 72-pin ZIP or SIMM/Angled SIMM Functional Description The CYM1846 is a high-performance 16-megabit static RAM module organized as 512K words by 32 bits. This module is constructed from four 512K x 8 SRAMs in SOJ packages mounted on an epoxy laminate substrate. Four chip selects are used to independently enable the four bytes. Reading or writing can be executed on individual bytes or any combination of multiple bytes through proper use of the chip selects. The CYM1846 is designed for use with standard 72-pin SIMM socket and ZIP footprint. The pinout is compatible with the 64-pin JEDEC ZIP/SIMM module family (CYM1821, CYM1831, CYM1836, and CYM1841) and the 72-pin CYM1851. Thus, a single motherboard design can be used to accommodate memory depth ranging from 16K words (CYM1821) to 1024K words (CYM1851). The standard SIMM can be used in Angled SIMM sockets and is available with either tin-lead or 10 micro-inches of gold flash on the edge contacts. Presence detect pins (PD 0 – PD 3) are used to identify module memory density in applications where modules with alternate word depths can be interchanged. Logic Block Diagram Pin Configuration PD0 – PD1 – PD2 – PD3 – A0 – A18 OPEN OPEN GND OPEN 19 OE WE 512Kx8 SRAM 8 512Kx8 SRAM 8 I/O0 – I/O7 CS1 I/O8 – I/O15 CS2 512Kx8 SRAM 8 512Kx8 SRAM 8 I/O16 – I/O23 CS3 I/O24 – I/O31 CS4 Cypress Semiconductor Corporation • 3901 North First Street • ZIP/SIMM Top View NC PD3 PD0 I/O0 I/O1 I/O2 I/O3 VCC A7 A8 A9 I/O4 I/O5 I/O6 I/O7 WE A14 CS1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 CS3 A16 GND I/O16 I/O17 I/O18 I/O19 A10 A11 A12 A13 I/O20 I/O21 I/O22 I/O23 GND NC NC 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 33 35 NC PD2 GND PD1 I/O8 I/O9 I/O10 I/O11 A0 A1 A2 I/O12 I/O13 I/O14 I/O15 GND A15 CS2 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 CS4 A17 OE I/O24 I/O25 I/O26 I/O27 A3 A4 A5 VCC A6 I/O28 I/O29 I/O30 I/O31 A18 NC 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 1846–1 San Jose • CA 95134 • 408-943-2600 December 1994 - Revised October 10, 1997 CYM1846 Selection Guide Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (mA) 1846–12 12 800 240 1846–15 15 800 240 1846–20 20 800 240 1846–25 25 800 240 1846–35 35 800 240 Shaded area contains preliminary information. Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) DC Input Voltage ............................................–0.5V to +7.0V Storage Temperature ................................. –55°C to +125°C Operating Range Ambient Temperature with Power Applied ............................................... –10°C to +85°C Range Ambient Temperature VCC Supply Voltage to Ground Potential ............... –0.5V to +7.0V Commercial 0°C to +70°C 5V ± 10% DC Voltage Applied to Outputs in High Z State ................................................ –0.5V to +VCC Electrical Characteristics Over the Operating Range Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage VIL Input LOW Voltage IIX Input Load Current IOZ Min. Max. Unit 2.4 V 0.4 V 2.2 VCC + 0.3 V –0.5 0.8 V GND ≤ VI ≤ V CC –10 +10 µA Output Leakage Current GND ≤ VO ≤ VCC, Output Disabled –10 +10 µA ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, CSN ≤ VIL 800 mA ISB1 Automatic CS Power-Down Current[1] Max. VCC, CS ≥ VIH, Min. Duty Cycle = 100% 240 mA ISB2 Automatic CS Power-Down Current[1] Max. VCC, CS ≥ VCC – 0.2V, VIN ≥ V CC – 0.2V, or V IN ≤ 0.2V −20, −25, 35 40 mA −12, −15 120 mA Capacitance[2] Parameter Description CINA Input Capacitance (WE, OE, A0–18) CINB Input Capacitance (CS) COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. Unit 40 pF 20 pF 20 pF Note: 1. A pull-up resistor to VCC on the CS input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given. 2. Tested on a sample basis. 2 CYM1846 AC Test Loads and Waveforms R1 481 Ω 5V OUTPUT R2 255 Ω 30 pF R1 481 Ω 5V ALL INPUT PULSES 3.0V OUTPUT R2 255 Ω 5 pF INCLUDING JIG AND SCOPE Equivalent to: OUTPUT 90% GND 10% ≤ 5 ns INCLUDING JIG AND SCOPE (a) 90% 10% ≤ 5 ns 1846–2 (b) 1846–3 THÉVENIN EQUIVALENT 167 Ω 1.73V Switching Characteristics Over the Operating Range[3] 1846–12 Parameter Min. Description 1846–15 Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 12 15 tAA Address to Data Valid tOHA Data Hold from Address Change tACS CS LOW to Data Valid 12 15 ns tDOE OE LOW to Data Valid 7 8 ns tLZOE OE LOW to Low Z tHZOE OE HIGH to High Z tLZCS CS LOW to Low Z[4] tHZCS CS HIGH to High Z[4, 5] 7 8 ns tPD CS HIGH to Power-Down 12 15 ns 12 3 ns 15 3 0 ns 0 7 3 ns ns 8 3 ns ns WRITE CYCLE[6] tWC Write Cycle Time 12 15 ns tSCS CS LOW to Write End 9 10 ns tAW Address Set-Up to Write End 9 10 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-Up to Write Start 1 1 ns tPWE WE Pulse Width 10 12 ns tSD Data Set-Up to Write End 7 8 ns tHD Data Hold from Write End 1 1 ns tLZWE WE HIGH to Low Z 3 3 ns tHZWE WE LOW to High Z[5] 0 Shaded area contains preliminary information. 3 7 0 8 ns CYM1846 4 CYM1846 Switching Characteristics Over the Operating Range[3] (continued) 1846–20 Parameter Description Min. Max. 1846–25 Min. Max. 1846–35 Min. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACS CS LOW to Data Valid 20 25 35 ns tDOE OE LOW to Data Valid 10 15 25 ns tLZOE OE LOW to Low Z tHZOE OE HIGH to High Z tLZCS tHZCS tPD WRITE CYCLE CS LOW to Low Z 20 25 20 3 CS HIGH to High Z 25 3 0 3 [4, 5] CS HIGH to Power-Down ns 35 3 0 10 [4] 35 ns 0 12 3 ns ns 12 3 ns ns 10 12 12 ns 20 25 35 ns [6] tWC Write Cycle Time 20 25 35 ns tSCS CS LOW to Write End 15 20 30 ns tAW Address Set-Up to Write End 15 20 30 ns tHA Address Hold from Write End 0 0 0 ns tSA Address Set-Up to Write Start 1 2 2 ns tPWE WE Pulse Width 15 20 30 ns tSD Data Set-Up to Write End 10 15 20 ns tHD Data Hold from Write End 1 2 2 ns tLZWE WE HIGH to Low Z 3 4 5 ns tHZWE [6] WE LOW to High Z 0 10 0 12 0 12 ns Notes: 3. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I OL/IOH and 30-pF load capacitance. 4. At any given temperature and voltage condition, tHZCS is less than tLZCS for any given device. These parameters are guaranteed and not 100% tested. 5. t HZCS and t HZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage. 6. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 5 CYM1846 Switching Waveforms Read Cycle No. 1 [7, 8] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID 1846–4 Read Cycle No. 2 [7, 9] tRC CS tACS OE tHZOE tDOE tHZCS tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID DATA OUT tLZCS tPD tPU ICC V CC SUPPLY CURRENT 50% 50% ISB 1846–5 Write Cycle No. 1 (WE Controlled) [6] tWC ADDRESS tSCS CS tAW tHA tSA tPWE WE tSD DATA IN DATA VALID tHZWE DATA OUT tHD tLZWE HIGH IMPEDANCE DATA UNDEFINED 1846–6 Notes: 7. WE is HIGH for read cycle. 8. Device is continuously selected, CS = VIL, and OE= VIL. 9. Address valid prior to or coincident with CS transition LOW. 6 CYM1846 Switching Waveforms (continued) Write Cycle No. 2 (CS Controlled) [6, 10] tWC ADDRESS tSCS CS tAW tSA tHA tPWE WE tSD DATAIN tHD DATA VALID tHZWE tLZWE HIGH IMPEDANCE DATAOUT DATA UNDEFINED Note: 10. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. Truth Table CS WE OE Inputs/Output Mode H X X High Z Deselect/Power-Down L H L Data Out Read L L X Data In Write L H H High Z Deselect Ordering Information Speed (ns) 12 15 20 25 35 Ordering Code Package Type Package Type Operating Range Commercial CYM1846PM–12C PM21 72-Pin Plastic SIMM Module CYM1846P8–12C PM21 72-Pin Plastic SIMM Module (gold contacts) CYM1846PZ–12C PZ11 72-Pin Plastic ZIP Module CYM1846PM–15C PM21 72-Pin Plastic SIMM Module CYM1846P8–15C PM21 72-Pin Plastic SIMM Module (gold contacts) CYM1846PZ–15C PZ11 72-Pin Plastic ZIP Module CYM1846PM–20C PM21 72-Pin Plastic SIMM Module CYM1846P8–20C PM21 72-Pin Plastic SIMM Module (gold contacts) CYM1846PZ–20C PZ11 72-Pin Plastic ZIP Module CYM1846PM–25C PM21 72-Pin Plastic SIMM Module CYM1846P8–25C PM21 72-Pin Plastic SIMM Module (gold contacts) CYM1846PZ–25C PZ11 72-Pin Plastic ZIP Module CYM1846PM–35C PM21 72-Pin Plastic SIMM Module CYM1846P8–35C PM21 72-Pin Plastic SIMM Module (gold contacts) CYM1846PZ–35C PZ11 72-Pin Plastic ZIP Module Commercial Commercial Commercial Commercial © Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CYM1846 Ordering Information Speed (ns) Ordering Code Package Type Package Type Shaded area contains preliminary information. Document #: 38–M–00073–B Package Diagrams 72-Pin Plastic SIMM Module PM21 72-Pin Plastic ZIP Module PZ11 8 Operating Range