CYM26KAH24AV33 PRELIMINARY 256K x 24 Static RAM Module Features Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data from I/O pins (I/O0 through I/O23), is written into the location specified on the address pins (A0 through A17). • High-density 6-Megabit SRAM Module • High-speed CMOS SRAMs — tAA = 10 ns • Single 3.3V power supply • Low active power(648 W at 10 ns) • TTL-compatible Inputs and Outputs • Available in standard 119-ball BGA Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. Then data from the memory location specified by the address pins will appear on I/O0 to I/O23. See the truth table at the back of this data sheet for a complete description of Read and Write modes. Functional Description The CYM26KAH24AV33 is a 3.3V high-performance 6-Megabit static RAM organized as a 256K words by 24 bits. This module is constructed from two SRAM dies mounted on a multilayer laminate substrate combined to form a 24-bit SRAM. The input/output pins (I/O0 through I/O23) are placed in a high-impedance state when the device is deselected (CEHIGH), and the outputs are disabled (OE HIGH), or during a Write operation (CE LOW, and WE LOW). The CYM26KAH24AV33 is available in a standard 119 BGA. Functional Block Diagram A[17:0] CE0/ WE0/ OE0/ A[17:0] I/O0-11 I/O0-11 A[17:0] CE/ WE/ OE/ CE1/ WE1/ OE1/ I/O12-23 I/O0-23 I/O12-23 Selection Guide Maximum Access Time Maximum Operating Current Maximum Standby Current Cypress Semiconductor Corporation Document #: 38-05324 Rev. ** • -10 -12 Unit 10 12 ns Commercial 180 170 mA Industrial 200 190 mA Commercial Industrial 20 20 mA 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised January 17, 2003 CYM26KAH24AV33 PRELIMINARY Pin Configurations 119 BGA Top View 1 2 3 4 5 6 7 A NC A A A A A NC B NC A A CE A A NC A NC[1] NC I/011 C I/O12 NC NC[1] D I/O13 VCC VSS VSS VSS VCC I/O10 E I/O14 NC VCC VSS VCC NC I/O9 F I/O15 VCC VSS VSS VSS VCC I/O8 G I/O16 NC VCC VSS VCC NC I/O7 H I/O17 VCC VSS VSS VSS VCC I/O6 J VCC VSS VCC VSS VCC VSS VDD K I/O18 VCC VSS VSS VSS VCC I/O5 L I/O19 NC VCC VSS VCC NC I/O4 M I/O20 VCC VSS VSS VSS VCC I/O3 N I/O21 NC VCC VSS VCC NC I/O2 P I/O22 VCC VSS VSS VSS VCC I/O1 R I/O23 NC NC NC NC NC I/O0 T NC A A WE A A NC U NC A A OE A A NC Note: 1. Bumps 3C and 5C are actually NC’s but they should be wired 3C to VCC and 5C to Vss to assure compatibility with future versions. Document #: 38-05324 Rev. ** Page 2 of 8 CYM26KAH24AV33 PRELIMINARY Current into Outputs (LOW)......................................... 20 mA Maximum Ratings Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Latch-up Current..................................................... > 200 mA Storage Temperature ................................ –65°C to +150°C Operating Range Ambient Temperature with Power Applied .. –55°C to +125°C Supply Voltage on VCC to Relative GND[2] ...... –0.5V to 4.6V Range DC Voltage Applied to Outputs in High-Z State[2] ....................................–0.5V to VCC + 0.5V Commercial Ambient Temperature VCC 0°C to +70°C 3.3V ±5% –40°C to +85°C 3.3V ±5% Industrial DC Input Voltage[2] .................................–0.5V to VCC + 0.5V Electrical Characteristics Over the Operating Range -10 Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage VIL Input LOW Voltage[2] IIX Input Load Current GND < VI < VCC IOZ Output Leakage Current GND < VI < VCC, Output Disabled ICC VCC Operating Supply Current VCC = Max. f = fMAX = 1/tRC ISB1 Automatic CE Power-down Current —TTL Inputs Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX ISB2 Automatic CE Power-down Current —CMOS Inputs Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 Min. -12 Max. Min. 2.4 Max. Unit 2.4 V 0.4 0.4 V V 2.0 VCC + 0.3 2.0 VCC + 0.3 –0.3 0.8 -0.3 0.8 V –2 +2 -2 +2 µA –2 +2 -2 +2 µA Commercial 180 170 mA Industrial 200 190 mA 80 80 mA 20 20 mA Commercial/ Industrial Capacitance[2] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max. Unit 10 pF 8 pF AC Test Loads and Waveforms R1 317 Ω UTPUT ALL INPUT PULSES 3.0V 3.3V Z0 = 50Ω 90% OUTPUT RL = 50Ω 5 pF VTH = 1.5V (a) INCLUDING JIG AND (b) SCOPE R2 351Ω GND ≤ 3 ns 10% 90% 10% ≤ 3 ns Note: 2. VIL (min.) = –2.0V for pulse durations of less than 20 ns. Document #: 38-05324 Rev. ** Page 3 of 8 CYM26KAH24AV33 PRELIMINARY AC Switching Characteristics[3] Over the Operating Range -10 Parameter Description Min. -12 Max. Min. Max. Unit Read Cycle tRC Read Cycle Time tAA Address to Data Valid 10 tOHA Data Hold from Address Change tACE CE active to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to Low Z tHZOE OE HIGH to High Z[4, 5] tLZCE CE active to Low Z[5] tHZCE CE inactive to High Z[4, 5] tPU CE active to Power-Up tPD CE inactive to Power-Down 12 10 3 ns 12 ns 12 ns 3 10 5 0 ns 6 0 5 3 6 3 5 0 ns ns 6 0 10 ns ns ns ns 12 ns Write Cycle[6, 7] tWC Write Cycle Time 10 12 ns tSCE CE active to Write End 7 8 ns tAW Address Set-Up to Write End 7 8 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-Up to Write Start 0 0 ns tPWE WE Pulse Width 7 8 ns tSD Data Set-Up to Write End 5 6 ns tHD Data Hold from Write End 0 0 ns tLZWE WE HIGH to Low Z[5] 3 3 ns tHZWE WE LOW to High Z[4, 5] 4 5 ns Switching Waveforms Read Cycle No. 1[8, 9] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Notes: 3. Tested initially and after any design or process changes that may affect these parameters. 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH. 5. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 8. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 9. Device is continuously selected. OE, CE = VIL. Document #: 38-05324 Rev. ** Page 4 of 8 CYM26KAH24AV33 PRELIMINARY Switching Waveforms (continued) Read Cycle No. 2 (OE Controlled)[10, 11] ADDRESS tRC CE tACE OE tHZOE tDOE DATA OUT tHZCE tLZOE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU ICC 50% 50% ISB Write Cycle No. 1 (CE Controlled)[12, 13] tWC ADDRESS tSCE CE tSA tSCE tHA tAW tPWE WE tSD DATA I/O tHD DATA VALID Notes: 10. WE is HIGH for read cycle. 11. Address valid prior to or coincident with CE transition LOW. 12. Data I/O is high impedance if OE = VIH. 13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05324 Rev. ** Page 5 of 8 CYM26KAH24AV33 PRELIMINARY Switching Waveforms (continued) Write Cycle No. 2 (WE Controlled, OE HIGH During Write) tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE OE tSD DATA I/O tHD DATAIN VALID Note 14 tHZOE Write Cycle No. 3 (WE Controlled, OE LOW) tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATA I/O Note 14 tHD DATA VALID tLZWE tHZWE Ordering Information Speed (ns) Ordering Code Package Name Package Type Operating Range 10 CYM26KAH24AV33-10BGC BG119 119-Ball BGA Commercial 10 CYM26KAH24AV33-10BGI BG119 119-Ball BGA Industrial 12 CYM26KAH24AV33-12BGC BG119 119-Ball BGA Commercial 12 CYM26KAH24AV33-12BGI BG119 119-Ball BGA Industrial Note: 14. During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05324 Rev. ** Page 6 of 8 PRELIMINARY CYM26KAH24AV33 Package Diagram 119-lead PBGA (14 x 22 x 2.4 mm) BG119 51-85115-*B All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05324 Rev. ** Page 7 of 8 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY CYM26KAH24AV33 Document History Page Document Title: CYM26KAH24AV33 256K x 24 Static RAM Module Document Number: 38-05324 REV. ECN NO. Issue Date Orig. of Change ** 123014 01/22/03 CS Document #: 38-05324 Rev. ** Description of Change New Data Sheet Page 8 of 8