ETC DS21Q55DK

DS21Q55DK
Quad T1/E1/J1 Transceiver Design Kit
Daughter Card
www.maxim-ic.com
GENERAL DESCRIPTION
FEATURES
The DS21Q55DK is an easy-to-use evaluation board
for the DS21Q55 quad T1/E1/J1 transceiver. The
DS21Q55DK is intended to be used as a daughter
card with the DK101 motherboard or the DK2000
motherboard. The DS21Q55DK comes complete with
a DS21Q55 quad SCT, transformers, termination
resistors, configuration switches, line-protection
circuitry, network connectors, and motherboard
connectors. The DK101/DK2000 motherboard and
Dallas’ ChipView software give point-and-click
access to configuration and status registers from a
Windowsâ-based PC. On-board LEDs indicate
receive loss-of-signal and interrupt status. An onboard FPGA contains mux logic to connect framer
ports to one another or to the DK2000 in a variety of
configurations.
§
§
§
§
§
§
§
§
Each DS21Q55DK is shipped with a free DK101
motherboard. For complex applications, the DK2000
high-performance demo kit motherboard can be
purchased separately.
§
Windows is a registered trademark of Microsoft Corp.
DESIGN KIT CONTENTS
ORDERING INFORMATION
PART
DS21Q55DK
Demonstrates Key Functions of DS21Q55 Quad
T1/E1/J1 Transceiver
Includes DS21Q55 Quad LIU, Transformers,
BNC, and RJ45 Network Connectors and
Termination Passives
Compatible with DK101 and DK2000 Demo Kit
Motherboards
DK101/DK2000 and ChipView Software Provide
Point-and-Click Access to the DS21Q55 Register
Set
All Equipment-Side Framer Pins are Easily
Accessible for External Data Source/Sink
Memory-Mapped FPGA Provides Flexible
Clock/Data/Sync Connections Among Framer
Ports and DK2000 Motherboard
LEDs for Loss-of-Signal and Interrupt Status
Easy-to-Read Silk-Screen Labels Identify the
Signals Associated with All Connectors, Jumpers
and LEDs
Network Interface Protection for Overvoltage and
Overcurrent Events
DS21Q55DK Design Kit Daughter Card
DK101 Low-Cost Motherboard
CD-ROM
ChipView Software
DS21Q55DK Data Sheet
DK101 Data Sheet
DS21Q55 Data Sheet
DS21Q55 Errata Sheet
DESCRIPTION
DS21Q55 Demo Kit Daughter Card
(with included DK101 Motherboard)
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DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit
COMPONENT LIST
DESIGNATION
QTY
C1–C8
8
0.22mF, 50V capacitors
Phycomp
PCF1150CT-ND
23
0.1mF 10%, 16V ceramic capacitors (0603)
Phycomp
06032R104K7B20D
4
0.1mF 10%, 25V ceramic capacitors (1206)
Panasonic
ECJ-3VB1E104K
8
1mF 10%, 16V ceramic capacitors (1206)
Panasonic
ECJ-3YB1C105K
2
1
1
5
16
1
8
1
2
1
3
10mF 20%, 10V ceramic capacitors (1206)
Quad port choke
LED, red, SMD
LED, green, SMD
1.25A, 250V fuse, SMT
10-pin, dual row, vertical jumper
5-pin connectors, BNC right-angle vertical
8-pin 4-port jack, right-angle RJ45
50-pin socket, SMD, dual row, vertical
12-pin connector, dual row, vertical
10kW 1%, 1/10W resistors (0805)
Panasonic
Pulse
Panasonic
Panasonic
Teccor
Digi-Key
Cambridge
Molex
Samtec
Digi-Key
Panasonic
ECJ-3YB1A106M
TX1473
LN1251C
LN1351C
F1250T
S2012-05-ND
CP-BNCPC-004
43223-8140
TFM-125-02-S-D-LC
S2012-06-ND
ERJ-6ENF1002V
5
10kW 5%, 1/10W resistors (0805)
Panasonic
ERJ-6GEYJ103V
17
0W 5%, 1/8W resistors (1206)
Panasonic
ERJ-8GEYJ0R00V
R13
1
470W 5%, 1/10W resistor (0805)
Panasonic
ERJ-6GEYJ471V
R22–R25
4
51.1W 1%, 1/10W resistors (0805)
Panasonic
ERJ-6ENF51R1V
R27, R28, R38
3
1.0kW 1%, 1/10W resistors (0805)
Panasonic
ERJ-6ENF1001V
R29–R36
8
61.9W 1%, 1/8W resistors (1206)
Panasonic
ERJ-8ENF61R9V
R37, R47
2
Not populated
Panasonic
Not populated
R40, R42–R44,
R46, R49
6
330W 0.1%, 1/10W MF resistors (0805)
Panasonic
ERA-6YEB331V
SW1–SW4
4
6-PIN TH Switch DPDT
Tyco
SSA22
T1
1
XFMR, XMIT/RCV, 1 to 2, SMT 32-pin
Pulse
TX1473
U1
1
XILINX spartan 2.5V FPGA
144-pin, 20 x 20 TQFP
Xilinx
XC2S50-5TQ144C
U2
1
Quad T1/E1/J1 transceiver
256-pin BGA, 0°C to +70°C
multichip module
Dallas
Semiconductor
DS21Q55
U3
1
1M PROM for FPGA 44-pin TQFP
Xilinx
XC18V01VQ44C_U
U4
1
8-pin mMAX, SO
2.5V or ADJ
Maxim
MAX1792EUA25
U20
1
Serial configuration EEPROM for XILINX
65kb, 8-DIP
Atmel
AT17LV65EUA-NOPOP
Z1–Z8
8
50A, 6V Sidactor, DO214 SMD
Teccor
P0080SAMC
Z9–Z16
8
500A, 25V Sidactor, DO214 SMD
Teccor
P0300SCMC
Z17–Z32
16
500A, 170V Sidactor, DO214 SMD
Teccor
P1800SCMC
C9, C10, C12, C18,
C22–C33, C35,
C38–C43
C11, C13–C15
C16, C17, C19–C21,
C34, C36, C45
C37, C44
CH1
DS1
DS2–DS6
F1–F16
J1
J2–J9
J10
J11, J12
J13
R1, R2, R4
R3, R26, R39, R41,
R45
R5–R12, R14–R21,
R48
DESCRIPTION
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SUPPLIER
PART
DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit
FPGA
RLOS 1-4 LEDs
FPGA
STATUS
LED
JTAG
FPGA
CONFIG
PROM
QUAD PORT
CHOKE
QUAD PORT
TRANSFORMER
CPU INTERFACE
INT LED
CPU INTERFACE
DS21Q55
PCM BUS
TEST POINTS
IMPEDANCE
MATCHING/
LINE
PROTECTION
2.5V FPGA
SUPPLY
LINE
PROTECTION
PORT 4
BNC
PORT
4
LINE
PROTECTION
PORT 3
BNC
PORT
3
LINE
PROTECTION
PORT 2
BNC
PORT
2
LINE
PROTECTION
PORT 1
BNC
PORT
1
ERRATA
·
·
Connector J1 has silk-screen mislabeled such that the text TMS and TCK should be swapped. Worded
differently, TCK belongs to pin 7 and TMS belongs to pin 9.
Switches SW1 to SW4 are missing silk screen to indicate which side is grounded. Sliding the switch toward the
BNC grounds the BNC shell (E1 mode). For T1 mode the switch should be slid away from the BNC.
BASIC OPERATION
This design kit relies upon several supporting files, which are available for downloading on our website at
www.maxim-ic.com/telecom. See the DS21Q55DK QuickView data sheet for these files.
Hardware Configuration
Using the DK101 Processor Board:
·
·
·
·
Connect the daughter card to the DK101 processor board.
Supply 3.3V to the banana-plug receptacles marked GND and VCC_3.3V. (The external 5V connector is
unused. Additionally, the ‘TIM 5V supply’ headers are unused.)
All processor board DIP-switch settings should be in the ON position with exception of the flash-programming
switch, which should be OFF.
From the Programs menu, launch the host application named ChipView.EXE. Run the ChipView application. If
the default installation options were used, click the Start button on the Windows toolbar and select Programs ®
ChipView ® ChipView.
Using the DK2000 Processor Board:
·
·
·
Connect the daughter card to the DK2000 processor board.
Connect J1 to the power supply that is delivered with the kit. Alternately, a PC power supply may be connected
to connector J2.
From the Programs menu, launch the host application named ChipView.EXE. Run the ChipView application. If
the default installation options were used, click the Start button on the Windows toolbar and select Programs ®
ChipView ® ChipView.
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BOARD FLOORPLAN
DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit
General
·
·
Upon power-up, the RLOS LEDs (green) will not be lit, the INT LED (red) will not be lit, but the FPGA status
LED (green) will be lit.
When operating in E1 mode, slide SW1–SW4 such that the BNC shell is grounded (to the left, as shown in the
board floorplan). When operating in T1 mode, ensure that SW1–SW4 are slid to the right as shown in the
board floorplan.
Miscellaneous
·
·
·
Clock frequencies and certain pin bias levels are provided by a register-mapped FPGA, which is on the
DS21Q55 daughter card.
The definition file for this FPGA is named DS21Q55DC_FPGA.def. The definitions are located on page 6. A
drop-down menu on the top of the screen allows for switching between definition files.
All files referenced above are available for download as described in the section marked “BASIC OPERATION”
QUICK SETUP (DEMO MODE)
·
·
·
·
The PC will load ChipView offering a choice between DEMO MODE, REGISTER VIEW, and TERMINAL
MODE. Select Demo Mode.
The program will request a configuration file, select among the displayed files
(DS2155_E1_DSNCOM_DRVR.cfg or DS2155_T1_DSNCOM_DRVR.cfg).
The Demo Mode screen will appear. Upon external loopback, the LOS and OOF indicators will extinguish.
Note: Demo Mode interacts with the device driver, which is resident in the DK101/DK2000 firmware. The
current implementation of this driver is for one device. As such, the demo mode will only interact with Port 1.
With minor changes, the device driver is extendible to N devices.
QUICK SETUP (REGISTER VIEW)
·
·
·
·
The PC will load ChipView offering a choice between DEMO MODE, REGISTER VIEW, and TERMINAL
MODE. Select Register View.
The program will request a definition file. Select DS21Q55DC_FPGA.def; through the ‘links’ section this will
also load DS21Q55DC.def.
The Register View Screen will appear, showing the register names, acronyms, and values for the DS21Q55
Predefined register settings for several functions are available as initialization files.
· INI files are loaded by selecting the menu File®Reg Ini File®Load Ini File
· Load the INI file DS21Q55_T1_BERT_ESF.ini
· After loading the INI file, the following may be observed:
- The RLOS LEDs (green) light upon external loopback.
- All four ports of the DS2Q155 begin transmitting a Daly pattern. When external loopback is applied, the
BERT bit count registers BBC1–3 and BEC1–3 may be updated by clearing and setting BC1.LC and
clicking the ‘Read All’ button.
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DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit
ADDRESS MAP
DK101 Daughter Card address space begins at 0x81000000.
DK2000 Daughter Card address space begins at:
0x30000000 for slot 0
0x40000000 for slot 1
0x50000000 for slot 2
0x60000000 for slot 3
All offsets given below are relative to the beginning of the daughter card address space (shown above).
Table 1. Daughter Card Address Map
OFFSET
0X0000
to
0X0015
0X1000
to
0X10ff
0X2000
to
0X20ff
0X3000
to
0X30ff
0X4000
to
0X40ff
DEVICE
FPGA
DESCRIPTION
Board identification and clock/signal routing
T1/E1/J1
Transceiver #1
DS21Q55 T1/E1/J1 transceiver, port 1
T1/E1/J1
Transceiver #2
DS21Q55 T1/E1/J1 transceiver, port 2
T1/E1/J1
Transceiver #3
DS21Q55 T1/E1/J1 transceiver, port 3
T1/E1/J1
Transceiver #4
DS21Q55 T1/E1/J1 transceiver, port 4
Registers in the FPGA may be easily modified using the ChipView host-based user-interface software along with
the definition file named “DS21Q55DC_FPGA.def.”
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DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit
FPGA Register Map
Table 2. FPGA Register Map
OFFSET
0X0000
0X0002
0X0003
0X0004
0X0005
0X0006
0X0007
0X0011
0X0012
0X0013
0X0014
0X0015
0X0016
0X0017
0X0018
0X0019
0X001A
0X001B
REGISTER
NAME
BID
XBIDH
XBIDM
XBIDL
BREV
AREV
PREV
MCSR
TCSR
SYSCLKT
SYSCLKR
SYNC1
SYNC2
SYNC3
TSERS
PRSER
PSYNC
PCLK
TYPE
Read-Only
Read-Only
Read-Only
Read-Only
Read-Only
Read-Only
Read-Only
Control
Control
Control
Control
Control
Control
Control
Control
Control
Control
Control
DESCRIPTION
Board ID
High-Nibble Extended Board ID
Middle-Nibble Extended Board ID
Low-Nibble Extended Board ID
Board FAB Revision
Board Assembly Revision
PLD Revision
DS21Q55 MCLK Pin Source
DS21Q55 TCLK Pin Source
DS21Q55 TSYSCLK Pin Setting
DS21Q55 RSYSCLK Pin Setting
DS21Q55 TSYNC Source
DS21Q55 TSSYNC Source
DS21Q55 RSYNC Source
TSER Source
PCM RSER Source
PCM RSYNC/TSYNC Source
PCM RCLK/TCLK Source
ID REGISTERS
BID: BOARD ID (Offset=0X0000)
BID is read only with a value of 0xD
XBIDH: HIGH NIBBLE EXTENDED BOARD ID (Offset=0X0002)
XBIDH is read only with a value of 0x0
XBIDM: MIDDLE NIBBLE EXTENDED BOARD ID (Offset=0X0003)
XBIDM is read only with a value of 0x1
XBIDL: LOW NIBBLE EXTENDED BOARD ID (Offset=0X0004)
XBIDL is read only with a value of 0x6
BREV: BOARD FAB REVISION (Offset=0X0005)
BREV is read only and displays the current fab revision
AREV: BOARD ASSEMBLY REVISION (Offset=0X0006)
AREV is read only and displays the current assembly revision
PREV: PLD REVISION (Offset=0X0007)
PREV is read only and displays the current PLD firmware revision
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DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit
CONTROL REGISTERS
Register Name: MCSR
Register Description: DS21Q55 MCLK Pin Source
Register Offset: 0x0011
Bit #
Name
Default
7
—
—
6
—
—
5
—
—
4
—
—
3
—
—
2
—
—
1
MSRCB
1
0
MSRCA
1
3
T2S1
0
2
T2S0
0
1
T1S1
0
0
T1S0
0
Bit 0: DS21Q55 Port 1 and 3 MCLK Source (MSRCA)
0 = Connect MCLK 1 (controls port 1 and 3) to the 1.544MHz clock
1 = Connect MCLK 1 (controls port 1 and 3) to the 2.048MHz clock
Bit 1: DS21Q55 Port 2 and 4 MCLK Source (MSRCA)
0 = Connect MCLK 2 (controls port 2 and 4) to the 1.544MHz clock
1 = Connect MCLK 2 (controls port 2 and 4) to the 2.048MHz clock
Register Name: TCSR
Register Description: DS21Q55 TCLK Pin Source
Register Offset: 0x0012
Bit #
Name
Default
7
T4S1
0
6
T4S0
0
5
T3S1
0
4
T3S0
0
Bit 0 to 1: DS21Q55 Port 1 TCLK Source (T1S0, T1S1)
The source for TCLK 1 is Defined as shown in Table 3.
Bit 2 to 3: DS21Q55 Port 2 TCLK Source (T2S0, T2S1)
The source for TCLK 2 is Defined as shown in Table 3.
Bit 4 to 5: DS21Q55 Port 3 TCLK Source (T3S0, T3S1)
The source for TCLK 3 is Defined as shown in Table 3.
Bit 6 to 7: DS21Q55 Port 4 TCLK Source (T4S0, T4S1)
The source for TCLK 3 is Defined as shown in Table 3.
Table 3. TCLKx Source Definition
TxS1, TxS0
00
01
10
11
TCLK CONNECTION
Drive TCLKX with the 1.544MHz clock
Drive TCLKX with the 2.048MHz clock
Drive TCLKX with RCLKX
N/A
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DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit
Register Name: SYSCLKT
Register Description: DS21Q55 TSYSCLK Pin Setting
Register Offset: 0x0013
Bit #
Name
Default
7
R4S1
0
6
R4S0
0
5
R3S1
0
4
R3S0
0
3
R2S1
0
2
R2S0
0
1
R1S1
0
0
R1S0
0
3
T2S1
0
2
T2S0
0
1
T1S1
0
0
T1S0
0
Bit 0 to 1: DS21Q55 Port 1 TSYSCLK Source (R1S0, R1S1)
The source for TSYSCLK 1 is Defined as shown in Table 4.
Bit 2 to 3: DS21Q55 Port 2 TSYSCLK Source (R2S0, R2S1)
The source for TSYSCLK 2 is Defined as shown in Table 4.
Bit 4 to 5: DS21Q55 Port 3 TSYSCLK Source (R3S0, R3S1)
The source for TSYSCLK 3 is Defined as shown in Table 4.
Bit 6 to 7: DS21Q55 Port 4 TSYSCLK Source (R4S0, R4S1)
The source for TSYSCLK 4 is Defined as shown in Table 4.
Table 4. TSYSCLKx Source Definition
RxS1, RxS0
00
01
10
11
TSYSCLKX CONNECTION
Drive TSYSCLKX with the 1.544MHz clock
Drive TSYSCLKX with the 2.048MHz clock
Drive TSYSCLK X with 8.192MHz clock
Drive TSYSCLKX with DS21Q55 PortX BPCLK
Register Name: SYSCLKR
Register Description: DS21Q55 RSYSCLK Pin Setting
Register Offset: 0x0014
Bit #
Name
Default
7
T4S1
0
6
T4S0
0
5
T3S1
0
4
T3S0
0
Bit 0 to 1: DS21Q55 Port 1 RSYSCLK Source (T1S0, T1S1)
The source for RSYSCLK 1 is Defined as shown in Table 5.
Bit 2 to 3: DS21Q55 Port 2 RSYSCLK Source (T2S0, T2S1)
The source for RSYSCLK 2 is Defined as shown in Table 5.
Bit 4 to 5: DS21Q55 Port 3 RSYSCLK Source (T3S0, T3S1)
The source for RSYSCLK 3 is Defined as shown in Table 5.
Bit 6 to 7: DS21Q55 Port 4 RSYSCLK Source (T4S0, T4S1)
The source for RSYSCLK 4 is Defined as shown in Table 5.
Table 5. RSYSCLKx Source Definition
TxS1, TxS0
00
01
10
11
RSYSCLKX CONNECTION
Drive RSYSCLKX with the 1.544MHz clock
Drive RSYSCLKX with the 2.048MHz clock
Drive RSYSCLK X with 8.192MHz clock
Drive RSYSCLKX with DS21Q55 PortX BPCLK
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DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit
Register Name: SYNC1
Register Description: DS21Q55 TSYNC Pin Source
Register Offset: 0x0015
Bit #
Name
Default
7
—
—
6
—
—
5
—
—
4
—
—
3
T4SRC
0
2
T3SRC
0
1
T2SRC
0
0
T1SRC
0
Bit 0: DS21Q55 Port 1 TSYNC Source (T1SRC)
0 = TSYNC 1 is an output, tri-state corresponding FPGA driver pin (weak pulldown)
1 = Drive TSYNC 1 with RSYNC 1
Bit 1: DS21Q55 Port 2 TSYNC Source (T2SRC)
0 = TSYNC 2 is an output, tri-state corresponding FPGA driver pin (weak pulldown)
1 = Drive TSYNC 2 with RSYNC 2
Bit 2: DS21Q55 Port 3 TSYNC Source (T3SRC)
0 = TSYNC 3 is an output, tri-state corresponding FPGA driver pin (weak pulldown)
1 = Drive TSYNC 3 with RSYNC 3
Bit 3: DS21Q55 Port 4 TSYNC Source (T4SRC)
0 = TSYNC 4 is an output, tri-state corresponding FPGA driver pin (weak pulldown)
1 = Drive TSYNC 4 with RSYNC 4
Note: When driving TSYNCx with RSYNCx the corresponding DS21Q55 port should be configured such that
TSYNCx is an input (IOCR1.1 = 0) and RSYNCx is an output (IOCR1.4 = 0).
Register Name: SYNC2
Register Description: DS21Q55 TSSYNC Pin Source
Register Offset: 0x0016
Bit #
Name
Default
7
—
—
6
—
—
5
—
—
4
—
—
3
T4SRC
0
2
T3SRC
0
1
T2SRC
0
0
T1SRC
0
Bit 0: DS21Q55 Port 1 TSSYNC Source (T1SRC)
0 = Not using transmit-side elastic store, tri-state corresponding FPGA driver pin (weak pulldown)
1 = Drive TSSYNC 1 with RSYNC 1
Bit 1: DS21Q55 Port 2 TSSYNC Source (T2SRC)
0 = Not using transmit-side elastic store, tri-state corresponding FPGA driver pin (weak pulldown)
1 = Drive TSSYNC 2 with RSYNC 2
Bit 2: DS21Q55 Port 3 TSSYNC Source (T3SRC)
0 = Not using transmit-side elastic store, tri-state corresponding FPGA driver pin (weak pulldown)
1 = Drive TSSYNC 3 with RSYNC 3
Bit 3: DS21Q55 Port 4 TSSYNC Source (T4Source)
0 = Not using transmit-side elastic store, tri-state corresponding FPGA driver pin (weak pulldown)
1 = Drive TSSYNC 4 with RSYNC 4
Note: When driving TSSYNCx with RSYNCx the corresponding DS21Q55 port should be configured such that
RSYNCx is an output (IOCR1.4 = 0).
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DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit
Register Name: SYNC3
Register Description: DS21Q55 RSYNC Pin Setting
Register Offset: 0x0017
Bit #
Name
Default
7
RSOR1
0
6
RSOR0
0
5
—
—
4
—
—
3
R4IO
0
2
R3IO
0
1
R2IO
0
0
R1IO
0
Bit 0: DS21Q55 Port 1 RSYNC Setting (R1IO)
0 = RSYNC 1 is an output, tri-state corresponding FPGA driver pin (weak pulldown)
1 = Drive RSYNC 1 with RSYNCX as shown in Table 6
Bit 1: DS21Q55 Port 2 RSYNC Setting (R2IO)
0 = RSYNC 2 is an output, tri-state corresponding FPGA driver pin (weak pulldown)
1 = Drive RSYNC 2 with RSYNCX as shown in Table 6
Bit 2: DS21Q55 Port 3 RSYNC Setting (R3IO)
0 = RSYNC 3 is an output, tri-state corresponding FPGA driver pin (weak pulldown)
1 = Drive RSYNC 4 with RSYNCX as shown in Table 6
Bit 3: DS21Q55 Port 4 RSYNC Setting (R4IO)
0 = RSYNC 4 is an output, tri-state corresponding FPGA driver pin (weak pulldown)
1 = Drive RSYNC 4 with RSYNCX as shown in Table 6
Note: When driving RSYNCy with RSYNCx the corresponding DS21Q55 port should be configured such that
RSYNCx is an output (IOCR1.4 = 0) and RSYNCy is an input (IOCR1.4 = 1).
Table 6. RSYNCx Function Definition
RSOR1, RSOR0
00
01
10
11
MASTER RSYNC DESIGNATION
RSYNC 1 is used to drive other RSYNC pins (providing RXIO = 1)
RSYNC 2 is used to drive other RSYNC pins (providing RXIO = 1)
RSYNC 3 is used to drive other RSYNC pins (providing RXIO = 1)
RSYNC 4 is used to drive other RSYNC pins (providing RXIO = 1)
Register Name: TSERS
Register Description: DS21Q55 TSER Pin Source
Register Offset: 0x0018
Bit #
Name
Default
7
T4S1
0
6
T4S0
0
5
T3S1
0
4
T3S0
0
Bit 0 to 1: DS21Q55 Port 1 TSER Source (T1S0, T1S1)
The source for TSER 1 is Defined as shown in Table 4.
Bit 2 to 3: DS21Q55 Port 2 TSER Source (T2S0, T2S1)
The source for TSER 2 is Defined as shown in Table 4.
Bit 4 to 5: DS21Q55 Port 3 TSER Source (T3S0, T3S1)
The source for TSER 3 is Defined as shown in Table 4.
Bit 6 to 7: DS21Q55 Port 4 TSER Source (T4S0, T4S1)
The source for TSER 4 is Defined as shown in Table 4.
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3
T2S1
0
2
T2S0
0
1
T1S1
0
0
T1S0
0
DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit
Table 7. TSERx Source Definition
TxS1, TxS0
00
01
10
11
TSERX CONNECTION
Tri-state TSERX (weak pulldown)
Drive TSERX with RSERX
Drive TSERX with PCM_TXD bus (DK2000 only)
N/A
Register Name: PRSER
Register Description: PCM RSER Source
Register Offset: 0x0019
Bit #
Name
Default
7
—
—
6
—
—
5
—
—
4
—
—
3
R1EN
0
2
R1EN
0
1
R1EN
0
Bit 0 to 1: PCM RSER Source (R1EN)
0 = Do not drive DS21Q55 Port 1 RSER onto PCM_RSER
1 = Logically OR DS21Q55 Port 1 RSER with selected other RSER pins and drive onto PCM_RSER
Bit 2 to 3: DS21Q55 Port 2 TSER Source (T2S0, T2S1)
0 = Do not drive DS21Q55 Port 2 RSER onto PCM_RSER
1 = Logically OR DS21Q55 Port 2 RSER with selected other RSER pins and drive onto PCM_RSER
Bit 4 to 5: DS21Q55 Port 3 TSER Source (T3S0, T3S1)
0 = Do not drive DS21Q55 Port 3 RSER onto PCM_RSER
1 = Logically OR DS21Q55 Port 3 RSER with selected other RSER pins and drive onto PCM_RSER
Bit 6 to 7: DS21Q55 Port 4 TSER Source (T4S0, T4S1)
0 = Do not drive DS21Q55 Port 4 RSER onto PCM_RSER
1 = Logically OR DS21Q55 Port 4 RSER with selected other RSER pins and drive onto PCM_RSER
Note: PRSER register is for use with the DK2000 only.
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0
R1EN
0
DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit
Register Name: PSYNC
Register Description: PCM RSYNC/TSYNC Source
Register Offset: 0x001A
Bit #
Name
Default
7
—
—
6
—
—
5
T2SR
0
4
T1SR
0
3
—
—
Bit 0 to 1: PCM_RSYNC Source
R2SR, R1SR
PCM_RSYNC Source
00
PCM_RSYNC is driven by DS21Q55 port 1 RSYNC.
01
PCM_RSYNC is driven by DS21Q55 port 2 RSYNC.
10
PCM_RSYNC is driven by DS21Q55 port 3 RSYNC.
11
PCM_RSYNC is driven by DS21Q55 port 4 RSYNC.
Bit 4 to 5: PCM_TSYNC Source
T2SR, T1SR
PCM_TSYNC Source
00
PCM_TSYNC is driven by DS21Q55 port 1 TSYNC.
01
PCM_TSYNC is driven by DS21Q55 port 2 TSYNC.
10
PCM_TSYNC is driven by DS21Q55 port 3 TSYNC.
11
PCM_TSYNC is driven by DS21Q55 port 4 TSYNC.
Note: PSYNC register is for use with the DK2000 only.
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2
—
—
1
R2SR
0
0
R1SR
0
DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit
Register Name: PCLK
Register Description: PCM RCLK/TCLK Source
Register Offset: 0x001B
Bit #
Name
Default
7
—
—
6
TCM
0
5
T2SR
0
4
T1SR
0
3
—
—
2
RCM
0
Bit 0 to 2: PCM_RCLK Source
RCM, R2SR, R1SR
PCM_RCLK Source
000
PCM_RCLK is driven by DS21Q55 port 1 RCLK.
001
PCM_RCLK is driven by DS21Q55 port 2 RCLK.
010
PCM_RCLK is driven by DS21Q55 port 3 RCLK.
011
PCM_RCLK is driven by DS21Q55 port 4 RCLK.
100
PCM_RCLK is driven by DS21Q55 port 1 BPCLK.
101
PCM_RCLK is driven by DS21Q55 port 2 BPCLK.
110
PCM_RCLK is driven by DS21Q55 port 3 BPCLK.
111
PCM_RCLK is driven by DS21Q55 port 4 BPCLK.
Bit 4 to 5: PCM_TCLK Source
TCM, T2SR, T1SR
PCM_TCLK Source
000
PCM_TCLK is driven by source used for DS21Q55 port 1 TCLK.
001
PCM_TCLK is driven by source used for DS21Q55 port 2 TCLK.
010
PCM_TCLK is driven by source used for DS21Q55 port 3 TCLK.
011
PCM_TCLK is driven by source used for DS21Q55 port 4 TCLK.
100
PCM_TCLK is driven by DS21Q55 port 1 BPCLK.
101
PCM_TCLK is driven by DS21Q55 port 2 BPCLK.
110
PCM_TCLK is driven by DS21Q55 port 3 BPCLK.
111
PCM_TCLK is driven by DS21Q55 port 4 BPCLK.
Note: PCLK register is for use with the DK2000 only.
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1
R2SR
0
0
R1SR
0
DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit
FPGA CONTROL EXAMPLES
SCENARIO #1: DS21Q55 TO/FROM DK2000
DS21Q55
DK2000
XO
TSER
TCLK
BPCLK
TSYNC
PCM_TXD
RSER
RCLK
BPCLK
RSYNC
PCM_RXD
PCM_TCLK
PCM_TSYNC
PCM_RCLK
PCM_RSYNC
Table 8. FPGA Configuration for Scenario #1 (Port 1, T1 Mode)
REGISTER
SETTING
FUNCTION
MCSR
0X01
Drive DS21Q55 ports 1 and 3 MCLK with 2.048MHz
TCSR
0X00
Drive TCLK with 1.544MHz
SYSCLKT
0X00
Drive TSYSCLK with 1.544MHz
SYSCLKR
0X00
Drive RSYSCLK with 1.544MHz
SYNC1
0X00
Tri-state FPGA driver pin for DS21Q55 TSYNC1
SYNC2
0X01
Drive TSSYNC1 with RSYNC1
SYNC3
0X00
Tri-state FPGA driver pin for DS21Q55 RSYNC
TSERS
0X02
Drive DS21Q55 TSER1 with data from PCM bus
PRSER
0X01
Drive DS21Q55 RSER1 onto PCM bus
PSYNC
0X00
PCM RSYNC and PCM TSYNC are provided by DS21Q55 port 1 RSYNC and
TSYNC (respectively)
PCLK
0X44
PCM RCLK and TCLK are driven by port 1 BPCLK
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DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit
SCENARIO #2: EXTERNAL REMOTE LOOPBACK
(FULL BANDWIDTH, NOT JUST PAYLOAD)
DS21Q55
TSER
TCLK
BPCLK
TSYNC
RSER
RCLK
BPCLK
RSYNC
Table 9. FPGA Configuration for Scenario #2 (Port 1, T1 Mode)
REGISTER
SETTING
FUNCTION
MCSR
0X01
Drive DS21Q55 ports 1 and 3 MCLK with 2.048MHz
TCSR
0X02
Drive TCLK1 with RCLK1
SYSCLKT
0X00
Drive TSYSCLK with 1.544MHz
SYSCLKR
0X00
Drive RSYSCLK with 1.544MHz
SYNC1
0X01
Drive TSYNC1 with RSYNC1
SYNC2
0X01
Drive TSSYNC1 with RSYNC1
SYNC3
0X00
Tri-state FPGA driver pin for DS21Q55 RSYNC
TSERS
0X01
Drive DS21Q55 TSER1 with data from RSER1
PRSER
N/A
Unused
PSYNC
N/A
Unused
PCLK
N/A
Unused
Table 10. DS21Q55 Partial Configuration for Scenario #2 (Port 1, T1 Mode)
REGISTER
IOCR1
ESCR
CCR1
SETTING
TSIO = 0;
RSIO = 0
TESE = 0;
RESE = 0
TCSS1 = 0;
TCSS2 = 0
FUNCTION
TSYNc is an input, RSYNC is an output
Bypass Rx and Tx elastic stores
TCLK is driven by TCLK pin
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DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit
DS21Q55 INFORMATION
For more information about the DS21Q55, please consult the DS21Q55 data sheet available on our website at
www.maxm-ic.com/DS21Q55. Software downloads are also available for this demo kit.
DS21Q55DK INFORMATION
For more information about the DS21Q55DK, including software downloads, please consult the DS21Q55DK data
sheet available on our website at www.maxim-ic.com/telecom.
TECHNICAL SUPPORT
For additional technical support, please e-mail your questions to [email protected]
SCHEMATICS
The DS21Q55DK schematics are featured in the following pages.
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products · Printed USA
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© 2003 Maxim Integrated Products · Printed USA
© 2003 Maxim Integrated Products · Printed USA
© 2003 Maxim Integrated Products · Printed USA
© 2003 Maxim Integrated Products · Printed USA
© 2003 Maxim Integrated Products · Printed USA
© 2003 Maxim Integrated Products · Printed USA
© 2003 Maxim Integrated Products · Printed USA
© 2003 Maxim Integrated Products · Printed USA
© 2003 Maxim Integrated Products · Printed USA
© 2003 Maxim Integrated Products · Printed USA
© 2003 Maxim Integrated Products · Printed USA
© 2003 Maxim Integrated Products · Printed USA
© 2003 Maxim Integrated Products · Printed USA
© 2003 Maxim Integrated Products · Printed USA
© 2003 Maxim Integrated Products · Printed USA