EDI88512C HI-RELIABILITY PRODUCT 512Kx8 Monolithic SRAM CMOS FEATURES ■ 512Kx8 bit CMOS Static The EDI88512C is a 4 megabit Monolithic CMOS Static RAM. ■ Random Access Memory • Access Times of 70, 85, 100ns • Data Retention Function (LP version) • TTL Compatible Inputs and Outputs • Fully Static, No Clocks The 32 pin DIP pinout adheres to the JEDEC evolutionary standard for the four megabit device. Both the DIP and CSOJ packages are pin for pin upgrades for the single chip enable 128K x 8, the EDI88128C. Pins 1 and 30 become the higher order addresses. A Low Power version with Data Retention (EDI88512LP) is also available for battery backed applications. Military product is available compliant to Appendix A of MIL-PRF-38535. ■ 32 lead JEDEC Approved Evolutionary Pinout • Ceramic Sidebrazed 600 mil DIP (Package 9) • Ceramic SOJ (Package 140) ■ Single +5V (±10%) Supply Operation FIG. 1 PIN CONFIGURATION PIN DESCRIPTION TOP VIEW A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 AØ I/OØ I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 VCC 31 A15 30 A17 29 WE 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CS 21 I/O7 20 I/O6 19 I/O5 18 I/O4 17 I/O3 I/O0-7 Data Inputs/Outputs A0-18 Address Inputs WE Write Enables CS Chip Selects OE Output Enable VCC Power (+5V ±10%) VSS Ground NC Not Connected BLOCK DIAGRAM Memory Array AØ-18 Address Buffer Address Decoder I/O Circuits I/OØ-7 WE CS OE February 2001 Rev. 11 1 White Electronic Designs Corporation • www.whiteedc.com • (602) 437-1520 EDI88512C TRUTH TABLE ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss -0.5 to 7.0 Unit OE CS WE Mode Output Power V X H L X H L L L X H H L Standby Output Deselect Read Write High Z High Z Data Out Data In Icc 2 , Icc3 Icc 1 Icc 1 Icc 1 Operating Temperature TA (Ambient) 0 to +70 °C -40 to +85 °C Military -55 to +125 °C Storage Temperature, Plastic -65 to +150 °C 1 W Parameter Symbol Min Typ Max Unit mA Supply Voltage VCC 4.5 5.0 5.5 V °C Supply Voltage VSS 0 0 0 V Input High Voltage VIH 2.2 — Vcc +0.5 V Input Low Voltage VIL -0.3 — +0.8 V Commercial Industrial Power Dissipation Output Current 20 Junction Temperature, TJ 175 RECOMMENDED OPERATING CONDITIONS NOTE: Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE (TA = +25°C) Parameter Symbol Condition Address Lines CI VIN = Vcc or Vss, f = 1.0MHz Max Unit 12 pF Data Lines CO VOUT = Vcc or Vss, f = 1.0MHz 14 pF These parameters are sampled, not 100% tested. DC CHARACTERISTICS (VCC = 5V, *TA = -55°C to +125°C) Parameter Symbol Conditions Min Typ* Max Units Input Leakage Current ILI VIN = 0V to VCC — — ±10 Output Leakage Current ILO VI/O = 0V to VCC — — ±10 µA µA Operating Power Supply Current I CC1 WE, CS = VIL, II/O = 0mA, Min Cycle (70-100ns) — 45 75 mA Standby (TTL) Power Supply Current I CC2 CS ≥ VIH, VIN ≤ VIL , VIN ≥ VIH mA Full Standby Power Supply Current I CC3 CS ≥ VCC -0.2V VIN ≥ Vcc -0.2V or VIN ≤ 0.2V — 3 10 C — — 5 mA LP — — 2 mA Output Low Voltage VOL IOL = 2.1mA — — 0.4 V Output High Voltage VOH IOH = -1.0mA 2.4 — — V NOTE: DC test conditions: VIL = 0.3V, VIH = Vcc -0.3V AC TEST CONDITIONS Figure 1 Figure 2 Vcc 480Ω Q Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load Vcc 480Ω NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2) Q 255Ω 30pF VSS to 3.0V 5ns 1.5V Figure 1 255Ω White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520 5pF 2 EDI88512C AC CHARACTERISTICS – READ CYCLE (VCC = 5.0V, VSS = 0V, TA = 0°C to +70°C) Parameter Symbol JEDEC Alt. Min 70ns 85ns Read Cycle Time tAVAV tRC 70 Address Access Time tAVQV tAA 70 85 100 ns Chip Enable Access Time tELQV tACS 70 85 100 ns Chip Enable to Output in Low Z (1) tELQX tCLZ Chip Disable to Output in High Z (1) tEHQZ tCHZ 30 ns Output Hold from Address Change tAVQX tOH Output Enable to Output Valid tGLQV tOE 50 ns 30 ns Max Min 85 10 10 10 tGLQX tOLZ 5 tGHQZ tOHZ 0 ns 10 ns 45 5 5 0 30 0 Max Min Units ns 30 10 25 Max 10 35 Output Disable to Output in High Z(1) Min 100 25 Output Enable to Output in Low Z (1) 100ns Max ns 1. This parameter is guaranteed by design but not tested. AC CHARACTERISTICS – WRITE CYCLE (VCC = 5.0V, VSS = 0V, TA = 0°C to +70°C) Symbol 70ns 85ns Max JEDEC Alt. Min Write Cycle Time tAVAV tWC 70 85 100 ns Chip Enable to End of Write tELWH tELEH tCW tCW 60 60 70 70 80 80 ns ns Address Setup Time tAVWL tAVEL tAS tAS 0 0 0 0 0 0 ns ns Address Valid to End of Write tAVWH tAVEH tAW tAW 65 65 70 70 80 80 ns ns Write Pulse Width tWLWH tWLEH tWP tWP 50 50 55 55 60 60 ns ns Write Recovery Time tWHAX tEHAX tWR tWR 0 0 0 0 0 0 ns ns Data Hold Time tWHDX tEHDX tDH tDH 0 0 0 0 0 0 ns ns Write to Output in High Z (1) tWLQZ tWHZ 0 Data to Write Time tDVWH tDVEH tDW tDW 40 30 40 35 40 40 ns ns Output Active from End of Write (1) tWHQX tWLZ 5 5 5 ns 25 Min 100ns Parameter 0 30 0 Max 30 Units ns 1. This parameter is guaranteed by design but not tested. 3 White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520 EDI88512C FIG. 2 TIMING WAVEFORM - READ CYCLE tAVAV ADDRESS tAVQV CS tAVAV ADDRESS ADDRESS 1 ADDRESS 2 tAVQV tAVQX tELQV tELQX tEHQZ tGLQV tGLQX tGHQZ OE DATA I/O DATA 1 DATA OUT DATA 2 READ CYCLE 2 (WE HIGH) READ CYCLE 1 (WE HIGH; OE, CS LOW) FIG. 3 WRITE CYCLE - WE CONTROLLED tAVAV ADDRESS tAVWH tELWH tWHAX CS tAVWL tWLWH WE tDVWH DATA IN tWHDX DATA VALID tWLQZ tWHQX HIGH Z DATA OUT WRITE CYCLE 1, WE CONTROLLED FIG. 4 WRITE CYCLE - CS CONTROLLED tAVAV WS32K32-XHX ADDRESS tAVEH tELEH tEHAX CS tAVEL tWLEH WE tDVEH DATA IN DATA VALID HIGH Z DATA OUT WRITE CYCLE 2, CS CONTROLLED White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520 tEHDX 4 EDI88512C DATA RETENTION CHARACTERISTICS (EDI88512LP ONLY) (TA = -55°C to +125°C) Characteristic Low Power Version only Data Retention Voltage Sym VDD Data Retention Quiescent Current ICCDR Chip Disable to Data Retention Time TCDR VIN ≥ VDD -0.2V Operation Recovery Time TR Conditions Min Typ VDD = 2.0V 2 – – V CS ≥ VDD -0.2V – – 185 µA or VIN ≤ 0.2V Max Units 0 – – ns TAVAV – – ns FIG. 5 DATA RETENTION - CS CONTROLLED Data Retention Mode 4.5V Vcc WS32K32-XHX VDD 4.5V tCDR CS tR CS = VDD -0.2V DATA RETENTION, CS CONTROLLED 5 White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520 EDI88512C PACKAGE 9: 32 LEAD SIDEBRAZED CERAMIC DIP 1.616 1.584 0.620 0.600 0.060 0.040 Pin 1 Indicator 0.200 0.125 0.061 0.017 0.155 0.115 0.100 TYP 0.020 0.016 0.600 NOM 15 x 0.100 = 1.500 ALL DIMENSIONS ARE IN INCHES PACKAGE 140: 32 LEAD CERAMIC SOJ 0.010 0.006 0.019 0.015 0.840 0.820 0.444 0.430 0.379 0.155 0.106 ALL DIMENSIONS ARE IN INCHES White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520 6 0.050 TYP EDI88512C ORDERING INFORMATION EDI 8 8 512 C X X X WHITE ELECTRONIC DESIGNS SRAM ORGANIZATION, 512Kx8 TECHNOLOGY: C = CMOS Standard Power LP = Low Power ACCESS TIME (ns) PACKAGE TYPE: C = 32 lead Sidebrazed DIP, 600 mil (Package 9) N = 32 lead Ceramic SOJ (Package 140) DEVICE GRADE: B = MIL-STD-883 Compliant M = Military Screened -55°C to +125°C I = Industrial -40°C to +85°C C = Commercial 0°C to +70°C 7 White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520