ENH050Q1-320/450/600 Panelview Enhancing the Vision ENH050Q1-320/450/600 Color TFT-LCD Module Features GENERAL DESCRIPTION Panelview provides optically enhanced solutions to the standard Sharp LQ5AW136 color active matrix LCD module. The first enhancement is an index matching (IM) film lamination to the front surface of the display polarizer. ■ Slim, lightweight and compact The IM film is available in two surface treatments - IM/ Clear and IM/110 (a 10% diffusion). The second enhancement is the incorporation of a reflective polarizer (RP) to improve brightness by up to 40%. The third enhancement is the addition of prism films (RPp) further increasing the brightness of the display. The module accepts full color video signals conforming to the NTSC(M) and PAL(B-G) system standards. ■ Built-in video interface circuit and control circuit responsive to two sets of standard RGB analog video signals. 1) Active area/Outline area=70% 2) Thickness: 16.5mm 3) Mass: 185g (Max) ■ Reduced reflection as a result of low reflectance Black-Matrix and Index Matching (IM) film laminationi. IM is available in two surface treatments, IM/Clear (glossy) and IM/110 (10% diffusion). ■ It is possible to use both the simultaneous and the independent time sampling. It can withstand an intense environment, the outline dimension is suitable for an automotive display, compact size, compatible with 2DIN size. ■ An external clock mode is available. ■ Optical viewing angle: wide view angle (6 oclock direction.) (Customers can use this module as a 12 oclock viewing direction type by using a display rotating function to rotate right/left and up/down scanning direction electrically.) Panelview assumes no responsibility for any damage resulting from the use of the device which does not comply with the instructions and the precautions specified in these specification sheets. Panelview does assume the responsibility for the warranty of the enhanced product. ■ This module includes a high luminance edge light that is excellent at low temperature. FEATURES ■ Dual mode type. [NTSC(M) and PAL(B-G) standards] ■ It is possible to use the dimming frequency(PWM) for backlight. ■ MBK-PAL enables the 234-scanning lines panel to display a picture with virtually 273-scanning lines. CONSTRUCTION AND OUTLINE ■ Outline dimensions of TFT-LCD module: See Fig. 3 ■ TFT-active matrix-LCD drive system with high contrast. ■ The module consists of a TFT-LCD panel, driver IC's, control PWB mounted with electronic circuits, edge light, frame, front and rear shielding cases. (Backlight driving DC/AC inverter is not built in the module.) ■ 74,880 pixels (RGB Stripe configuration and full color) 5" diagonal size. MECHANICAL SPECIFICATION Parameter Display format Active area Screen size (Diagonal) Dot pitch Dot configuration Outline dimension (1) Specification Unit 74,880 Pixels 960(W) x 234(H) dots 102.2(W) x 74.8(H) mm 13 (5") cm 0.1065(W) x 0.3195(H) mm RGB Stripe configuration 126.8 (W) x 89.6 (H) x 16.5 (D) mm 185 (Max) g Mass Note: This measurement is typical, and see Fig.3 for details . August 2003 Rev. 0 ENH050Q1-XXX Original specifications created by Sharp. 1 Panelview (503) 690-2460 www.whiteedc.com Panelview is a subsidiary of White Electronic Designs Corporation ENH050Q1-320/450/600 Panelview Enhancing the Vision INPUT/OUTPUT TERMINALS AND THEIR DESCRIPTIONS TFT-LCD PANEL DRIVING SECTION (Hi means digital input voltage, Lo means GND.) Pin No. Symbol I/O Description 1 HSY I, O Input/output horizontal sync. signal (low active) Remarks (1) 2 VSY I, O Input/output vertical sync. signal (low active) (2) 3 PWM O Terminal for output PWM of dimming back light (3) 4 NTP I Terminal for display mode change of NTSC and PAL (4) 5 HRV I Turning the direction of horizontal scanning (5) 6 VRV I Turning the direction of vertical scanning (6) 7 VSW I Selection signal of two sets of video signals (7) 8 SAM I Terminal for sampling mode change (8) 9 VCDC I DC bias voltage adjusting terminal of common electrode driving signal (9) 10 VSH I Positive power supply voltage 11 VBS I Composite video signal for sync. seperator 12 BRT I Brightness adjusting terminal (10) 13 VR1 I Color video signal (Red) 1 14 VG1 I Color video signal (Green) 1 ↑ 15 VB1 I Color video signal (Blue) 1 ↑ 16 VSL I Negative power supply voltage 17 VR2 I Color video signal (Red) 2 18 VG2 I Color video signal (Green) 2 ↑ 19 VB2 I Color video signal (Blue) 2 ↑ 20 GND I Ground 21 CLKC I 22 CLK I, O (11) Positive (On when VSW=Hi.) Positive (On when VSW=Lo.) Change the input/output direction of CLK,HSY and VSY. (12) Input/output clock signal (13) Notes: 1. If CLKC=Hi, this terminal outputs horizontal sync. signal in phase with VBS. If CLKC=Lo, this terminal will be external horizontal sync. input terminal. 2. If CLKC=Hi, this terminal outputs vertical sync. signal in phase with VBS. If CLKC=Lo, this terminal will be external vertical sync. input terminal. 3. PWM signal is used for the PWM dimming frequency and it is easy to get PWM signal dimming by combining both HSY and PWM signal. But use this PWM signal in case of input standard NTSC or PAL signal. 4. This terminal is to switch the display mode, and it is NTSC mode when NTP is High and is PAL mode when NTP is Low. 5. When this terminal is High, it will be normal and when it is Low, it will display reversely on the horizontal direction. 6. When this terminal is High, it will be normal and when it is Low, it will display reversely on the vertical direction. 7. This terminal is to switch input for groups of RGB color video signals, and Input 1 (No. 13 to 15) is selected when VSW is High and Input 2 (No. 17 to 19) is selected when VSW is Low. 8. This terminal switches the sampling mode. It is the independent data-sampling timing at RGB dots when SAM is High and it is the simultaneous data-sampling timing at RGB dots when SAM is Low. 9. This terminal is applicable to the DC bias voltage adjusting terminal of the common electrode driving signal. If power supply voltage is typical, it is not necessary to re-adjust it. So, use it in the open condition. However, in the case that the power supply voltage is changed, or power supply voltage is reduced, adjust it externally to get the best contrast with a resistor that is added to this terminal, or semi-fixed resistor, VCDC in module. A recommended circuit is shown in Fig. 5. 10. The sync. signal which will be input, is negative polarity and is applicable to standard composite sync. signal, negative one in the same pulse level. 11. DC voltage supplied to this terminal, makes the brightness of the screen adjustable, which is the black level of the video signal. Although this is adjusted in the time of delivery to get the best display in the condition of the open terminal, it is also able to be re-adjusted externally with a resistor that can be added to this terminal, or a semi-fixed resistor, BRT, in module. A recommended circuit is shown in Fig. 5. 12. CLKC=Hi, CLK.HSY.VSY terminals are output mode. CLKC= Lo : CLK. HSY. VSY terminals are input mode. 13. If CLKC=Hi, this terminal outputs the clock for source drivers. If CLKC=Lo, this terminal will be the external clock input terminal. Original specifications created by Sharp. Panelview Hillsboro, OR (503) 690-2460 Panelview is a subsidiary of White Electronic Designs Corporation 2 ENH050Q1-320/450/600 Panelview Enhancing the Vision FUNCTIONAL MACHING AND INPUT/OUTPUT MODE CLKC="Hi" CLKC="Lo" Terminal SAM="Hi" SAM="Lo" SAM="Hi" SAM="Lo" HSY Output Output Input Input VSY Output Output Input Input CLK Output Dot clock Output Pixel clock Input Dot clock Input Pixel clock BACKLIGHT DRIVING SECTION Terminal No. Symbol I/O CN1 1 VL1 I Input terminal (hi voltage side) [14] Function 2 NC Non connection 3 VL2 I Input terminal (low voltage side) Note: 14. Low Voltage side of DC/AC inverter for backlight driving connects with Ground of inverter circuit. ABSOLUTE MAXIMUM RATINGS GND = OV , TA = 25°C Parameter Symbol MIN MAX Positive power supply voltage V SH -0.3 +9.0 Unit V Negative power supply voltage V SL -6.0 + 0.3 V Analog input signals (1) Vi 2.0 Vp-p Digital input/output signals (2) VI -0.3 +5.4 V DC bias voltage of common electrode driving signal VCDC V SL V SH V Brightness adjusting terminal V BRT 0 + 5.1 V °C Storage temperature (3) Operating temperature (3,4) T STG -30 85 surface of panel Top1 -30 85 °C environment Top2 -30 60 °C Notes: 1. VBS, VR1, VG1, VB1, VR2, VG2, VB2 terminals(Video signal) 2. NTP, HRV, VRV, SAM, VSW, HSY, VSY, CLKC, CLK terminals 3. The temperature of all parts in module should not exceed this rating. Maximum wet-bulb temperature should be less than 58°C. No dew condensation. Original specifications created by Sharp. 3 Panelview (503) 690-2460 www.whiteedc.com Panelview is a subsidiary of White Electronic Designs Corporation ENH050Q1-320/450/600 Panelview Enhancing the Vision ELECTRICAL CHARACTERISTICS RECOMMENDED OPERATING CONDITION TFT-LCD PANEL DRIVING SECTION GND = OV, TA = 25°C Parameter Symbol MIN TYP MAX Unit Positive power supply voltage V SH +7.8 +8.0 +8.2 V Negative power supply voltage V SL -5. 2 -5. 0 -4. 8 V VBS 0.7 1.0 2.0 Vp-p Vi 0.7 Vp-p ViDC VIH -1.0 -3.7 0 -1.0 +5.1 V V (3) Input resistor is over 10kΩ. (4) Amplitude Analog input voltage Digital input voltage DC component High level Remarks (1) Input resistor (2) is over l0kΩ. Low level VIL 0 +1.0 V Histeresis VH 0.4 V Digital output High level VOH +4.0 +5.5 V voltage Low level VOL 0 +1.0 V over 60kΩ. (5) Output clock Duty cycle Duty 45/55 50/50 55/45 CLKC=High (6) Input horizontal Drive I OH 0.25 mA VOH=2.6V capability I OL -0.28 mA VOL=2.3V freq. fH (N) 15.13 15.73 16.33 kHz CLKC=High PAL fH (P) 15.03 15.63 16.23 kHz (8) tHI (N) tHI (P) 4.2 4.2 4.7 4.7 5.2 5.2 µs µs rise time trHI 1 0.5 µs fall time tf H I 1 0.5 µs freq. NTSC fV (N) f H/284 f H/262 f H/258 Hz CLKC=High, H=1/fH fV (P ) f H/344 f H/312 f H/304 Hz (9) for VBS terminal pulse NTSC width PAL sync. component Input clock PAL pulse NTSC tVI (N) 3H µs width PAL tVI 2.5H µs µs (P) for VBS terminal rise time tr VI 1 0.5 fall time tf V I 1 0.5 µs frequency fCLI 18.2 18. 9 19.6 MHz SAM=High CLKC=Low fCLI 6. 0 6. 8 7.6 MHz SAM=Low (10) t WH t WL 20.0 20.0 ns ns rise time tr CLI 5.0 ns fall time tf C L I 5.0 ns fHI fCLI/1230 f CLI /1200 f CLI/1170 Hz SAM=High CLKC=Low fHI f CLI /465 f CLI /435 f CLI /405 Hz SAM=Low (11) t HI 1.0 4.7 8.4 µs for HSY terminal rise time trHI 1 0.05 µs fall time tf H I 1 0.05 µs fVI 50 f HI /262 f HI /258 Hz (12) 1H 3H 5H µs for VSY terminal High width Low width Input HSY (7) NTSC sync. component Input vertical Load resister is frequency (Horizontal sync.) pulse width Input VSY frequency (Vertical sync.) pulse width tVI (P) rise time tr VI 2 0.5 µs fall time Data set up time tf V I 2 t SU 1 25 0.5 µs ns Data hold time t HO 1 25 ns Data set up time t SU 2 1.0 µs Data hold time t HO 2 1.0 µs Original specifications created by Sharp. Panelview Hillsboro, OR (503) 690-2460 Panelview is a subsidiary of White Electronic Designs Corporation 4 for CLK terminal (13) (14) CLKC= Low CLKC=Low ENH050Q1-320/450/600 Panelview Enhancing the Vision TFT-LCD PANEL DRIVING SECTION Parameter Symbol MIN TYP MAX Unit Remarks DC bias voltage for common electrode driving signal VCDC 0 +2.0 +3.0 V DC component (15) Terminal voltage applicable to brightness V BRT +2.0 +2.3 +2. 4 V Notes: 1. Power supply voltage should not be changed after adjusting VCDC. 2. VR1, VG1, VB1, VR2, VG2, VB2 terminals (Video signal) 3. VBS, VR1, VG1, VB1, VR2, VG2, VB2 terminals 4. HSY, VSY, NTP, VSW, HRV, VRV, SAM CLKC, CLK terminals 5. HSY, VSY, CLK terminals (output mode) 6. CLK terminals (output mode) 7. Duty cycle is defined as follows. 8. VBS (horizontal sync. component) 9. VBS (vertical sync. component) 10. CLK (input mode) 11. HSY (input mode) 12. VSY (input mode) 13. In case of CLKC=Lo, it shows the phase difference from HSY to CLK. In that case, HSY will be taken at the rise timing of CLK. 14. In case of CLKC=Lo. it shows the phase difference from VSY to HSY. In that case, VSY will be taken at the rise timing of HSY. 15. Adjusting the optimal voltage on every module at the typical value of power supply voltage to get the maximum value of contrast. However, in the case that the power supply voltage is changed, for example the level of power supply voltage is reduced, adjust it externally to get the best contrast with a resistor you add to this terminal, or semifixed resistor, VCDC, in module. A recommended circuit is shown in Fig. 5. Duty=TOL/TOH TOH TOL BACKLIGHT DRIVING SECTION Parameter Symbol MIN TYP MAX Unit Remarks VL7 550 610 670 Vrms I L =6.5mArms Lamp current IL 3.0 6.5 7.0 mArms normal operation Lamp frequency fL 20 70 KHz Kickoff voltage VS 1450 Vrms Ta = +25°C 1500 Vrms Ta = -30°C Lamp Voltage POWER CONSUMPTION TA = 25°C Parameter Positive supply current Symbol Conditions MIN TYP MAX Unit I SH VSH = +8.0V 140 170 mA VSL = -5.0V 55 70 mA 1.4 1.7 W (16) 4.0 W (17) Negative supply current ISL Total WS Lamp power consumption WL normal driving Remarks 16. Excluding backlight section 17. Reference data by calculation (I L x VL x 1: number of lump) Circuit Diagram Input/Output Signal Waveforms (Fig. 6) The circuit block diagram of TFT-LCD module is shown in Fig. 4. BRT, VCDC, external adjusting recommended circuit is shown in Fig. 5. Caution: For the VBS signal, input standard composite video (or sync.) signal applicable to the operating mode which have NTSC (M) or PAL (B-G) and is selected by the NTP signal. Caution: Turn the power supply on or off (VSH and V SL) at the same time. Be careful to supply all power voltage before inputting signals. If using PWM mode, refer to the timing chart shown in Fig. 7. Dimming Backlight by PWM Timing Chart Original specifications created by Sharp. 5 Panelview (503) 690-2460 www.whiteedc.com Panelview is a subsidiary of White Electronic Designs Corporation ENH050Q1-320/450/600 Panelview Enhancing the Vision INPUT/OUTPUT SIGNAL TIMING CHART (FIG. 6) (CLKC=HIGH, NTSC: fH=15.7KHZ, fV=60HZ/PAL: fH=15.6 KHZ, fV=50HZ) Parameter Symbol MIN TYP MAX Unit Remarks pulse width t HS 2 3.2 3.9 4.6 µs f=fH (18) phase difference tpd 0.4 1.1 1.8 µs (19) rise time trHO 0.5 µs CL=10pF Horizontal sync. output pulse [HSY] fall time tf HO 0.5 µs pulse width tvs 4H µs phase difference tv HO 11.0 28.0 µs (20) rise time tr VO 2.0 µs CL=10pF [VSY] fall time tf V O 2.0 µs Vertical odd field t PV 1 1H µs even field t PV 2 0.5H µs (21) NTSC MODE f CLO fH x XXX 2 MHz SAMC=Hi PAL MODE f CLO fH x XXX 2 MHz (22) NTSC MODE f CLO fH x XXX 6 MHz SAMC=Lo PAL MODE f CLO fH x XXX 6 MHz (23) Vertical sync. output pulse phase difference Clock output frequency [CLK] 1201 1209 1201 1209 1H=1/f H 1H=1/f H (Supply voltage condition: VSH = +8.0V, VSL = 5.0V) Notes: 18. Adjusted by variable resister (H-POS) in a module. 19. Variable by variable resister (H-POS) in a module. adjustment : tpd = 1.1 ± 0. 7 µs 20. Synchronized with HSY, based on falling timing of HSY. 21. VSY signal delays. 22. Independent sampling mode. 23. Simultaneous sampling mode. Display Time Range However, the video signals of NTSC (M) mode (NTP=High, CLKC=High) (14n+12)H, (14n+20) H/Even field. Displaying the following range within video signals. (14n+17)H, (14n+23) H/Odd field (n=1, 2..., 20) Horizontally: 12.2 ~ 63 µs from the falling edge of HSY. (SAM=High) are not displayed on the module. External Clock Mode (NTP=High, CLKC= Lo ) 12.3 ~ 62.9 µs from the falling edge of HSY. (SAM=Low) Vertically: 20 ~ 253 H Displaying the following range within video signals. Horizontally: 205 ~ 1164 clk from the falling edge of HSY. (SAM=High) from the falling edge of VSY. 84 ~ 403 clk from the falling edge of HSY. (SAM=Low) (clk means input external clock.) PAL(B-G) Mode (NTP=Low, CLKC=High ) Displaying the following range within video signals. Horizontally: 13.0 ~ 63.8 µs from the falling edge of HSY. (SAM=High) Vertically: 13.1 ~ 63.7 µs from the falling edge of HSY. (SAM=Low) Vertically: 26 ~ 298 H from the falling edge of VSY. Original specifications created by Sharp. Panelview Hillsboro, OR (503) 690-2460 Panelview is a subsidiary of White Electronic Designs Corporation 6 20 ~ 253 H from the falling edge of VSY. ENH050Q1-320/450/600 Panelview Enhancing the Vision OPTICAL CHARACTERISTICS TA=25°C Parameter Symbol Viewing angle ∆ θ 11 range ∆ θ 12 Condition CR ≥5 ∆θ2 Contrast ratio Min Typ 60 65 Max ° (degree) Unit 35 40 ° (degree) 60 65 ° (degree) CRmax Optimal 60 Response Rise tr θ = 0° 30 60 time Fall td 50 100 ms Y I L=6.5mArms 240 320 cd/m2 Luminance White chromaticity x I L=6.5mArms 0.263 0.313 0.363 y I L=6.5mArms 0.279 0.329 0.379 Remarks (1, 2) (2, 3) ms (2, 4) (5) Lamp life +25°C continuation 10,000 hour (6) time -30°C intermission 2,000 time (7) DC/AC inverter for external connection shown in following, Harison Electric Co., Ltd, HIU-288. Notes: 1. Viewing angle range is defined as follows. Fig. 1: Definition of Viewing Angle Normal line ∆θ2 ∆θ2 ∆ θ 12 ∆ θ 11 6 o'clock direction 2. Applied voltage condition: a. VCDC is adjusted so as to attain maximum contrast ratio. b. Brightness adjusting voltage (BRT) is open. c. Input video signal of standard black level and 100% white level. 3. Contrast ratio is defined as follows: Photodetector output with LCD being white Contrast ratio (CR) = Photodetector output with LCD being black Original specifications created by Sharp. 7 Panelview (503) 690-2460 www.whiteedc.com Panelview is a subsidiary of White Electronic Designs Corporation ENH050Q1-320/450/600 Panelview Enhancing the Vision 4. Response time is obtained by measuring the transition time of photodetector output, when input signals are applied so as to make the area black from white and white* from black. black Photodetector output (Relative Value) white white 100% 90% 10% 0% tr td time 5. Measured on the center area of the panel at a viewing cone 1° by TOPCON luminance meter BM-7. (After 30 minutes operation) DC/AC inverter driving frequency: 49kHz 6. Lamp life time is defined as the time when either "a" or "b" occurs in the continuous operation under the condition of lamp current IL=3~7. 0mArms and PWM dimming 100%~5%. (TA=25°C) a. Brightness becomes 50% of the original value. b. Kick off voltage at TA=30°C exceeds maximum value,1500Vrms. 7. The intermittent cycle is defined as a time when brightness becomes 50% of the original value under the condition of following cycle. Ambient temperature: -30°C HIGH (6.5mArms) OFF 5 min. 5 min. 5 min. 5 min. Original specifications created by Sharp. Panelview Hillsboro, OR (503) 690-2460 Panelview is a subsidiary of White Electronic Designs Corporation 8 ENH050Q1-320/450/600 Panelview Enhancing the Vision MECHANICAL CHARACTERISTICS - Terminal holding force: more than 0.9N/pin. (Each terminal is pulled out at a rate of 25 ±3mm/min.) By applying pressure on the active area it is possible to cause damage to the display. Input/Output Connector Performance Input/output connectors for the operation of LCD module (FPC connector 22 pin) - Applicable FPC Shown in Fig. 3. 23.0 1.0 21 +0.05 -0.05 +0.02 1.0 -0.02 0.7 +0.07 -0.05 +0.15 -0.15 (R0.5) 5 MIN 6 MIN 0.3 +0.1 -0.1 4 1 3 2 No. Name 1 Base material Materials 2 Copper foil Copper foil (35µm thick) Solder plated in 2 to 12µm 3 Cover lay Polyimide or equivalent material 4 Reinforcing plate Polyimide or equivalent material (25µm thick) Polyester polyimide or equivalent material (188µm thick) (Fig. 3) FPC applied to input/output connector (1.0mm pitch) I/O CONNECTOR OF BACKLIGHT DRIVING CIRCUIT Symbol Used Connector Corresponding connector CN1 BHR-02(8.0)VS-1N SM02(8.0)B-BHS-TB (wire to board) Manufacturer JST SM02(8.0)B-BHS-1N (wire to board) JST BHMR-03V(wire to wire) JST Original specifications created by Sharp. 9 Panelview (503) 690-2460 www.whiteedc.com Panelview is a subsidiary of White Electronic Designs Corporation ENH050Q1-320/450/600 Panelview Enhancing the Vision DISPLAY QUALITY a) Floor: Conductive treatment of 1MΩ or more on the tile (conductive mat or conductive paint on the tile) The display quality of the color TFT-LCD module shall be in compliance with the incoming Inspection Standard. b) Clean room free from dust and with an adhensive mat on the doorway HANDLING INSTRUCTIONS c) Advisable humidity:50%~70% Advisable temperature:15°C~27°C Mounting of Module The TFT-LCD module is designed to be mounted on equipment using the mounting tabs in the four corners of the module at the rear side. d) Workers shall wear conductive shoes, conductive work clothes, conductive gloves and an earth band. When mounting the module, the M2.6 tapping screw (fastening torque is 0.3 through 0.5Nm) is recommended. Make certain to fix the module on the same plane. Avoid warping or twisting the module. If the TFT-LCD module metal parts (shielding lid and rear case) become soiled, wipe them with a soft dry cloth. Wipe off water spots or finger grease immediately. Prolonged contact with water may cause discoloration or spots. Precautions in Mounting Polarizer which is made of soft material and susceptible to flaws must be handled carefully. A protective film (Laminator) is applied on the surface to protect it against scratches and dirt. It is recommended to peel off the laminator immediately before use, taking care with static electricity. The TFT-LCD module uses glass which breaks or cracks easily if dropped or bumped on a hard surface. Handle with care. Since CMOS LSI is used in this module, take care of static electricity and ground one's body when handling. Precautions in peeling off the laminator A) Working environment When the laminator is peeled off, static electricity may cause dust to stick to the polarizer surface. To avoid this, the following working environment is desired. Original specifications created by Sharp. Panelview Hillsboro, OR (503) 690-2460 Panelview is a subsidiary of White Electronic Designs Corporation 10 ENH050Q1-320/450/600 Panelview Enhancing the Vision Precautions in Adjusting Module SHIPPING REQUIREMENTS Variable resistor on the rear face of the module has been adjusted optimally before shipment. Therefore, do not change any adjusted values. If adjusted values are changed, the specifications described here may not be satisfied. Carton storage condition: Number of layers of cartons in stack : 10 layers max. Environmental condition: Caution of Product Design Temperature 0°C to 40°C 1) The LCD module shall be protected against water by the waterproof cover. Humidity 60%RH or less (at 40°C) No dew condition even at a low temperature and high humidity Others 1) Do not expose the module to direct sunlight or intensive ultraviolet rays for many hours: LCD Module will deteriorate from ultraviolet rays. 2) Store the module at a temperature near room temperature. When stored at lower than the rated storage temperature, liquid crystal solidifies, causing the panel to be damaged. When stored at higher than the rated storage temperature, liquid crystal turns into isotropic liquid and may not recover. 3) If LCD panel breaks, the liquid crystal could possibly escape from the panel. Since the liquid crystal is injurious, avoid contact with the eyes or mouth. Wash with soap immediately if contact with the liquid crystal occurs. Atmosphere Harmful gases such as acid and alkali which corrode electronic components and wires must not be present. Storage period Approximately 3 months Opening of package To prevent TFT-LCD module from being damaged by static electricity, adjust the room humidity to 50%RH or higher and make certain one is grounded before opening the package. RELIABILITY TEST ITEMS 4) Observe all other precautionary requirements in handling general electronic components. Reliability test items for the TFT-LCD module are shown on page 12. Original specifications created by Sharp. 11 Panelview (503) 690-2460 www.whiteedc.com Panelview is a subsidiary of White Electronic Designs Corporation ENH050Q1-320/450/600 Panelview Enhancing the Vision RELIABILITY TEST ITEMS FOR TFT-LCD MODULE No Test items Test conditions High temperature 1 storage test Tp= 85°C 240h Tp= 30°C 240h Tp= 60°C ⋅ 90~95%RH 240h operating test Tp= 85°C 240h Low temperature Tp= 30°C 240h Low temperature 2 storage test High temperature 3 and high humidity operating test High temperature 4 5 operating test 6 discharge test Electrostatic =200V ⋅ 200pF(0 Ω). Once for each terminal. 980m/s2 ⋅ 6ms. 7 ±X, ±Y, ±Z 3 times for each direction Shock test 8 (JIS C0041. A-7 Condition C) Vibration test Frequency range : 8~33. 3Hz Stroke : 1.3mm Sweep : 33.3Hz~400Hz Acceleration : 28.4m/s2 Frequency : 15min 2 hours for each direction of X, Z (1) 4 hours for direction of Y (8 hours in total) (JIS D1601) 30°C ~ 85°C/200 cycles 9 Heat shock test (0.5h) (0.5h) Tp = Panel temperature Evaluation Result Criteria: Note 1: Direction of X,Y,Z is defined as follows. 1 2 o' clock direction Z Y X 6 o' clock direction Original specifications created by Sharp. Panelview Hillsboro, OR (503) 690-2460 Panelview is a subsidiary of White Electronic Designs Corporation 12 ENH050Q1-320/450/600 Panelview Enhancing the Vision Fig. 3 Outline Dimensions of TFT-LCD module 126.8 ± 0.3 13 +0.3 -0.2 13 +0.3 -0.2 Screen center 42.4 RG B RG 89.9 MAX 79.8 (Case open area) 89.6 ± 0.3 Screen size (102.24 x 74.763) Direction of best viewing angle (6 o'clock) 107.4 (Case open area) 960H x 234V dots 13 +0.3 -0.2 0.2 +0.1 -0.1 +0.3 5 5 9.5 16.5 -0.2 3 3 datum line 2.2 89.2 11 31.2 2.2 datum line 03A Rear View Original specifications created by Sharp. 13 Panelview (503) 690-2460 www.whiteedc.com Panelview is a subsidiary of White Electronic Designs Corporation Backlight TFT-LCD panel Source driver Gate driver Control circuit Original specifications created by Sharp. 14 Fig. 4 Circuit block diagram of TFT-LCD module Backlight driving signal Video interface circuit Amplifying polarity inversion Sync. separator VSH VSL VHL VCDC BRT Power supply for backlignt RGB video signal 2 RGB video signal 1 VBS VSW NTP HSY VSY CLK CLKC GND Power supply VSH, VSL (Caution) * Not included in the module Backlight * driving circuit VSH Panelview LCD driving signal Common driving signal (COM) Gate driver driving signal Source driver driving signal Gate driver power supply circuit FRP HSY VSW Panelview Hillsboro, OR (503) 690-2460 Panelview is a subsidiary of White Electronic Designs Corporation SYN Gate driver power supply +5.3V Regulator Enhancing the Vision ENH050Q1-320/450/600 15 clock 0 5V 0 5V 0 5V A G D B (INPUT) 0.7VPP (Note) input impedance of A, B, D: >10kΩ input impedance of C: >50kΩ G: vertical sync. horizontal sync. 0 +5V -5V +8V HSY VSY PWM N/P HRV VRV VSW SAM VCDC VSH VBS BRT VRI VGI VBI VSL VR2 VG2 VB2 GND CLKC CLK 1kΩ I 1kΩ 8.2kΩ 560Ω 560Ω 560Ω 560Ω 560Ω 560Ω 560Ω C-MOS LSI 0.01xF 0.01xF 0.01xF 0.01xF 0.01xF 0.01xF +5.3V IC C-MOS LSI C-MOS LSI C-MOS LSI IC 10kΩ 2kΩ 15kΩ 8.2kΩ 50kΩ Driver ICs COM -5V +8V Driver ICs IC 47kΩ +5.3V TFT-LCD Module Regulator +5.3V 10kΩ Fig. 5 Recommended Circuit SW SW I/O Connector Panelview F: E: D: C: B: 5V +8V 0.7VPP -5V C 1VPP under HV E F GND A: (Gray scale) I/O Signals Enhancing the Vision ENH050Q1-320/450/600 Original specifications created by Sharp. Panelview (503) 690-2460 www.whiteedc.com Panelview is a subsidiary of White Electronic Designs Corporation Panelview Hillsboro, OR (503) 690-2460 Panelview is a subsidiary of White Electronic Designs Corporation 0.7 Vp-p tpv1 Original specifications created by Sharp. 16 tVHO trVO Vertical display period: HSY VSY 234H (NTSC) 273H (PAL) t fHO tpv2 tVHO even field Fig. 6-A Input/Output signal waveforms (CLKC= "High") 19H (NTSC) 25H (PAL) tvs detailed 1.0 Vp-p odd field trHO tfVO Panelview HSY VIDEO (R,G,B) VSY VBS 3H (NTSC) 2.5H (PAL) 16.7ms (NTSC) 20ms (PAL) Enhancing the Vision ENH050Q1-320/450/600 Video signal VR1~VB1 or VR2~VB2 HSY VBS 17 50% 50% 12.3 µs (NTSC, SAM Low) 13.0 µs (NTSC, SAM High) 13.4 µs (NTSC, SAM Low) 12.2 µs (NTSC, SAM High) tHS2 tpd tHS1 tfH0 90% 10% trH0 Panelview Fig. 6-B Input/Output signal waveforms (CLKC="High") Horizontally display area 50.6µs (SAM "Low") Horizontally display area 50.8µs (SAM "High") 1H=63.5µs (NTSC) 1H=64.0µs (PAL) Enhancing the Vision ENH050Q1-320/450/600 Original specifications created by Sharp. Panelview (503) 690-2460 www.whiteedc.com Panelview is a subsidiary of White Electronic Designs Corporation Panelview Hillsboro, OR (503) 690-2460 Panelview is a subsidiary of White Electronic Designs Corporation Original specifications created by Sharp. 18 HSY 1185 1185 1190 1195 1195 1200 RESET 1200 0 1205 Fig. 6-C Input/Output signal waveforms (CLKC="High") 1190 RESET 5 0 52.9 ns 10 Panelview INDEPENDENT SAMPLING MODE (DOT CLOCK) SIMULTANEOUS SAMPLING MODE (PIXEL CLOCK) SYSTEM CLOCK PAL MODE HSY INDEPENDENT SAMPLING MODE (DOT CLOCK) SIMULTANEOUS SAMPLING MODE (PIXEL CLOCK) SYSTEM CLOCK NTSC MODE Enhancing the Vision ENH050Q1-320/450/600 ENH050Q1-320/450/600 Panelview HSY tH01 1H trVO tfCLI HSY VSY HSY HSY VSY tHI trCLI CLK Fig. 6-D Input/Output signal waveforms (external clock mode NTP="High", CLKC="Low") tH02 tSU1 tWL tWH tfH12 trH12 tfVO tSU2 Enhancing the Vision Original specifications created by Sharp. 19 Panelview (503) 690-2460 www.whiteedc.com Panelview is a subsidiary of White Electronic Designs Corporation Panelview Hillsboro, OR (503) 690-2460 Panelview is a subsidiary of White Electronic Designs Corporation Original specifications created by Sharp. 20 1/2H 1/2H 1H magnify TIME range 89H 105H 89H (PAL) 105H (NTSC) Period of stop DC/AC inverter oscillation Fig. 7 PWM signal waveform for dimming backlight Period of DC/AC inverter oscillation nH nH 525H (NTSC) 625H (PAL) Panelview PWM HSY VSY (PAL) PWM (NTSC) PWM VSY Enhancing the Vision ENH050Q1-320/450/600 ENH050Q1-320/450/600 Panelview Enhancing the Vision Normal line ADJUSTING METHOD OF OPTIMUM COMMON ELECTRODE DC BIAS VOLTAGE Photodetector (including luminosity factor) To obtain optimum DC bias voltage of common electrode driving signaI(VCDC). Photo-electric devices are very effective, and the accuracy is within 0.1V. (In visual examination method, the accuracy is about 0.5V because of the difference among individuals.) θ To gain optimum common electrode DC bias voltage, there is the following method which uses the photoelectric device. Polarizing filter (Measurement of flicker) DC bias voltage is adjusted so as to minimize NTSC: 60Hz (30Hz) PAL: 50Hz (25Hz) flicker. Frame LCD panel Backlight (Plane source) Photo-electric device Output voltage Brightness: Less than 5000cd/m2 Wave length: To be cut less than 400nm Oscilloscope (X-Y recorder) VCDC LCD Fig. 9 Optical characteristics Fig. A Measurement system Photo-electric output voltage is measured by an oscilloscope at a system shown in Fig.A. DC bias voltage must be adjusted so as to minimize the NTSC:60Hz(30Hz) PAL:50Hz(25Hz) flicker with DC bias voltage changing slowly. (Fig. B) DC bias: Optimum + 1V DC bias: Optimum Fig. B Waveforms of flicker Original specifications created by Sharp. 21 Panelview (503) 690-2460 www.whiteedc.com Panelview is a subsidiary of White Electronic Designs Corporation