SLWS130 GC3011 DIGITAL RESAMPLER 1.0 KEY FEATURES • 80 million samples per second (MSPS) input rate • • Fractional rate change down to 1/4th the input rate Synchronization logic to allow multi-chip complex data operation. Multiple chips can be synchronized with fixed delay offsets. Two chips allow rate changes up or down. 12 bit data I/O 32 bit rate control accumulator 16 sample output FIFO 15 tap linear phase interpolator 4096 interpolation steps 80% input passband (0 to 0.4FCK) • • • • • • • • 1.1 • • • • • +/- 0.1 dB passband ripple Less than +/- 0.02 degrees rms phase jitter -73 dB image rejection 60 dB worst case NPR Adaptive rate change to lock the resampling ratio to the output clock rate PLL/VCO to generate an output clock to match the rate change Microprocessor interface for control, output, and diagnostics Built in diagnostics 2W power at 50 MHz, 5 volts 520 mW at 30 MHz, 3.3 volts 100 pin QFP package • • • • • • BLOCK DIAGRAM A block diagram illustrating the major functions of the chip is shown in Figure 1 CV,FOZ,FIZ DC[0:11] M/S FRST DIN[0:11] OCK SI CK 12 bits 12 bits INTERPOLATION CONTROL TO ALL CIRCUITS INTERPOLATION RATIO AND MODES MULTI-CHIP SYNC AND OFFSET INTERPOLATION FILTER 15 TAPS 4096 STEPS OUTPUT MODES RESET IN CLK IN EIN EVAL C[0:8] R/W INTERPOLATION RLL 4 bits 8 bits CONTROL IFACE A[0:3] SYNC CIRCUIT 16 SAMPLE FIFO ERROR SI CLK OUT SO OUT INTERPOLATION RATIO INTERPOLATION MODES ERROR ERROR OUTPUT CLOCK GENERATOR (FIXED CLOCK MODE OR PLL AND VCO) DATA BYPASS OUTPUT MUX AND FORMAT 12 bits OUTPUT MODES FE HF DOUT[0:11] DVAL SO CKOUT CK2X CS Figure 1. GC3011 Block Diagram -1- JULY 22, 1996 This document contains information which may be changed at any time without notice CVOUT CVIN GC3011 DIGITAL RESAMPLER 2.0 FUNCTIONAL DESCRIPTION Fabricated in 0.7 micron CMOS technology, the GC3011 chip is a general purpose digital resampler chip designed to accurately reduce the sample rate of the input data stream by a fractional amount ranging from 1.0 down to 0.25. The chip includes an interpolation control block, a multi-chip synchronization and offset circuit, a 15 tap interpolation filter, a 16 word output FIFO memory, an output clock generator and an interpolation ratio rate-lock loop (RLL) circuit. In addition, an output multiplexor circuit allows the user to by-pass the FIFO and output the resampled samples directly. A control interface allows the user to set the resampling modes, resampling rate and output clocking modes. The multi-chip sync and offset circuit allows multiple GC3011 chips to be synchronized in a master/slave configuration. The offset portion of the circuit allows each chip’s interpolation delay to be offset by a fixed amount relative to the other chips. The GC3011 chip accepts input rates up to 70 MHz. The chip can operate in a fixed resampling mode where the user specifies the desired output rate, or the chip can be configured to adapt the resampled rate to match an externally provided output clock. The resampled data can be output synchronous to the input clock or can be output synchronous to the output clock. When output synchronous to the input clock the samples are accompanied by a data valid flag to indicate which samples are valid and which are invalid. When output synchronous to the output clock the chip uses the internal 16 word FIFO to smooth the data. The output clock can be provided externally, or can be generated within the chip using the internal oscillator which is locked to the resampled data rate. The chip does not provide any anti-alias filtering. The user must bandlimit the input signal before it is down-sampled by the GC3011 chip. The GC2011 digital filter chip can be used for this purpose. Fractional upsampling can be achieved by using the GC2011 digital filter chip to up sample the signal by a factor of two before it is downsampled by the GC3011. On chip diagnostic circuits are provided to simplify system debug and maintenance. The chip receives configuration and control information over a microprocessor compatible bus consisting of an 8 bit data I/O port, a 4 bit address port, a read/write bit, and a control select strobe. The chip’s 16 control registers (8 bits each) are memory mapped into the 4 bit address space of the control port. 2.1 CONTROL INTERFACE The chip is configured by writing control information into sixteen control registers within the chip. The contents of these control registers and how to use them are described in Section 4.0. The registers are written to or read from using the C[0:7], A[0:3], R/W, and CS pins. Each control register has been assigned a unique address within the chip. An external processor (a microprocessor, computer, or DSP chip) can write into a register by setting A[0:3] to the desired register address, setting the R/W pin low, setting C[0:7] to the desired value and then pulsing CS low. To read from a control register the processor must set A[0:3] to the desired address, set R/W high, and then set CS low. The chip will then drive C[0:7] with the contents of the selected register. After the processor has read the value from C[0:7] it should set CS high. The C[0:8] pins are turned off (high GRAYCHIP,INC. -2- JULY 22, 1996 This document contains information which may be changed at any time without notice GC3011 DIGITAL RESAMPLER impedance) whenever CS is high or R/W is low. The chip will only drive these pins when CS is low and R/W is high. 2.2 SYNC CIRCUIT The sync circuit is used to synchronize the chip during diagnostics or system initialization. The sync circuit includes a 20 bit counter which can be programmed to generate terminal count (TC) sync pulses every 28, 212, 216 or 220 input clock cycles. The counter can be synchronized to the SI sync input, or left to free run. The SI and TC sync pulses can be used to synchronize or clear the counters, accumulators or state machines found within the rest of the chip. The lower 12 bits of the counter are used as input samples to the resampler during diagnostics. The user may select which sync signal is output from the chip on the SO pin. The SO signal can be either a delayed version of the sync input, the counter’s TC sync, or a one-shot pulse. The sync output signal is one clock cycle wide, synchronized to the output clock (OCK). 2.3 INTERPOLATION FILTER The interpolation filter is used to interpolate between input data samples in order to generate output samples at fractional time delays relative to the input samples. The filter is a 15 tap FIR filter with 4096 sets of coefficients. Each set of coefficients corresponds to a different time delay between input samples. The circuit accepts a new delay control word (12 bits) every clock cycle which tells it which set of coefficients to use during that clock cycle. This allows the interpolation time delays to vary every clock sample. Interpolating to 4096 delay values gives a worst case phase error (phase jitter) of +/- 360/8192 = +/- 0.09 degrees. The delay control word can either come from the interpolation control circuit described below, or from an external source. The external input allows multiple resamplers to be synchronized to controls coming from a common resampler chip in a master/slave arrangement. 2.4 INTERPOLATION CONTROL The interpolation control circuit is used to generate the time delay control words used by the interpolation filter. The interpolated output rate is specified as the ratio of the input rate to the output rate. This ratio is limited to be within the range of 1 to 4 and is formatted as a 32 bit word. The most significant 2 bits are the integer portion of the ratio and the lower thirty bits are the fractional part. This ratio is equivalent to the ratio of the output sample spacing to the input sample spacing. The interpolation ratio feeds a 32 bit accumulator. The 2 bit integer portion of the accumulator’s output is used to determine the number of input samples to skip between output samples, and the upper 12 bits of the fractional part is used as the interpolation filter’s delay control word. GRAYCHIP,INC. -3- JULY 22, 1996 This document contains information which may be changed at any time without notice GC3011 DIGITAL RESAMPLER 2.5 INTERPOLATION RLL The interpolation ratio can be fixed by the user, or can be allowed to adapt to the ratio that keeps the output FIFO half-full. The adaption is performed by the interpolation rate lock loop (RLL) circuit. Figure 2 is a block diagram showing the interpolation RLL circuit and the interpolation control circuit. INTERPOLATION RATIO 2-A OR CLEAR EIN EVAL ERROR DELAY CONTROL WORD (12 BITS) DELAY ACCUMULATOR MUX ERROR FROM FIFO 32 bits 32 bits CLEAR 2-B OR CLEAR 32 bits LATCH 16 MSBs EXT_ERR TO CONTROL INTERFACE RATIO_HOLD RATE-LOCKED-LOOP INTERPOLATION CONTROL Figure 2. Interpolation RLL And Control Circuits 2.5.1 Fixed Interpolation Mode The fixed interpolation mode is used when the user knows what the desired output rate should be relative to the input rate. For example, a user may wish to use this mode when he is using the resampler to baud synchronize a modem signal. In this case the user has an external baud rate detection circuit which tells the user how to adjust the interpolation ratio. The user fixes the interpolation ratio by turning off (clearing) the Rate-Locked-Loop (RLL) circuit. Clearing the RLL output fixes the delay accumulator’s input to be the 32 bit value supplied by the user. 2.5.2 Adaptive Interpolation Mode In this mode the RLL circuit automatically adjusts the interpolation ratio to keep the FIFO half full. This mode is used when the output clock is fixed and the chip’s interpolation ratio must exactly match the ratio between the chip’s input clock and the output clock. For example, a user may wish to use the adaptive interpolation mode in order to interface two asynchronous signal processing systems, or when an external baud sync circuit has provided a baud synchronous output clock. The adaption uses an error signal from the FIFO. The error is a bit indicating the error is plus or minus one. A minus one indicates that the FIFO is less than half full and the interpolation ratio (the ratio of the input rate to the output rate) needs to be decreased. A plus one indicates that the FIFO is more than half full and the interpolation ratio needs to be increased. The user sets up the adaptive interpolation mode GRAYCHIP,INC. -4- JULY 22, 1996 This document contains information which may be changed at any time without notice GC3011 DIGITAL RESAMPLER by setting the interpolation ratio to a value close to the actual ratio1 and setting the adaption constants 2-A and 2-B, where A and B are constants ranging from 0 to 31. These constants set the adaption rate and the tracking bandwidth of the adaption loop. These constants can also be set to zero in order to clear the 2-A or 2-B feedback paths or to freeze the adaption process. A large value for B will slow the adaption process and will reduce the phase jitter, but will also decrease the tracking bandwidth of the loop. The adaption time when the interpolation ratio starts at zero will be approximately 2B clock cycles. The tracking bandwidth of the loop is determined by how fast the loop will adapt to an output rate change and if it adapts fast enough to prevent a FIFO overflow or underflow error. Since the FIFO has a range of +/- 8 samples, the tracking range in Hz is approximately 2(3-B) times the input clock rate2. The constant 2-A is used to dampen the adaption loop to prevent ringing. The value of A should be approximately one-half of B. Note that small values of A will introduce residual phase jitter equal to +/360x2-A degrees. The values of A and B are application dependant. If adaption time is important, then a two-stage adaption process may be desirable. An initial setting of B equal to 16 and A equal to 12 will allow the loop to converge rapidly. Once the loop has converged, A and B can be set to minimize residual phase noise. Settings between 22 and 31 for B and between 14 and 15 for A are suggested. A setting of B=22 gives a tracking bandwidth of 128 Hz. A setting of B=31 would reduce the tracking bandwidth to about 0.25 Hz. 2.5.3 External Adaption Mode The RLL can be adapted from an external error signal using the EIN and EVAL inputs to the chip. In this mode the user uses an external circuit to detect resampling rate errors and drives the EIN with a 0 or a 1. A ‘1’ means increase the ratio and a‘0’ means decrease it. A high level on the EVAL signal identifies when the EIN signal is valid. The EVAL and EIN signals are clocked into the chip on the rising edge of the input clock. 2.5.4 The Ratio-Hold Register The user can monitor current resampling ratio using the Ratio-Hold Register. This register captures and holds the most significant 16 bits of the current resampling ratio when the RATIO_HOLD bit is set (See Section 4.8). This register can be used to determine if the resampler has converged in the adaptive interpolation mode (See Section 2.5.2 above). 1. This speeds up the adaption, but is not necessary for the adaption to work. The ratio can be set to zero if desired. 2. The chip will converge to the correct interpolation ratio outside of the tracking bandwidth, but while it is converging the FIFO will overflow or underflow so that the data output will be corrupted until it re-converges. GRAYCHIP,INC. -5- JULY 22, 1996 This document contains information which may be changed at any time without notice GC3011 DIGITAL RESAMPLER 2.6 MULTI-CHIP SYNC AND OFFSET CIRCUIT The multi-chip sync and offset circuit allows multiple chips to be used in parallel, all locked to the same resampling ratio and phase. The circuit also allows each chip to be offset by a fixed time delay relative to the others. A block diagram of the circuit is shown in Figure 3. DC[0:11] CV FIZ FOZ M/S BI-DIR CONTROL Delay Control From Delay Accumulator MUX NOTE: FOZ and FIZ go to the FIFO Delay Control OFFSET Control Valid Valid Multi-chip Mode Delay Offset 14 bits Figure 3. Multi-chip Synchronization And Offset Circuit Multiple chips are synchronized in a master/slave configuration. The M/S control pin is high for the master chip and is low for the slave chip. The master chip drives the bi-directional DC, CV, FIZ, and FOZ pins as outputs. The slave chips use the pins as inputs. The multi-chip mode control signal selects between the internal filter controls and the external ones. The master chip sends the 12 delay control bits (DC) and the control valid strobe (CV) to the slave chips. The slave chips accept the DC and CV signals, add a delay offset to them and output the delay control and control valid strobes to the resampler filter. The FIZ and FOZ flags are used to lock the FIFOs in the slave chips to the master chip’s FIFO. The FOZ and FIZ flags go high each time the fifo read or write address counters on the master chip go to zero. These flags clear the read or write counters on the slave chips. FOZ controls the read counters, FIZ controls the write counters. 2.7 OUTPUT FIFO The 16 sample FIFO is used to smooth the output interface between data being generated synchronous to the input clock and data being output synchronous to the output clock. If the interpolation ratio is correct, then the FIFO would only need to be one or two samples deep. Since the ratio can not be exact, the FIFO has been expanded to 16 words to allow a +/- 8 sample buffer. The +/- 8 sample buffer prevents the FIFO from overflowing or underflowing while the RLL circuit (or an external adaption loop) adapts to variations in the output clock. GRAYCHIP,INC. -6- JULY 22, 1996 This document contains information which may be changed at any time without notice GC3011 DIGITAL RESAMPLER Output samples are clocked into the FIFO by the interpolation control circuit at a rate determined by the interpolation ratio. For example, if the interpolation ratio is set at 1.5, then two samples will be clocked into the FIFO for every 3 input clocks. If the ratio is 2.25, then four samples would be stored in the FIFO for every nine input clocks. The FIFO timing for a ratio of 1.5 is shown in Figure 4. INPUT CLOCK FIFO INPUT (FROM FILTER) Y9 Y10 Y11 Y12 Y13 Y15 Y14 FIFO INPUT CLOCK VALID FLAG FIFO OUTPUT CLOCK FIFO OUTPUT (TO DOUT) Y0 Y1 Y2 Y3 Y4 Y5 Y6 Figure 4. Fifo Timing 2.7.1 FIFO ERRORS Notice that the output data samples in Figure 4 are delayed by 8 clock cycles relative to the input samples. This is the ideal case when the FIFO is half full. If the output clock is faster than the FIFO input clock, then the FIFO will empty and an underflow error will occur. If the output clock is slower than the FIFO input clock, then the FIFO will fill up and an overflow error will occur. The FIFO will remain in the overflow or underflow condition until the I/O rates change and the FIFO begins to empty or fill, or until the FIFO is reset. The output samples will not be valid when an underflow/overflow error occurs. The FIFO generates half full and FIFO error flags. The half full flag is high whenever the FIFO contains more than 8 samples. The FIFO error flag is high whenever the FIFO contains less than 2 or more than 14 samples. The FIFO half full and error flags are output from the chip on the HF and FE pins. The user can also monitor the FIFO using the HALF_FULL, FIFO_FULL, FIFO_EMPTY and FIFO_DEPTH control bits in the FIFO control register (see Sections 4.8 and 4.9). The FIFO_FULL and FIFO_EMPTY control bits are set when an overflow or underflow condition occurs and will remain set until the user clears the bits. The FIFO_DEPTH is a read only 4 bit field which reflects the depth of the FIFO. The depth is encoded as a 4 bit gray scale number to minimize errors when reading the FIFO depth. The mapping between grayscale and binary is as follows: FIFO_EMPTY HALF_FULL FIFO_FULL GRAY SCALE: 0 1 3 2 6 7 5 4 C D F E A B 9 8 HEX: 0 1 2 3 4 5 6 7 8 9 A B C D E F GRAYCHIP,INC. -7- JULY 22, 1996 This document contains information which may be changed at any time without notice GC3011 DIGITAL RESAMPLER 2.7.2 FIFO RESET The FIFO is initialized to its half full state by setting the FRST pin high or by using the FIFO_RESET control mode (See Section 4.6). The FIFO will remain in the half full state until the FRST pin is set low. The 8 outputs following a FIFO_RESET will be invalid. 2.8 OUTPUT CLOCK GENERATOR The resampled data can be output either synchronous to the input clock, synchronous to an internally generated output clock, or synchronous to an externally provided output clock. A separate clock input pin (OCK) is provided for the output data clock. The user connects this clock pin to either the input clock, the internally generated resampled clock (CKOUT), or to an externally provided clock as described below. 2.8.1 Synchronous Output Mode In this mode the output FIFO is bypassed and the data is output synchronous to the input clock. The samples are accompanied by a data valid strobe (DVAL) which indicates whether the user should skip or accept each output sample. The polarity of the strobe can be programmed as active high or low depending upon how the user wants to use it. A typical use of the DVAL strobe would be as an enable strobe to external registers or FIFOs. In the DVAL_EARLY mode (See Section 4.6) the DVAL signal is active one clock cycle early so that it can be used as a clock enable to the GC2011 or GC3021 chips which expect the clock enable to arrive one clock earlier than the data. In the synchronous output mode the input clock pin (CK) must be tied to the output clock pin (OCK). 2.8.2 Internally Generated Clock A voltage controlled oscillator (VCO) and charge-pump phase-lock-loop (PLL)1 is built into the GC3011 to generate a smooth clock to match the resampled data rate. The VCO consists of a odd number of inverters connected in a ring (commonly known as a ring oscillator). The clock frequency is controlled by dividing the ring oscillator output by a factor of 2n, by varying the number of stages in the ring and by adjusting a control voltage. The output of the ring oscillator can be divided by 2n where n ranges from 0 to 15. The number of stages in the ring oscillator can be varied digitally from 1 to 16. Each stage is non-inverting, a final stage provides the feedback inversion. The control voltage adjusts the delay of each stage and hence the frequency of oscillation. The control voltage can adjust the oscillation frequency in either a narrow range adjust mode or wide range adjust mode. In the narrow mode the control voltage can adjust the frequency by ±12%. These parameters allow the output clock to be generated with a minimum frequency of 10 KHz and a maximum frequency of 80 MHz. 1. F. M. Gardner, “Charge-Pump Phase-Lock-Loops”, IEEE Transactions on Communications, vol. COM-28, pp. 1849-1858, Nov. 1980 GRAYCHIP,INC. -8- JULY 22, 1996 This document contains information which may be changed at any time without notice GC3011 DIGITAL RESAMPLER The chip outputs the resampled clock on the CKOUT pin. This clock will drive up to 40 pF of load. In a typical application the user will connect the CKOUT pin to an external clock buffer or driver chip. The output of the driver chip is then used to drive the output clock (OCK) pin as well as any circuitry accepting the GC3011 chip’s output data. This guarantees that the output data will be clocked out of the GC3011 chip using the same clock edge that the follow-on circuitry uses to accept it. The chip also generates a double rate clock (CK2X). This clock is twice the rate of the CKOUT clock and is locked to the CKOUT clock so that the rising and falling edges of CKOUT line up with rising edges of the CK2X. The chip automatically adapts the clock division ratio, the number of stages in the ring oscillator and the control voltage so as to generate a clock which matches the resampled data rate and keeps the FIFO half full. The adaption time is typically very short (less than 2000 output clock cycles). The VCO/PLL will then track variations in temperature, supply voltage and resampling ratio over a ± 12% range. The user must check that the ± 12% is adequate for the application. To do this one must estimate the maximum temperature variation, the maximum supply voltage variation and the maximum resampling rate variation for the resampler and then use the following dependencies to estimate the adequate tracking range. The temperature dependence of the VCO is -0.27%/C. The voltage dependence of the VCO is 18%/V at 5 volts and 40% per volt at 3.3 volts. For example, if the temperature at adaption time is 100 ˚C and is expected to vary ± 20 ˚C, and if the voltage at adaption time is 5V and is expected to vary ± 0.1V, and if the resampled data rate is expected to change by 0.1%, then the total range required is: VCO range = ± (0.27×20 + 18 × 0.1 + 0.1) = ± 7.3% which is well within the ±12% allowable range. The CLOCK control registers (see Section 4.7) allow the user to force, if necessary, the divider and ring oscillator length settings. The VCO status register allows the user to monitor the divider and length settings. 2.8.3 Extended VCO Range Mode The pull range of the VCO can be extended by setting the EXTENDED_RANGE bit in the CLOCK control registers (See Section 4.7). This mode doubles the pull range to ±24%to allow a wider variance due to temperature or voltage fluctuations. This mode increases the phase jitter of the VCO. GRAYCHIP,INC. -9- JULY 22, 1996 This document contains information which may be changed at any time without notice GC3011 DIGITAL RESAMPLER 2.8.4 Selecting External Components for the PLL The recommended analog supply filter and loop filter is shown in Figure 5. LOOP FILTER SUPPLY FILTER VCC Digital VCC Analog Vcc AVCC GC3011 CVIN Control Voltage 10uF 0.1uF R CVOUT AGND 47 Ohms C1 C2 Analog Gnd 47 Ohms GND Digital GND Figure 5. Supply and Loop Filters All components shown in figure 5 should be placed as close as possible to the package. CVIN and CVOUT should be shorted together. Separate CVIN and CVOUT pins are provided for specialized applications that need an active loop filter. The supply filter is used to isolate the analog power pins from the noise on the digital supply. This filter will cause a slight drop in the analog VCC voltage. At 5 volts the drop is about 0.2 volts. At 3.3 volts the drop is about 0.1 volts. The PLL bandwidth and damping are set by the resistor R and the capacitors C1 and C2. The resistor R sets the loop gain K (which should be 1-10% of FOUT) using the formula: 2π × K R = -----------------K 0 × Ip Where the pump current Ip is: Ip = 0.16 × (V-1) mA and the VCO gain K0 is: K0 = 0.785 Fout (at 5V) or (EQ 1) K0 = 1.047 Fout (at 3.3V) The fastest response is achieved by using critical damping. Underdamping introduces oscillations that can rapidly increase the response time. Overdamping reduces overshoot but gradually increases response time. One should select a damping factor that minimizes response time without introducing significant oscillations. Overdamping is preferred to underdamping. The damping factor should be between 0.7 and 1.4 (critical damping is 0.7). Let ζ be the damping factor. 4×ζ×ζ C 1 = --------------------K×R GRAYCHIP,INC. - 10 - (EQ 2) JULY 22, 1996 This document contains information which may be changed at any time without notice GC3011 DIGITAL RESAMPLER The PLL uses a third order loop to reduce jitter due to voltage across R while the pump current is active. The third order loop is accomplished using a second capacitor C2, which should be significantly smaller than C1. Generally, C2 = C1 / 100 Suggested values for R, C1 and C2 are shown in Table 1: Table 1: Suggested PLL Filter Components FOUT Loop BW R C1 C2 (MHZ) (% of FOUT) (Ohms) (µF) (µF) 1 10 20 40 60 2.8.5 1 125 3.0 0.03 10 1250 0.03 0.0003 1 125 0.3 0.003 10 1250 0.003 0.00003 1 125 0.2 0.002 10 1250 0.002 0.00002 1 125 0.08 0.0008 10 1250 0.0008 0.000008 1 125 0.05 0.0005 10 1250 0.0005 0.000005 External Output Clock Mode The FIFO output can be clocked using an externally provided clock. Samples will be output from the chip synchronous to the rising edge of this clock. This mode is used when the user has an external output clock, or when multiple chips are being synchronized to an output clock generated by one of a bank of resampler chips. In this mode the OCK clock pin is driven by the external clock. 2.9 POWER DOWN MODES The chip has a power down and keep alive circuit. This circuit contains a slow, nominally 1 KHz, oscillator and a clock-loss detect cell. This circuit is used to detect the loss of clock and provide a slow keep-alive clock to the chip. The circuit is also used to power down the chip by switching from the high speed input clock to the low speed keep-alive clock. The low speed clock rate is slow enough to power down the chip while fast enough to refresh the dynamic nodes within the chip. The user can select whether this circuit is in the automatic clock-loss detect mode, is always on (power down mode), or is disabled (the slow clock never kicks in). GRAYCHIP,INC. - 11 - JULY 22, 1996 This document contains information which may be changed at any time without notice GC3011 DIGITAL RESAMPLER 2.10 DIAGNOSTICS An input ramp generator, a sync period generator, and a checksum generator are provided on the chip in order to run diagnostic tests. Diagnostics are performed by turning on the ramp generator, enabling the diagnostic syncs, letting the chip operate for at least 4 sync periods, reading the checksum and comparing it to its predicted value. A new checksum is generated every sync period. The input ramp sequence is the same for every sync period and the chip is re-initialized at the beginning of each sync period so that each checksum should be the same once the chip’s data path has been flushed. The chip requires at least 3 sync periods to flush, so the fourth and following checksums should be valid. The test is then repeated for several different resampling ratios and mode settings. The sync period is 220 clocks, or approximately 1 million clock cycles, so four sync periods will be about 4 million clocks. This represents a delay of less than 70 milliseconds for a clock rate of 60 MHz. The following table lists the expected checksums for four test configurations. All values are in HEX. CONTROL REGISTER TEST 1 TEST 2 TEST 3 TEST 4 ? ? ? TBD EXPECTED CHECKSUMS (REG 15) GRAYCHIP,INC. ? - 12 - JULY 22, 1996 This document contains information which may be changed at any time without notice GC3011 DIGITAL RESAMPLER 3.0 PACKAGING The GC3011 chip comes in a 100 pin plastic quad flatpack package 0.35 mm (0.014") 3.7mm (0.146") 17.9 mm (0.705") 14.0 mm (0.551") A3 (MSB) A2 A1 A0 R/W CS FRST CV FOZ FIZ PLL ANALOG PINS M/S 38 37 34 33 32 31 30 29 28 27 22 21 20 98 19 18 GC3011 RESAMPLER DO1 DO0 VCC GND VCC GND C0 C1 C2 C3 C4 C5 C6 C7 VCC GND A0 A1 A2 A3 CS R/W GND VCC DI0 DI1 DI2 DI3 DI4 DI5 23.9 mm (0.941") VCC GND FOZ SO OCK VCC GND DVAL DO11 DO10 DO9 DO8 DO7 VCC GND DO6 DO5 DO4 DO3 DO2 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 0.65 mm (0.256") 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 (MSB) DC11 DC10 DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0 8 11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 DC6 DC7 DC8 DC9 VCC GND DC10 DC11 CK SI EIN EVAL DI11 DI10 DI9 DI8 DI7 DI6 GND VCC C7 (MSB) C6 C5 C4 C3 C2 C1 C0 AVCC CVIN CVOUT AGND GND VCC VCC CKOUT GND GND CK2X VCC VCC GND FRST FE HF M/S FIZ CV DC0 DC1 GND VCC VCC GND DC2 DC3 DC4 DC5 20.0 mm (0.787") CKOUT CK2X OCK 1 15 FE HF MULTI-CHIP SYNCHRONIZATION PINS 59 60 93 16 17 CVIN 61 62 63 64 CK CVOUT 67 68 69 70 71 72 73 74 DVAL 2 96 97 GC3011 RESAMPLER AGND 39 EIN EVAL 92 91 90 89 88 85 84 83 82 81 80 79 SO SI 3 41 42 (MSB) DO11 DO10 DO9 DO8 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 AVCC 40 DI11(MSB) DI10 DI9 DI8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 4 43 44 45 46 47 48 51 52 53 54 55 56 100 PIN QUAD FLAT PACK (TOP VIEW) GC3011-PQ: PLASTIC PACKAGE GC3011-CQ: CERAMIC PACKAGE VCC PINS:6,7,12,13,24,25,35,50,57,66,76,78,87,95,100 GND PINS:5,9,10,14,23,26,36,49,58,65,75,77,86,94,99 NOTE: 0.01 to 0.1 µf DECOUPLING CAPACITORS SHOULD BE PLACED AS CLOSE AS POSSIBLE TO EACH SIDE OF THE CHIP GRAYCHIP,INC. - 13 - JULY 22, 1996 This document contains information which may be changed at any time without notice GC3011 DIGITAL RESAMPLER 3.1 PIN DESCRIPTIONS SIGNAL DESCRIPTION DI[0:11] INPUT DATA. Active high The 12 bit two’s complement input samples. New samples are clocked into the chip on the rising edge of the clock. The input data rate is assumed to be equal to the clock rate. CK INPUT CLOCK. Active high The clock input to the chip. The input signals are clocked into the chip on the rising edge of this clock. OCK OUTPUT CLOCK. Active high The output signals are clocked out of the chip on the rising edge of this clock. SI SYNC IN. Active low The sync input to the chip. All timers, accumulators, and control counters are, or can be, synchronized to SI. This sync is clocked into the chip on the rising edge of the input clock (CK). EIN ERROR IN. Active high The external error input to the rate-lock-loop circuit. This signal is sampled on the rising edge of the input clock (CK). EVAL ERROR VALID. Active high EVAL identifies when the error to the RLL is valid. The rate-lock-loop circuit updates when EVAL is high. This signal is sampled on the rising edge of the input clock (CK). DO[0:11] OUTPUT DATA. Active high The resampled data are output as a 12 bit words on these pins. The bits are clocked out on the rising edge of the output clock (OCK). DVAL DATA VALID. Programmable active high or low level The data valid strobe. This strobe is used to identify the valid output samples when the chip is operated in the synchronous I/O mode (common I/O clock mode). This strobe is clocked out of the chip on the rising edge of the clock (CK). This strobe is active for the clock cycle just before DO changes. The high/low polarity of the strobe is programmable. See Section 2.5 for details. SO SYNC OUT. Active low This signal is either a delayed version of the input sync SI, the sync counter’s terminal count (TC), or a one-shot strobe. The SO signal is clocked out of the chip on the rising edge of the output clock (OCK). M/S MASTER/SLAVE CONTROL. High for master, low for slave This pin determines if the chip is the master or slave in a multi-chip synchronization mode. This pin should be pulled high for the master chip and grounded for the slave chips. GRAYCHIP,INC. - 14 - JULY 22, 1996 This document contains information which may be changed at any time without notice GC3011 DIGITAL RESAMPLER DC[0:11] DELAY CONTROL. Active high The 12 bit delay control word is used in the master/slave mode to lock the resampling ratio of multiple slave chips to a single master chip. The master chip broadcasts its delay control word on these pins. The slave chips accept the delay control word on these pins. The direction of the pins is determined by the M/S pin. The DC word is clocked out of and into the chips on the rising edge of the input clock (CK). CV CONTROL VALID. Active high The control valid strobe is broadcast by the master chip in the master/slave synchronization mode. The slave chips accept this signal to identify when the delay controls are valid. The direction of this pin is determined by the M/S pin.The CV strobe is clocked out of and into the chips on the rising edge of the input clock (CK). FOZ,FIZ FIFO READ ZERO, FIFO WRITE ZERO. Active high These controls are broadcast by the master chip in the master/slave synchronization mode. The slave chips use these signals to clear the FIFO input (FIZ) and FIFO output (FOZ) counters. The FIZ signal is clocked in and out of the chips on the rising edge of the input clock (CK). The FOZ signal is clocked in and out of the chips on the rising edge of the output clock (OCK). The direction of these pins are determined by the M/S pin. FRST FIFO RESET. Active high This signal resets the FIFO to the half full state. This signal is clocked into the chip on the rising edge of the input clock (CK) and must be active for at least one input clock cycle. HF HALF FULL. Active high The FIFO half full flag. This signal is high when the FIFO is at least half full, and zero otherwise. This signal is clocked out on the rising edge of the input clock (CK) FE FIFO ERROR. Active high The FIFO full or empty flag. This signal is high when the FIFO is either full or empty. If the FIFO is full, it will remain full until the output clock speeds up. If the FIFO is empty, it will remain empty until the output clock slows down. The output data will be unknown while this flag is high. The FRST pin can be used to force the FIFO to the half full state when a FIFO error occurs by connecting FE to FRST. This signal is clocked out on the rising edge of the input clock (CK). CKOUT CLOCK OUTPUT. Active high The resampled clock output. The chip generates a 50% (nominal) duty cycle clock at the resampled data rate and outputs it on this pin. CK2X DOUBLE RATE CLOCK OUTPUT. Active high This clock is output at twice the CKOUT clock rate, but not exceeding the highest clock frequency rating of the chip. This clock is useful when two chips are used in parallel to increase the data output rate. GRAYCHIP,INC. - 15 - JULY 22, 1996 This document contains information which may be changed at any time without notice GC3011 DIGITAL RESAMPLER C[0:7] CONTROL DATA I/O BUS. Active high This is the 8 bit control data I/O bus. Control register data is loaded into the chip or read from the chip through these pins. The chip will only drive these pins when CS is low and R/W is high. A[0:3] CONTROL ADDRESS BUS. Active high These pins are used to address the 16 control registers within the chip. Each of the 16 control registers within the chip are assigned a unique address. A control register can be written to or read from by setting A[0:3] to the register’s address. R/W READ/WRITE CONTROL. High for read, low for write This pin determines if the control bus cycle is a read or write operation. The pin is high for a read and is low for a write. CS CONTROL STROBE. Active low This control strobe enables the read or write operation. The contents of the register selected by A[0:3] will be output on C[0:7] when R/W is high and CS is low. If R/W is low when CS goes low, then the selected register will be loaded with the contents of C[0:7]. AVCC, AGND ANALOG POWER AND GROUND, power pins The analog power and ground pins used by the output clock generator. See Section 2.8.3. CVIN, CVOUT PLL CONTROL VOLTAGE PINS, analog control voltage The control voltage for the phase lock loop. Discrete components connected to these pins as shown in Section 2.8.3 form the loop filter for the PLL. GRAYCHIP,INC. - 16 - JULY 22, 1996 This document contains information which may be changed at any time without notice GC3011 DIGITAL RESAMPLER 4.0 CONTROL REGISTERS The chip is configured and controlled through the use of 16 eight bit control registers. These registers are accessed for reading or writing using the control bus pins (CS, R/W, A[0:3], and C[0:7]) described in the previous section. The register names and their addresses are: ADDRESS NAME ADDRESS NAME 0 RATIO byte 0 8 Sync Mode 1 RATIO byte 1 9 Counter Mode 2 RATIO byte 2 10 Output Mode 3 RATIO byte 3 11 Clock Mode 0 4 OFFSET byte 0 12 Clock Mode 1 5 OFFSET byte 1 13 Status Control 6 A Reg 14 Status 0 7 B Reg 15 Status 1 The following sections describe each of these registers. The type of each register bit is either R or R/W indicating whether the bit is read only or read/write. All bits are active high. GRAYCHIP,INC. - 17 - JULY 22, 1996 This document contains information which may be changed at any time without notice GC3011 DIGITAL RESAMPLER 4.1 RATIO WORD REGISTERS Registers 0, 1, 2, and 3 contain the 32 bit resampling ratio word. Bit 0 is the LSB, bit 31 is the MSB. ADDRESS 0: RATIO BYTE 0 BIT TYPE NAME DESCRIPTION 0-7 R/W RATIO[0:7] Byte 0 (least significant) of the ratio ADDRESS 1: RATIO BYTE 1 BIT TYPE NAME DESCRIPTION 0-7 R/W RATIO[8:15] Byte 1 of the ratio ADDRESS 2: RATIO BYTE 2 BIT TYPE NAME DESCRIPTION 0-7 R/W RATIO[16:23] Byte 2 of the ratio ADDRESS 3: RATIO BYTE 3 BIT TYPE NAME DESCRIPTION 0-7 R/W RATIO[24:31] Most significant byte of the ratio If the desired output sampling rate is FOUT, and the input sampling rate is FIN, then the resampling ratio should be set to: RATIO = FIN/FOUT Where RATIO is a unsigned fractional value ranging from 1 to 4 and formatted as follows: BYTE 3 BYTE 2 BYTE 1 BYTE 0 MSB LSB 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 INTEGER 8 7 6 5 4 3 2 1 0 FRACTION BINARY POINT Bits 30 and 31 are the integer part of RATIO and must equal 1, 2, or 3. An integer portion of 0 will not work. The fractional part can take on any value. After loading the resampling ratio value the user can choose, using the LOAD_RATIO control bits in the Sync Mode register (See Section 4.4), to have it take effect immediately, or when a sync event occurs. GRAYCHIP,INC. - 18 - JULY 22, 1996 This document contains information which may be changed at any time without notice GC3011 DIGITAL RESAMPLER 4.2 OFFSET WORD REGISTERS Registers 4, and 5 contain the 14 bit delay offset word. Bit 0 is the LSB, bit 13 is the MSB. ADDRESS 4: OFFSET BYTE 0 BIT TYPE NAME DESCRIPTION 0-7 R/W OFFSET[0:7] Byte 0 (least significant) of the offset ADDRESS 5: OFFSET BYTE 1 BIT TYPE NAME DESCRIPTION 0-5 R/W OFFSET[8:13] Most significant 6 bits of the offset 6,7 R/W LOAD_OFFSET The sync mode for loading the offset into the offset circuit. See Table 1 in Section 4.4 for details. If the desired delay offset is D, and the input sampling rate is FIN, then the offset should be set to: OFFSET = D*FIN Where OFFSET is a unsigned fractional value ranging from 0 to 4 and formatted as follows: MSB 13 12 11 10 9 INTEGER LSB 8 7 6 5 4 3 2 1 0 FRACTION BINARY POINT Bits 12 and 13 are the integer part of OFFSET and can equal 0, 1, 2, or 3. The fractional part can take on any value. After loading the offset delay value the user can choose, using the LOAD_OFFSET control bits, to have it take effect immediately, or when a sync event occurs. GRAYCHIP,INC. - 19 - JULY 22, 1996 This document contains information which may be changed at any time without notice GC3011 DIGITAL RESAMPLER 4.3 A AND B RATE-LOCK-LOOP (RLL) COEFFICIENT REGISTERS Registers 6, and 7 contain the 5 bit A and B coefficients used in the RLL circuit. ADDRESS 6: A REGISTER BIT TYPE NAME DESCRIPTION 0-4 R/W A[0:4] The A coefficient 5-7 R/W unused ADDRESS 7: B REGISTER BIT TYPE NAME DESCRIPTION 0-4 R/W B[0:5] The B coefficient 5 R/W ERR_POL Invert the polarity of the EIN signal. Normally a high level on EIN will increase the resampling ratio (which decreases the output rate). With ERR_POL high a high level on EIN will decrease the resampling ratio (which increases the output rate). 6,7 R/W LOAD_AB The sync mode for loading A and B into the RLL circuit. See Table 1 in Section 4.4 for details. The A and B coefficients range from 0 to 31. The FIFO error in the RLL is multiplied by 2-A and 2-B when A and B are non-zero. If A or B are zero, then the error for that path (See Figure 2) is cleared. After loading the A and B coefficients, the user can choose, using the LOAD_AB control bits, to have them take effect immediately, or when a sync event occurs. GRAYCHIP,INC. - 20 - JULY 22, 1996 This document contains information which may be changed at any time without notice GC3011 DIGITAL RESAMPLER 4.4 SYNC MODE REGISTER The Sync mode control register determines how the circuits within the chip are synchronized. Each circuit which requires synchronization can be configured to be synchronized to the sync input (SI), or to the terminal count of the sync counter (TC). The sync to each circuit can also be set to be always on or always off. Each circuit is given a two bit sync mode control which is defined as: Table 2: SYNC MODES MODE SYNC DESCRIPTION 0 “0” (never asserted) 1 SI 2 TC 3 “1” (always) NOTE: the internal syncs are active high. The SI input has been inverted to be the active high sync SI. ADDRESS 8: SYNC MODE BIT TYPE NAME DESCRIPTION 0,1 (LSBs) R/W LOAD_RATIO The resampling ratio load selection 2,3 R/W RATE_ACC The rate accumulator sync selection. The rate accumulator in the RLL is initialized when this sync occurs. 4,5 R/W DELAY_ACC The delay accumulator sync selection. The delay accumulator is initialized when this sync occurs. 6,7 R/W OUTPUT_SYNC The selected sync is inverted and output on the SO pin. Mode 0 in Table 1 is replaced by the one-shot sync for the output sync selection. GRAYCHIP,INC. - 21 - JULY 22, 1996 This document contains information which may be changed at any time without notice GC3011 DIGITAL RESAMPLER 4.5 COUNTER MODE REGISTER This register controls the sync counter and the diagnostic input mode. ADDRESS 9: Counter Mode Register BIT TYPE NAME DESCRIPTION 0-3 R/W COUNT[0:3] The counter length mode. The counter period is set using COUNT according to the following table: 4,5 R/W COUNT_SYNC COUNT 0 1 3 PERIOD 24 28 212 7 216 15 220 The counter is synchronized as follows: COUNT_SYNC MODE 0 never 1 SI 2 OS (one-shot) 3 always 6 R/W DIAG 7 (MSB) R/W Unused. GRAYCHIP,INC. Use the 12 LSBs of the counter as input data. - 22 - JULY 22, 1996 This document contains information which may be changed at any time without notice GC3011 DIGITAL RESAMPLER 4.6 OUTPUT MODE REGISTER These register sets various output mode controls. ADDRESS 10: Output Mode Register BIT TYPE NAME DESCRIPTION 0-1 R/W FIFO_RESET The FIFO is reset to half full according to Table 1 in Section 4.4. 2 R/W BYPASS Turns off the FIFO so that the data and the data valid flag bypass the FIFO and are output directly from the chip. The OCK pin must be tied to the CK pin in this mode. 3 R/W Unused 4 R/W DVAL_EARLY Normally the DVAL is active for the clock cycle just before the DO output changes. When this bit is set the DVAL strobe comes out one clock earlier so that it can be used as a clock enable to GRAYCHIP devices which need the clock enable to be active one clock earlier. 5 R/W DVAL_POL The DVAL strobe is normally active high. DVAL is active low when DVAL_POL is high. 6 R/W FTEST Used to turn off FIFO multi-chip synch signals during diagnostics. 7 R/W PHASE_ONLY The FIFO driven phase detector is turned off when this bit is set and the PLL is driven by the phase detector only. Normally low. GRAYCHIP,INC. - 23 - JULY 22, 1996 This document contains information which may be changed at any time without notice GC3011 DIGITAL RESAMPLER 4.7 CLOCK MODE REGISTERS The clock mode registers control the phase-lock-loop (PLL) and voltage controlled oscillator (VCO) in the output clock generator. NOTE: This register presets to 60 (HEX) upon power up. ADDRESS 11: Clock Mode register 0 BIT TYPE NAME DESCRIPTION 0-3 R/W RING_LENGTH This four bit value, if the FORCE_LENGTH bit is set, sets the length of the inverter chain used in the VCO. The longer the chain, the slower the VCO frequency. 4-7 R/W RING_DIVIDE This four bit value, if the FORCE_DIVIDE bit is set, sets the power-of-two divide of the VCO output. The larger the divide, the slower the clock output. ADDRESS 12: Clock Mode register 1 BIT TYPE 0 R/W EXTENDED_RANGE This bit puts the VCO in the extended PLL range mode. This doubles the pull range of the VCO at the expense of some additional clock jitter. 1 R/W FORCE_LENGTH This bit forces the length of the VCO inverter chain to RING_LENGTH. 2 R/W FORCE_DIVIDE This bit forces the divide of the VCO output to RING_DIVIDE. 3 R/W VCO_TEST This bit puts the ring oscillator in a test mode by breaking the ring of inverters and using the OCK clock input as the first stage of the oscillator. 4 R/W DIVIDE_TEST This bit shortens the divider from 16 stages to 8 stages for test purposes. 5 R/W PLL_RESET This bit forces the PLL to be in the reset state ready for a new acquisition cycle. In the reset state the VCO control voltage is forced to its middle setting, the ring divider (FORCE_DIVIDE must be off) is forced to maximum, and the ring length (FORCE_LENGTH must be off) is set to 8. The PLL will adapt to the resampler’s output data rate when PLL_RESET is cleared and VCO_ENABLE is set. 6 R/W VCO_ENABLE This bit turns on the VCO. The output clock is cleared when this bit is low. 7 R/W CK2X_ENABLE Turns on the 2X clock output. GRAYCHIP,INC. NAME DESCRIPTION - 24 - JULY 22, 1996 This document contains information which may be changed at any time without notice GC3011 DIGITAL RESAMPLER 4.8 STATUS CONTROL REGISTER This register contains miscellaneous control and status information. ADDRESS 13: Status Control Register BIT TYPE NAME DESCRIPTION 0,1 R/W STATUS_SELECT Sets the mode of the STATUS registers as follows: STATUS_SELECT MODE 0 Read ratio 1 Read FIFO status 2 Read PLL status 3 Read checksum 2 R/W RATIO_HOLD The ratio register tracks the value of the resampler ratio when this bit is low and holds the last value when this bit is high. 3 R/W MULTI_MODE This control bit turns synchronization logic. 4 R/W EXT_ERR_MODE Use the external error signals EIN and EVAL instead of the FIFO error to update the rate-lock-loop. 5 R/W ONE_SHOT A one-shot strobe is generated each time this bit is set high. The bit must be cleared before another one-shot strobe can be generated. 6,7 R/W POWER_DOWN This two bit field controls the power down and keep alive circuit as follows: POWER_DOWN MODE 0 Clock loss detect mode 1 Power down mode 2 Disabled 3 Test The power_down bits default to 0 (clock loss detect mode) upon power up. GRAYCHIP,INC. - 25 - on the multi-chip JULY 22, 1996 This document contains information which may be changed at any time without notice GC3011 DIGITAL RESAMPLER 4.9 STATUS REGISTERS These registers allow the user to read the status information selected by STATUS_SELECT. 4.9.1 READ RATIO If STATUS_SELECT is 0 the current resampling ratio is read (see the RATIO_HOLD bit in Section 4.8 and the diagram in Figure 2.) ADDRESS 14: Status Register 0, STATUS_SELECT=0 BIT TYPE NAME DESCRIPTION 0-7 R RATIO[0:7] Lower byte of the ratio ADDRESS 15: Status Register 1, STATUS_SELECT=0 BIT TYPE NAME DESCRIPTION 0-7 R RATIO[8:15] Upper byte of the ratio 4.9.2 READ FIFO STATUS If STATUS_SELECT is 1 the FIFO status is read from address 14. Address 15 is unused. ADDRESS 14: Status Register 0, STATUS_SELECT=1 BIT TYPE NAME DESCRIPTION 0-3 R DEPTH[0:3] The FIFO depth. See Section 2.7.1 for the gray scale encoding of these bits. 4 R EMPTY The FIFO is empty when this bit is high 5 R HALF_FULL The FIFO is more than half full when this bit is high 6 R FULL The FIFO is full when this bit is high 7 R/Clear FIFO_ERROR This bit is set and held when the FIFO full or empty condition is detected. The user clears the bit by writing anything to address 14 when STATUS_SELECT= 1. GRAYCHIP,INC. - 26 - JULY 22, 1996 This document contains information which may be changed at any time without notice GC3011 DIGITAL RESAMPLER 4.9.3 READ PLL STATUS If STATUS_SELECT is 2 the PLL status is read from addresses 14 and 15. ADDRESS 14: Status Register 0, STATUS_SELECT=2 BIT TYPE NAME DESCRIPTION 0-3 R LENGTH[0:3] The current VCO length setting. 4-7 R DEPTH[0:3] The current VCO depth setting. ADDRESS 15: Status Register 1, STATUS_SELECT=2 BIT TYPE NAME DESCRIPTION 0-3 R STATE[0:3] The current PLL acquisition state. Zero is reset and 15 is acquired. 4 R BUSY This bit is high when acquisition is in progress or has not started. This bit is forced low if the FORCE_LENGTH and FORCE_DIVIDE bits are both high. 5 R LOCK Indicates that the PLL is in a lock state. 6,7 R LOCK_STATE[0:1] Indicates the lock state. During acquisition the state is zero. After acquisition 0 means the PLL is in lock. One means that the FIFO is too full and the VCO control voltage needs to be increased. Two means that the FIFO is too empty and the VCO control voltage needs to be decreased (slows the VCO). 4.9.4 READ CHECKSUM If STATUS_SELECT is 3 the checksum is read from addresses 14 and the keepalive clock status is read from 15. Address 15 is only used for test purposes. ADDRESS 14: Status Register 0, STATUS_SELECT=3 BIT TYPE NAME DESCRIPTION 0-7 R CHECKSUM[0:7] The checksum (See Section 2.10). ADDRESS 15: Status Register 1, STATUS_SELECT=3 BIT TYPE NAME DESCRIPTION 0 R KACK_IN Input keepalive clock. 1 R KA_IN Input clock is in the keepalive mode. 2 R KACK_OUT Output keepalive clock 3 R KA_OUT Output clock is in the keepalive mode. 4-7 R unused GRAYCHIP,INC. - 27 - JULY 22, 1996 This document contains information which may be changed at any time without notice GC3011 DIGITAL RESAMPLER 5.0 SPECIFICATIONS 5.1 ABSOLUTE MAXIMUM RATINGS Referenced to GND: PARAMETER MIN VCC DC Supply Voltage -0.3 7 V VIN Input voltage (undershoot and overshoot) -0.7 VCC+0.7 V TSTG Storage Temperature -65 150 °C FCK Clock Rate1 5K 5.2 TYP MAX UNITS Hz RECOMMENDED OPERATING CONDITIONS PARAMETER MIN TYP 5.0 VCC DC Supply Voltage 3.0 TC Temperature case -25 5.3 MAX UNITS 6.0 V 85 °C DC CHARACTERISTICS All parameters are at VCC=5V and temperature is 0 to 60 °C ambient unless noted PARAMETER VIL Voltage input low VIH Voltage input high IIN Input current (VIN=0V) VOL Voltage output low (IOL = 4mA) VOH Voltage output high (IOH = -4ma) MIN TYP MAX UNITS 0.8 V VCC=5V 2.0 V VCC=3.3V 1.5 V µA +/-50 0.5 V VCC=5V 2.5 5 V VCC=3.3V 1.5 3.3 V CIN Data input capacitance (All inputs except CK and C[0:7]) 4 pF CCK Clock input capacitance (CK input) 8 pF CCON Control data capacitance (C[0:7] I/O pins) 6 pF 1. The keep-alive circuit will kick in at rates below this. GRAYCHIP,INC. - 28 - JULY 22, 1996 This document contains information which may be changed at any time without notice GC3011 DIGITAL RESAMPLER 5.4 AC CHARACTERISTICS Commercial temperature range (-25 to 85°C), VCC +/- 5%, unless noted. PARAMETER MIN TYP MAX UNITS FCK Clock frequency1 VCC= 5v 3.3v 0.1 0.1 tCKL Clock low period (Below VIL) VCC= 5v 3.3v 5 8 ns tCKH Clock high period (Above VIH) VCC= 5v 3.3v 5 8 ns tSU Data setup before CK or OCK goes high VCC= 5v 3.3v 2 4 ns tHD Data hold time after CK or OCK goes high 0 ns tDLY Data output delay from CK2 VCC= tCSU tCHD 80 45 5v 3.3v 2 2 Control setup before CS goes low (A, R/W during read, and A, R/W, C during write) 5 ns Control hold after CS goes high (A, R/W during read, and A, R/W, C during write) 5 ns 30 ns tCSPW Control strobe pulse width (Write operation) tCDLY Control output delay to C after CS goes low3 (Read operation) VCC = 5v 40 3.3v tCZ Control tristate delay after CS goes high IPD Power down supply current (VIN=0 or VCC, See Section 4.8) ICC Supply current (FCK=50 MHz, VCC=5.0V) 9 13 MHz ns ns 60 ns 10 ns 4 mA 210 mA VCC F CK ICC (MAX) = ------------ ----------- 210 mA 5 50 M 1. The chip may not operate properly at clock frequencies below MIN and above MAX, 2. Capacitive output load is 20 pf. Delays are measured from the rising edge of the clock to the output level rising above VIH or falling below VIL. 3. Capacitive output load is 80 pf. GRAYCHIP,INC. - 29 - JULY 22, 1996 This document contains information which may be changed at any time without notice GC3011 DIGITAL RESAMPLER 6.0 APPLICATION NOTES 6.1 POWER AND GROUND CONNECTIONS The GC3011 chip is a very high performance chip which requires solid power and ground connections to avoid noise on the VCC and GND pins. If possible the GC3011 chip should be mounted on a circuit board with dedicated power and ground planes and with at least two decoupling capacitors (0.01 and 0.1 µf) adjacent to each GC3011 chip. If dedicated power and ground planes are not possible, then the user should place decoupling capacitors adjacent to each VCC and GND pair. IMPORTANT The GC3011 chip may not operate properly if these power and ground guidelines are violated. 6.2 STATIC SENSITIVE DEVICE The GC3011 chip is fabricated in a high performance CMOS process which is sensitive to the high voltage transients caused by static electricity. These parts can be permanently damaged by static electricity and should only be handled in static free environments. 6.3 80 MHZ OPERATION Care must be taken in generating the clock when operating the GC3011 chip at its full 80 MHz clock rate. The user must insure that the clock is above 2 volts for at least 5 nanoseconds and is below 1 volt for at least 5 nanoseconds. 6.4 REDUCED VOLTAGE OPERATION The power consumed by the GC3011 chip can be greatly reduced by operating the chip at the lowest VCC voltage which will meet the application’s timing requirements. GRAYCHIP,INC. - 30 - JULY 22, 1996 This document contains information which may be changed at any time without notice GC3011 DIGITAL RESAMPLER 6.5 SYNCHRONIZING MULTIPLE GC3011 CHIPS A system containing two or more GC3011 chips will need to be synchronized so that their resampling delays and output FIFOs are locked. This is done using the multi-chip synchronization signals DC[0:11], CV, FOZ, FIZ and M/S as described in Section 2.6. A block diagram showing how to configure the chips is shown in Figure 6. . IIN SYNC IN DI DO IOUT SI GC3011 “MASTER” INPUT CLOCK CK OCK M/S QIN DC DV FOZ FIZ DC DV FOZ FIZ DI SI OUTPUT CLOCK CKOUT CLOCK DRIVER CHIP DO QOUT GC3011 “SLAVE” CK OCK CKOUT M/S Figure 6. SYNCHRONIZING MULTIPLE GC3011 CHIPS Figure 6 shows how one would configure the chips to resample complex data. The sync input is not necessary unless there are system wide diagnostics which require it. GRAYCHIP,INC. - 31 - JULY 22, 1996 This document contains information which may be changed at any time without notice GC3011 DIGITAL RESAMPLER This page left intentionally blank GRAYCHIP,INC. - 32 - JULY 22, 1996 This document contains information which may be changed at any time without notice (415) 323-2955 FAX (415) 323-0206 2185 Park Blvd., Palo Alto, CA. 94306 GRAYCHIP DSP CHIPS AND SYSTEMS GC3011 DIGITAL RESAMPLER CHIP DATASHEET July 22, 1996 This datasheet contains preliminary information which may be changed at any time without notice. IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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