ETC HYM71V8M635AT6

8Mx64 bits
PC133 SDRAM SO DIMM
based on 8Mx16 SDRAM with LVTTL, 4 banks & 4K Refresh
HYM71V8M635A(L)T6 Series
DESCRIPTION
The Hynix HYM71V8M635AT6 Series are 8Mx64bits Synchronous DRAM Modules. The modules are composed of four 8Mx16bits
CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package on a 144pin glass-epoxy
printed circuit board. Two 0.33uF and one 0.1uF decoupling capacitors per each SDRAM are mounted on the PCB.
The Hynix HYM71V8M635AT6 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 64Mbytes memory. The Hynix HYM71V8M635AT6 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and
outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth.
FEATURES
•
PC133/PC100MHz support
•
SDRAM internal banks : four banks
•
144pin SDRAM SO DIMM
•
Module bank : one physical bank
•
Serial Presence Detect with EEPROM
•
Auto refresh and self refresh
•
1.00” (25.40mm) Height PCB with double sided components
•
4096 refresh cycles / 64ms
•
Programmable Burst Length and Burst Type
•
Single 3.3±0.3V power supply
•
All device pins are compatible with LVTTL interface
•
Data mask function by DQM
- 1, 2, 4 or 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
•
Programmable CAS Latency ; 2, 3 Clocks
ORDERING INFORMATION
Part No.
Clock
Frequency
Internal
Bank
Ref.
HYM71V8M635AT6-K
HYM71V8M635AT6-H
HYM71V8M635ALT6-K
HYM71V8M635ALT6-H
Power
SDRAM
Package
Plating
TSOP-II
Gold
Normal
133MHz
4 Banks
4K
Low Power
This document is a general product description and is subject to change without notice. Hynix semiconductor Inc. does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 1.4/Dec. 01
2
PC133 SDRAM SO DIMM
HYM71V8M635A(L)T6 Series
PIN DESCRIPTION
PIN
PIN NAME
DESCRIPTION
CK0, CK1
Clock Inputs
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
CKE0
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
/S0
Chip Select
Enables or disables all inputs except CK, CKE and DQM
BA0, BA1
SDRAM Bank Address
Selects bank to be activated during /RAS activity
Selects bank to be read/written during /CAS activity
A0 ~ A11
Address
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8
Auto-precharge flag : A10
/RAS, /CAS, /WE
Row Address Strobe, Column
Address Strobe, Write Enable
/RAS, /CAS and /WE define the operation
Refer function truth table for details
DQM0~DQM7
Data Input/Output Mask
Controls output buffers in read mode and masks input data in write mode
DQ0 ~ DQ63
Data Input/Output
Multiplexed data input / output pin
VCC
Power Supply (3.3V)
Power supply for internal circuits and input buffers
VSS
Ground
Ground
SCL
SPD Clock Input
Serial Presence Detect Clock input
SDA
SPD Data Input/Output
Serial Presence Detect Data input/output
SA0~2
SPD Address Input
Serial Presence Detect Address Input
WP
Write Protect for SPD
Write Protect for Serial Presence Detect on DIMM
NC
No Connection
No connection
Rev. 1.4/Dec. 01
3
PC133 SDRAM SO DIMM
HYM71V8M635A(L)T6 Series
PIN ASSIGNMENTS
FRONT SIDE
PIN NO.
BACK SIDE
NAME
PIN NO.
NAME
FRONT SIDE
PIN NO.
NAME
BACK SIDE
PIN NO.
NAME
1
VSS
2
VSS
71
NC
72
NC
3
DQ0
4
DQ32
73
NC
74
*CK1
5
DQ1
6
DQ33
75
VSS
76
VSS
7
DQ2
8
DQ34
77
NC
78
NC
9
DQ3
10
DQ35
79
NC
80
NC
11
VCC
12
VCC
81
VCC
82
VCC
13
DQ4
14
DQ36
83
DQ16
84
DQ48
15
DQ5
16
DQ37
85
DQ17
86
DQ49
17
DQ6
18
DQ38
87
DQ18
88
DQ50
19
DQ7
20
DQ39
89
DQ19
90
DQ51
21
VSS
22
VSS
91
VSS
92
VSS
23
DQM0
24
DQM4
93
DQ20
94
DQ52
25
DQM1
26
DQM5
95
DQ21
96
DQ53
27
VCC
28
VCC
97
DQ22
98
DQ54
29
A0
30
A3
99
DQ23
100
DQ55
31
A1
32
A4
101
VCC
102
VCC
33
A2
34
A5
103
A6
104
A7
35
VSS
36
VSS
105
A8
106
BA0
37
DQ8
38
DQ40
107
VSS
108
VSS
39
DQ9
40
DQ41
109
A9
110
BA1
41
DQ10
42
DQ42
111
A10/AP
112
A11
43
DQ11
44
DQ43
113
VCC
114
VCC
45
VCC
46
VCC
115
DQM2
116
DQM6
47
DQ12
48
DQ44
117
DQM3
118
DQM7
49
DQ13
50
DQ45
119
VSS
120
VSS
51
DQ14
52
DQ46
121
DQ24
122
DQ56
53
DQ15
54
DQ47
123
DQ25
124
DQ57
55
VSS
56
VSS
125
DQ26
126
DQ58
57
NC
58
NC
127
DQ27
128
DQ59
59
NC
60
NC
129
VCC
130
VCC
131
DQ28
132
DQ60
Voltage Key
61
133
DQ29
134
DQ61
CKE0
135
DQ30
136
DQ62
64
VCC
137
DQ31
138
DQ63
66
/CAS
139
VSS
140
VSS
/WE
68
NC
141
SDA
142
SCL
/S0
70
NC
143
VCC
144
VCC
CK0
62
63
VCC
65
/RAS
67
69
Note : * CK1 are connected with termination R/C (Refer to the Block Diagram)
Rev. 1.4/Dec. 01
4
PC133 SDRAM SO DIMM
HYM71V8M635A(L)T6 Series
BLOCK DIAGRAM
S0
DQMB0
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQML
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQMB1
DQ 32
DQ 33
DQ 34
DQ 35
DQ 36
DQ 37
DQ 38
DQ 39
DQMU
DQMB2
DQ 16
DQ17
DQ 18
DQ 19
DQ 20
DQ 21
DQ 22
DQ 23
DQML
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQMB3
DQ 48
DQ 49
DQ 50
DQ 51
DQ 52
DQ53
DQ 54
DQ 55
DQMU
CS
U0
DQ 8
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
CS
U1
DQ 8
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
A0 ~ A11, BA0,1
RAS
CAS
WE
CKE0
U0 - U3
U0 - U3
U0 - U3
U0 - U3
U0 - U3
DQMB4
DQ 8
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
DQML
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQMB5
DQ 40
DQ 41
DQ 42
DQ 43
DQ 44
DQ 45
DQ 46
DQ 47
DQMU
DQMB6
DQ 24
DQ25
DQ26
DQ 27
DQ 28
DQ 29
DQ 30
DQ 31
DQML
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQMB7
DQ 56
DQ 57
DQ 58
DQ 59
DQ 60
DQ 61
DQ 62
DQ 63
DQMU
VSS
Rev. 1.4/Dec. 01
Capacitor
two 0.33uF and one 0.1uF per SDRAM
CS
U3
DQ 8
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
10ohm
10pF
SCL
VCC
U2
DQ 8
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
4 SDRAMS
CK0
CK1
CS
U0 ~ U3
U0 ~ U3
U4
SERIAL PD
A0
A1
SDA
A2
VSS
5
PC133 SDRAM SO DIMM
HYM71V8M635A(L)T6 Series
SERIAL PRESENCE DETECT
BYTE
NUMBER
FUNCTION
DESCRIPTION
FUNCTION
VALUE
-H
-K
-H
-K
BYTE0
# of Bytes Written into Serial Memory at Module
Manufacturer
128 Bytes
80h
BYTE1
Total # of Bytes of SPD Memory Device
256 Bytes
08h
BYTE2
Fundamental Memory Type
BYTE3
# of Row Addresses on This Assembly
BYTE4
# of Column Addresses on This Assembly
9
09h
BYTE5
# of Module Banks on This Assembly
1 Bank
01h
BYTE6
Data Width of This Assembly
64 Bits
40h
BYTE7
Data Width of This Assembly (Continued)
-
00h
BYTE8
Voltage Interface Standard of This Assembly
BYTE9
SDRAM Cycle Time @/CAS Latency=3
7.5ns
7.5ns
75h
75h
BYTE10
Access Time from Clock @/CAS Latency=3
5.4ns
5.4ns
54h
54h
BYTE11
DIMM Configuration Type
BYTE12
Refresh Rate/Type
BYTE13
Primary SDRAM Width
BYTE14
Error Checking SDRAM Width
BYTE15
Minimum Clock Delay Back to Back Random Column
Address
BYTE16
Burst Lenth Supported
BYTE17
# of Banks on Each SDRAM Device
SDRAM
04h
12
0Ch
LVTTL
None
00h
15.625us
/ Self Refresh Supported
80h
x16
10h
None
00h
tCCD = 1 CLK
01h
1,2,4,8,Full Page
8Fh
4 Banks
04h
/CAS Latency=2,3
06h
SDRAM Device Attributes, /CAS Lataency
BYTE19
SDRAM Device Attributes, /CS Lataency
/CS Latency=0
01h
BYTE20
SDRAM Device Attributes, /WE Lataency
/WE Latency=0
01h
BYTE21
SDRAM Module Attributes
Neither Buffered nor Registered
00h
+/- 10% voltage tolerence, Burst Read
Single Bit Write, Precharge All, Auto
Precharge, Early RAS Precharge
0Eh
SDRAM Device Attributes, General
1
01h
BYTE18
BYTE22
2
BYTE23
SDRAM Cycle Time @/CAS Latency=2
7.5ns
10ns
75h
A0h
BYTE24
Access Time from Clock @/CAS Latency=2
5.4ns
6ns
54h
60h
BYTE25
SDRAM Cycle Time @/CAS Latency=1
-
-
00h
00h
BYTE26
Access Time from Clock @/CAS Latency=1
BYTE27
Minimum Row Precharge Time (tRP)
BYTE28
Minimum Row Active to Row Active Delay (tRRD)
15ns
BYTE29
Minimum /RAS to /CAS Delay (tRCD)
15ns
BYTE30
Minimum /RAS Pulse Width (tRAS)
45ns
BYTE31
Module Bank Density
BYTE32
Command and Address Signal Input Setup Time
BYTE33
Command and Address Signal Input Hold Time
BYTE34
Data Signal Input Setup Time
1.5ns
1.5ns
15h
15h
BYTE35
Data Signal Input Hold Time
0.8ns
0.8ns
08h
08h
BYTE36
~61
Superset Information (may be used in future)
BYTE62
SPD Revision
BYTE63
Checksum for Byte 0~62
BYTE64
Manufacturer JEDEC ID Code
BYTE65
~71
....Manufacturer JEDEC ID Code
BYTE72
Manufacturing Location
Rev. 1.4/Dec. 01
NOTE
-
-
00h
00h
15ns
20ns
0Fh
14h
15ns
0Fh
0Fh
20ns
0Fh
14h
45ns
2Dh
2Dh
1.5ns
1.5ns
15h
15h
0.8ns
0.8ns
08h
08h
64MB
10h
-
00h
Intel SPD 1.2B
-
12h
6F
3, 8
A6h
Hynix JEDED ID
ADh
Unused
FFh
HSI (Korea Area)
HSA (United States Area)
HSE (Europe Area)
HSJ (Japan Area)
HSS(Singapore)
ASIA Area
0*h
1*h
2*h
3*h
4*h
10
6
PC133 SDRAM SO DIMM
HYM71V8M635A(L)T6 Series
Continued
BYTE
NUMBER
FUNCTION
DESCRIPTION
BYTE73
Manufacturer’s Part Number (Component)
BYTE74
Manufacturer’s Part Number (128Mb based)
BYTE75
Manufacturer’s Part Number (Voltage Interface)
BYTE76
Manufacturer’s Part Number (Memory Width)
BYTE78
Manufacturer’s Part Number (Module Type)
BYTE78
Manufacturer’s Part Number (Data Width)
BYTE79
....Manufacturer’s Part Number (Data Width)
BYTE80
Manufacturer’s Part Number (Refresh, SDRAM Bank)
BYTE81
BYTE82
FUNCTION
VALUE
-H
-K
-H
-K
7 (SDRAM)
37h
NOTE
4, 5
1
31h
4, 5
V (3.3V, LVTTL)
56h
4, 5
4, 5
8
38h
M (SO DIMM)
4Dh
4, 5
6
36h
4, 5
3
33h
4, 5
5 (4K Refresh, 4Banks)
35h
4, 5
Manufacturer’s Part Number (Generation)
A
41h
4, 5
Manufacturer’s Part Number (Package Type)
T
54h
4, 5
6 (x16 based)
36h
4, 5
- (Hyphen)
2Dh
4, 5
BYTE83
Manufacturer’s Part Number (Component Configuration)
BYTE84
Manufacturer’s Part Number (Hyphent)
BYTE85
Manufacturer’s Part Number (Min. Cycle Time)
BYTE86
~90
Manufacturer’s Part Number
K
H
4Bh
48h
4, 5
Blanks
20h
4, 5
BYTE91
Revision Code (for Component)
Process Code
-
4, 6
BYTE92
....Revision Code (for PCB)
Process Code
-
4, 6
BYTE93
Manufacturing Date
Year
-
3, 6
BYTE94
....Manufacturing Date
Work Week
-
3, 6
Serial Number
-
6
None
00h
BYTE95
~98
BYTE99
~125
Assembly Serial Number
Manufacturer Specific Data (may be used in future)
BYTE126
Reserved
100MHz
64h
7, 8, 9
BYTE127
Reserved
Refer to Note7
8Fh
7, 8, 9
BYTE128
~256
Unused Storage Locations
-
00h
Note :
1. The bank address is excluded
2. 1, 2, 4, 8 for Interleave Burst Type
3. BCD adopted
4. ASCII adopted
5. Basically Hynix writes Part No. except for ‘HYM’ in Byte 73~90 to use the limited 18 bytes from byte 73 to byte 90
6. Not fixed but dependent
7. CK0 connected to DIMM, TBD junction temp, CL2(3) support, Intel defined Concurrent Auto Precharge support
8. Refer to the most recent Intel and JEDEC SPD Specification
9. These values are applied to PC100 applications only per Intel PC SDRAM specification
10. Refer to HSI Web site.
Byte 82~86 for L-Part
BYTE
NUMBER
FUNCTION
DESCRIPTION
FUNCTION
-K
VALUE
-H
-8
-P
NOTE
BYTE82
Manufacturer’s Part Number (Power)
L
4Ch
4, 5
BYTE83
Manufacturer’s Part Number (Package Type)
T
54h
4, 5
6 (x16 based)
36h
4, 5
- (Hyphen)
2Dh
4, 5
BYTE84
Manufacturer’s Part Number (Component Configuration)
BYTE85
Manufacturer’s Part Number (Hyphent)
BYTE86
Manufacturer’s Part Number (Min. Cycle Time)
Rev. 1.4/Dec. 01
K
H
48h
48h
4, 5
7
PC133 SDRAM SO DIMM
HYM71V8M635A(L)T6 Series
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Ambient Temperature
TA
0 ~ 70
°C
Storage Temperature
TSTG
-55 ~ 125
°C
Voltage on Any Pin relative to VSS
VIN, VOUT
-1.0 ~ 4.6
V
Voltage on VDD relative to VSS
VDD, VDDQ
-1.0 ~ 4.6
V
Short Circuit Output Current
IOS
50
mA
Power Dissipation
PD
4
W
Soldering Temperature ⋅ Time
TSOLDER
260 ⋅ 10
°C ⋅ Sec
Note : Operation at above absolute maximum rating can adversely affect device reliability.
DC OPERATING CONDITION (TA=0 to 70°C)
Parameter
Symbol
Min
Typ
Max
Unit
Note
Power Supply Voltage
VDD, VDDQ
3.0
3.3
3.6
V
1
Input High voltage
VIH
2.0
3.0
VDDQ + 0.3
V
1,2
Input Low voltage
VIL
-0.3
0
0.8
V
1,3
Note
Note :
1.All voltages are referenced to VSS = 0V
2.VIH(max) is acceptable 5.6V AC pulse width with <=3ns of duration.
3.VIL(min) is acceptable -2.0V AC pulse width with <=3ns of duration.
AC OPERATING TEST CONDITION (TA=0 to 70°C, VDD=3.3±0.3V, VSS=0V)
Parameter
Symbol
Value
Unit
AC Input High / Low Level Voltage
VIH / VIL
2.4/0.4
V
Vtrip
1.4
V
Input Rise / Fall Time
tR / tF
1
ns
Output Timing Measurement Reference Level Voltage
Voutref
1.4
V
CL
50
pF
Input Timing Measurement Reference Level Voltage
Output Load Capacitance for Access Time Measurement
1
Note :
1.Output load to measure access times is equivalent to two TTL gates and one capacitor (50pF). For details, refer to AC/DC output
load circuit
Rev. 1.4/Dec. 01
8
PC133 SDRAM SO DIMM
HYM71V8M635A(L)T6 Series
CAPACITANCE (TA=25°C, f=1MHz)
-K/H
Parameter
Pin
Input Capacitance
Data Input / Output Capacitance
Symbol
Unit
Min
Max
CK0
CI1
20
40
pF
CKE0
CI2
15
30
pF
/S0
CI3
15
30
pF
A0~11, BA0, BA1
CI4
20
30
pF
/RAS, /CAS, /WE
CI5
20
30
pF
DQM0~DQM7
CI6
5
15
pF
DQ0 ~ DQ63
CI/O
5
15
pF
OUTPUT LOAD CIRCUIT
Vtt=1.4V
RT=250 Ω
Output
Output
50pF
DC Output Load Circuit
Rev. 1.4/Dec. 01
50pF
AC Output Load Circuit
9
PC133 SDRAM SO DIMM
HYM71V8M635A(L)T6 Series
DC CHARACTERISTICS I (TA=0 to 70°C, VDD=3.3±0.3V)
Parameter
Symbol
Min.
Max
Unit
Note
Input Leakage Current
ILI
-4
4
uA
1
Output Leakage Current
ILO
-1
1
uA
2
Output High Voltage
VOH
2.4
-
V
IOH = -4mA
Output Low Voltage
VOL
-
0.4
V
IOL = +4mA
Note :
1.VIN = 0 to 3.6V, All other pins are not tested under VIN =0V
2.DOUT is disabled, VOUT=0 to 3.6
DC CHARACTERISTICS II
Parameter
Operating Current
Symbol
IDD1
Speed
Test Condition
Burst length=1, One bank active
tRC ≥ tRC(min), IOL=0mA
-K
-H
440
400
CKE ≤ VIL(max), tCK = 15ns
8
CKE ≤ VIL(max), tCK = ∞
8
IDD2N
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
Input signals are changed one time during
30ns. All other pins ≥ VDD-0.2V or ≤ 0.2V
80
IDD2NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
40
IDD3P
CKE ≤ VIL(max), tCK = 15ns
28
IDD3PS
CKE ≤ VIL(max), tCK = ∞
28
IDD3N
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
Input signals are changed one time during
30ns. All other pins ≥ VDD-0.2V or ≤ 0.2V
160
IDD3NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
160
Burst Mode Operating
Current
IDD4
tCK ≥ tCK(min), IOL=0mA
All banks active
Auto Refresh Current
IDD5
tRRC ≥ tRRC(min), All banks active
Self Refresh Current
IDD6
CKE ≤ 0.2V
IDD2P
Precharge Standby Current
in Power Down Mode
IDD2PS
Precharge Standby Current
in Non Power Down Mode
Active Standby Current
in Power Down Mode
Active Standby Current
in Non Power Down Mode
Unit
Note
mA
1
mA
mA
mA
mA
CL=3
480
480
CL=2
480
400
960
880
mA
1
mA
2
8
mA
3
3.2
mA
4
Note :
1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open
2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3.HYM71V8M635AT6-K/H
4.HYM71V8M635ALT6-K/H
Rev. 1.4/Dec. 01
10
PC133 SDRAM SO DIMM
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
-K
Parameter
CAS Latency = 3
-H
Symbol
Unit
Min
System Clock
Cycle Time
tCK3
Max
7.5
Min
Note
Max
7.5
1000
ns
1000
tCK2
7.5
Clock High Pulse Width
tCHW
2.5
-
2.5
-
ns
1
Clock Low Pulse Width
tCLW
2.5
-
2.5
-
ns
1
CAS Latency = 3
tAC3
-
5.4
-
5.4
ns
CAS Latency = 2
tAC2
-
5.4
-
6
ns
Data-Out Hold Time
tOH
2.7
-
2.7
-
ns
Data-Input Setup Time
tDS
1.5
-
1.5
-
ns
1
Data-Input Hold Time
tDH
0.8
-
0.8
-
ns
1
Address Setup Time
tAS
1.5
-
1.5
-
ns
1
Address Hold Time
tAH
0.8
-
0.8
-
ns
1
CKE Setup Time
tCKS
1.5
-
1.5
-
ns
1
CKE Hold Time
tCKH
0.8
-
0.8
-
ns
1
Command Setup Time
tCS
1.5
-
1.5
-
ns
1
Command Hold Time
tCH
0.8
-
0.8
-
ns
1
CLK to Data Output in Low-Z Time
tOLZ
1
-
1
-
ns
Access Time
From Clock
CLK to Data
Output in High-Z
Time
CAS Latency = 2
HYM71V8M635A(L)T6 Series
10
ns
2
CAS Latency = 3
tOHZ3
2.7
5.4
2.7
5.4
ns
CAS Latency = 2
tOHZ2
2.7
5.4
3
6
ns
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter
2.Access times to be measured with input signals of 1v/ns edge rate, from 0.8v to 2.0v
If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter
Rev. 1.4/Dec. 01
11
PC133 SDRAM SO DIMM
HYM71V8M635A(L)T6 Series
AC CHARACTERISTICS II
-K
Parameter
-H
Symbol
Unit
Min
Max
Min
Max
Operation
tRC
60
-
65
-
ns
Auto Refresh
tRRC
60
-
65
-
ns
RAS to CAS Delay
tRCD
15
-
20
-
ns
RAS Active Time
tRAS
45
100K
45
100K
ns
RAS Precharge Time
tRP
15
-
20
-
ns
RAS to RAS Bank Active Delay
tRRD
15
-
15
-
ns
CAS to CAS Delay
tCCD
1
-
1
-
CLK
Write Command to Data-In Delay
tWTL
0
-
0
-
CLK
Data-In to Precharge Command
tDPL
2
-
2
-
CLK
Data-In to Active Command
tDAL
4
-
5
-
CLK
DQM to Data-Out Hi-Z
tDQZ
2
-
2
-
CLK
DQM to Data-In Mask
tDQM
0
-
0
-
CLK
MRS to New Command
tMRD
2
-
2
-
CLK
CAS Latency = 3
tPROZ3
3
-
3
-
CLK
CAS Latency = 2
tPROZ2
2
-
2
-
CLK
Power Down Exit Time
tPDE
1
-
1
-
CLK
Self Refresh Exit Time
tSRE
1
-
1
-
CLK
Refresh Time
tREF
-
64
-
64
ms
Note
RAS Cycle Time
Precharge to Data
Output Hi-Z
1
Note :
1. A new command can be given tRRC after self refresh exit
Rev. 1.4/Dec. 01
12
PC133 SDRAM SO DIMM
HYM71V8M635A(L)T6 Series
DEVICE OPERATING OPTION TABLE
HYM71V8M635A(L)T6-K
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
133MHz(7.5ns)
2CLKs
2CLKs
6CLKs
8CLKs
2CLKs
5.4ns
2.7ns
125MHz(8ns)
3CLKs
3CLKs
6CLKs
9CLKs
3CLKs
6ns
3ns
100MHz(10ns)
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
3ns
HYM71V8M635A(L)T6-H
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
133MHz(7.5ns)
3CLKs
3CLKs
6CLKs
9CLKs
3CLKs
5.4ns
2.7ns
125MHz(8ns)
3CLKs
3CLKs
6CLKs
9CLKs
3CLKs
6ns
3ns
100MHz(10ns)
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
3ns
Rev. 1.4/Dec. 01
13
PC133 SDRAM SO DIMM
HYM71V8M635A(L)T6 Series
COMMAND TRUTH TABLE
Command
A10/
AP
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
Mode Register Set
H
X
L
L
L
L
X
OP code
No Operation
H
X
X
X
Bank Active
H
Read
Read with Autoprecharge
Write
Write with Autoprecharge
Precharge All Banks
Precharge selected Bank
Burst Stop
ADDR
H
X
X
X
L
H
H
H
X
L
L
H
H
X
H
X
L
H
L
H
X
CA
H
X
L
H
L
L
X
CA
H
X
L
L
H
L
X
X
H
X
L
H
H
L
X
L
H
L
H
V
V
H
X
L
V
X
H
V
X
Auto Refresh
H
H
L
L
L
H
X
X
Burst-Read-Single-WRITE
H
X
L
L
L
L
X
A9 Pin High
(Other Pins OP code)
Entry
H
L
L
L
L
H
X
Exit
L
H
Entry
H
L
Exit
L
H
1
Precharge
power down
Clock
Suspend
Entry
H
L
Exit
L
H
H
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
X
X
Note
V
DQM
Self Refresh
X
RA
BA
MRS
Mode
X
X
X
X
X
X
X
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2. X = Don′t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,
Opcode = Operand Code, NOP = No Operation
3. The burst read sigle write mode is entered by programming the Write burst mode bit (A9) in the mode register to a logic 1.
Rev. 1.4/Dec. 01
14
PC133 SDRAM SO DIMM
HYM71V8M635A(L)T6 Series
PACKAGE DEMENSION
Rev. 1.4/Dec. 01
15