ETC HYMA6V16733F14HGTG

HYMA6V16733F14HGTG
16Mx72 buffered Fast Page DRAM DIMM
PRELIMINARY
Description
The HYMA6V16733F14HGTG familiy is an 16Mx72 bits Dynamic RAM Module which is assembled 18 pieces of
16Mx4bit DRAMs in 32pin TSOP-II package and two 16bit driver ICs in 48pin TTSOP package mounted on a 168pin
printed circuit board with decoupling capacitors.
The HYMA6V16733F14HGTG is optimized for application to the systems which are required high density and large
capacity such as main memory of the computers and an image memory systems, and to the others which are
requested compact size.
The HYMA6V16733F14HGTG provides common data inputs and fast page mode
Features
•
Fast Page mode capability
•
8K Refresh cycle / 64ms
•
All inputs and outputs TTL compatible
•
•
/RAS only refresh, /CAS before /RAS
refresh,Hidden refresh capability
•
•
Single Power supply
168pins Dual In-Line Package
- HYMA6V16733F14HGTG : Gold plating
Low power
- active : 7200/6552mW(Max)
- standby : 105mW(CMOS level : Max)
* Fast access time & cycle time
Part No
tRAC
tCAC
tRC
tPC
HYMA6V16733F14HGTG-5
50ns
13ns
90ns
35ns
HYMA6V16733F14HGTG-6
60ns
20ns
104ns
40ns
Ordering Information
Part No.
Power Suppy
HYMA6V16733F14HGTG-5
Clock Frequency
50ns
3.3V
HYMA6V16733F14HGTG-6
Interface
Form Factor
TTL
168pin buffered DIMM
5.25x1.5 inch
60ns
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.0.1/Apr.01
HYMA6V16733F14HGTG
Pin Description
Pin
Pin Description
Pin
Pin Description
A0, B0, A1~A12
Address Inputs
/PDE
Presence Detect Enable
DQ0 ~ DQ71
Data Input / Output
Vcc
Power (+3.3V)
/RAS0, /RAS2
Row Address Strobe
Vss
Ground
/CAS0, /CAS4
Column Address Strobe
NC
No connection
/WE0, /WE2
Read / Write Enable
/OE0, /OE2
Output Enable
PD 1~8
Presence Detect
RSVD
Reserved Use
ID 0~1
ID bit
RFU
Reserved for future use
Pin Assignment
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
1
Vss
29
RSVD
57
DQ22
85
Vss
113
RSVD
141
DQ58
2
DQ0
30
/RAS0
58
DQ23
86
DQ36
114
/RAS1*
142
DQ59
3
DQ1
31
/OE0
59
Vcc
87
DQ37
115
RFU
143
Vcc
4
DQ2
32
Vss
60
DQ24
88
DQ38
116
Vss
144
DQ60
RFU
5
DQ3
33
A0
61
RFU
89
DQ39
117
A1
145
6
Vcc
34
A2
62
RFU
90
Vcc
118
A3
146
RFU
7
DQ4
35
A4
63
RFU
91
DQ40
119
A5
147
RFU
8
DQ5
36
A6
64
RFU
92
DQ41
120
A7
148
RFU
9
DQ6
37
A8
65
DQ25
93
DQ42
121
A9
149
DQ61
10
DQ7
38
A10
66
DQ26
94
DQ43
122
A11
150
DQ62
11
DQ8
39
A12
67
DQ27
95
DQ44
123
A13*
151
DQ63
12
Vss
40
Vcc
68
Vss
96
Vss
124
Vcc
152
Vss
13
DQ9
41
RFU
69
DQ28
97
DQ45
125
RFU
153
DQ64
14
DQ10
42
RFU
70
DQ29
98
DQ46
126
B0
154
DQ65
15
DQ11
43
Vss
71
DQ30
99
DQ47
127
Vss
155
DQ66
16
DQ12
44
/OE2
72
DQ31
100
DQ48
128
RFU
156
DQ67
17
DQ13
45
/RAS2
73
Vcc
101
DQ49
129
/RAS3*
157
Vcc
18
Vcc
46
/CAS4
74
DQ32
102
Vcc
130
/CAS5*
158
DQ68
19
DQ14
47
RSVD
75
DQ33
103
DQ50
131
RSVD
159
DQ69
20
DQ15
48
/WE2
76
DQ34
104
DQ51
132
/PDE
160
DQ70
21
DQ16
49
Vcc
77
DQ35
105
DQ52
133
Vcc
161
DQ71
22
DQ17
50
RSVD
78
Vss
106
DQ53
134
RSVD
162
Vss
23
Vss
51
RSVD
79
PD1
107
Vss
135
RSVD
163
PD2
24
RSVD
52
DQ18
80
PD3
108
RSVD
136
DQ54
164
PD4
25
RSVD
53
DQ19
81
PD5
109
RSVD
137
DQ55
165
PD6
26
Vcc
54
Vss
82
PD7
110
Vcc
138
Vss
166
PD8
27
/WE0
55
DQ20
83
ID0
111
RFU
139
DQ56
167
ID1
28
/CAS0
56
DQ21
84
Vcc
112
/CAS1*
140
DQ57
168
Vcc
Note : Pins marked * are not used in this module
Presence Detect Pins(Optional)
Rev.0.1/Apr.01
Pin
50ns
60ns
Pin
50ns
60ns
PD1
1
1
PD6
0
1
PD2
1
1
PD7
0
1
PD3
1
1
PD8
0
0
PD4
1
1
ID0
0
0
PD5
0
0
ID1
0
0
2
HYMA6V16733F14HGTG
Functinal Block Diagram
RAS0
RAS2
CAS0
CAS4
WE0
WE2
OE0
A1~A12
OE2
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 0
DQ 1
DQ 2
DQ 3
DQ 8
DQ 9
DQ 10
DQ 11
DQ 0
DQ 1
DQ 2
DQ 3
DQ 12
DQ 13
DQ 14
DQ 15
DQ 0
DQ 1
DQ 2
DQ 3
DQ 16
DQ 17
DQ 18
DQ 19
DQ 0
DQ 1
DQ 2
DQ 3
DQ 20
DQ 21
DQ 22
DQ 23
DQ 0
DQ 1
DQ 2
DQ 3
DQ 24
DQ 25
DQ 26
DQ 27
DQ 0
DQ 1
DQ 2
DQ 3
DQ 28
DQ 29
DQ 30
DQ 31
DQ 0
DQ 1
DQ 2
DQ 3
DQ 32
DQ 33
DQ 34
DQ 35
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQ 40
DQ 41
DQ 42
DQ 43
DQ 0
DQ 1
DQ 2
DQ 3
D2
DQ 44
DQ 45
DQ 46
DQ 47
DQ 0
DQ 1
DQ 2
DQ 3
D3
DQ 48
DQ 49
DQ 50
DQ 51
DQ 0
DQ 1
DQ 2
DQ 3
DQ 52
DQ 53
DQ 54
DQ 55
DQ 0
DQ 1
DQ 2
DQ 3
DQ 56
DQ 57
DQ 58
DQ 59
DQ 0
DQ 1
DQ 2
DQ 3
DQ 60
DQ 61
DQ 62
DQ 63
DQ 0
DQ 1
DQ 2
DQ 3
DQ 64
DQ 65
DQ 66
DQ 67
DQ 0
DQ 1
DQ 2
DQ 3
DQ 68
DQ 69
DQ 70
DQ 71
DQ 0
DQ 1
DQ 2
DQ 3
D0
D1
D4
D5
D6
D7
D8
A0
DRAMS: D0~D8
VSS
B0
DRAMS: D9~D17
PDE
VCC
VSS
Rev.0.1/Apr.01
DQ 36
DQ 37
DQ 38
DQ 39
D0~D17, Buffer
0.1uF or 0.22uF Capacitor
per each DRAMs
D0~D17, Buffer
VCC
VSS
D9
D10
D11
D12
D13
D14
D15
D16
D17
(when= 0, 1= NC)
+
4.7uF Tantal
Capacitor
3
HYMA6V16733F14HGTG
Absolute Maximum Ratings* (TA=0 to 70 oC)
Parameter
Symbol
Rating
Unit
Ambient Temperature
TA
0 ~ 70
oC
Storage Temperature
TSTG
-55 ~ 125
oC
Voltage on Any Pin relative to Vss
VIN / OUT
-0.5 ~ 4.6
V
Voltage on Vcc relative to Vss
Vcc
-0.5 ~ 4.6
V
Short Circuit Output Current
IOUT
50
mA
Power Dissipation
PD
21
W
* Note : 1. Stress greater than above absolute maximum ratings may cause permanent damage to the device
Recommended DC Operating Conditions (TA=0 to 70 oC)
Parameter
Symbol
Min
Typ.
Max
Unit
Note
Power Supply Voltage
Vcc
3.0
3.3
3.6
V
1
Input High Voltage
VIH
2.0
-
Vcc + 0.3
V
1
Input Low Voltage
VIL
-0.3
-
0.8
V
1
* Note : 1. All voltage referenced to Vss
Rev.0.1/Apr.01
4
HYMA6V16733F14HGTG
DC Electrical Characteristics (TA = 0 ~ 70oC, Vcc = 3.3V +/- 0.3V )
Symbol
Parameter
VOH
Output Level
Output “H” Level voltage(Iout= -2mA)
VOL
Output Level
Output “L” Level voltage(Iout=2mA)
ICC1
Operating current
Average power supply operating current
( /RAS, /CAS Cycling : tRC = tRC min)
Min
Max
Unit
2.4
Vcc
V
0
0.4
V
50ns
-
2160
60ns
-
1820
-
56
mA
ICC2
Standby current (TTL interface)
Power supply standby current
(/RAS, /UCAS,/LCAS=VIH, Dout = High-Z)
50ns
-
2160
ICC3
/RAS only refresh current
Average power supply current
/RAS only refresh mode
(/RAS cycling, /CAS=VIH, tRC= tRC min)
60ns
-
1820
Extended data out page mode current
(/RAS=VIL, /CAS, Address cycling : tHPC=tHPC min)
50ns
-
1980
60ns
-
1820
-
29
50ns
-
2160
60ns
-
1820
ICC4
ICC5
Standby current (CMOS )
Power supply standby current
( /RAS, /UCAS, /LCAS >= Vcc-0.2V, Dout = High-Z)
ICC6
/CAS-before-/RAS refresh current (tRC=tRC min)
Note
1, 2
mA
mA
2
mA
1, 3
mA
mA
ICC7
Battery back up operating current (standby with CBR)
(tRC=31.25us, tRAS=300ns, Dout=High-Z)
-
110
uA
II(L)
Input leakage current, Any input (0V<= Vin<=Vcc)
-5
5
uA
IO(L)
Output leakage current, (Dout is disabled, 0V<= Vout<=Vcc)
-5
5
uA
1
Note : 1. Icc depends on output load condition when the device is selected. Icc(max) is specified at the output open condition
2. Address can be changed once or less while /RAS = VIL
3. Address can be changed once or less while /CAS = VIH
Rev.0.1/Apr.01
5
HYMA6V16733F14HGTG
Capacitance
( Vcc = 3.3V +/- 0.3V, TA = 25C, f = 1MHz )
Parameter
Symbol
Min.
Max
Unit
Note
Input capacitance (A0 ~ A12, B0)
CI1
-
20
pF
1
Input capacitance (/WE0, /WE2, /OE0,/OE2)
CI2
-
20
pF
1,2
Input capacitance (/RAS0, /RAS2)
CI3
-
65
pF
1,2
Input capacitance (/CAS0, /CAS4)
CI4
-
20
pF
1,2
Output capacitance (DQ0 ~ DQ71)
CI/O
-
20
pF
1, 2
Note : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method
2. /CAS = VIH to disable Dout
AC Characteristics (Vcc=3.3V +/-10%, TA=0~70C, Note 1, 2, 19)
Test Condition
•
Input rise and fall times : 2ns
•
Input level : VIL / VIH = 0.0 / 3.0V
•
Input timing reference levels
: VIL / VIH = 0.8 / 2.0V
•
Output timing reference levels
: VOL / VOH = 0.8 / 2.0V
•
Output load : 1 TTL gate + CL(100pF)
(Including scope and jig)
Read, Write, Read-modify-write and Refresh Cycles
-50
Parameter
-60
Symbol
Unit
Min
Max
Min
Max
Note
Random read or write cycle time
tRC
84
-
104
-
ns
/RAS precharge time
tRP
30
-
40
-
ns
/CAS precharge time
tCP
10
-
10
-
ns
/RAS pulse width
tRAS
50
10,000
60
10,000
ns
/CAS pulse width
tCAS
8
10,000
10
10,000
ns
Row address set-up time
tASR
5
-
5
-
ns
Row address hold time
tRAH
10
-
10
-
ns
Column address set-up time
tASC
0
-
0
-
ns
Column address hold time
tCAH
10
-
10
-
ns
/RAS to /CAS delay time
tRCD
14
32
14
40
ns
3
/RAS to Column address delay time
tRAD
12
20
12
25
ns
4
/RAS hold time
tRSH
8
-
20
-
ns
/CAS hold time
tCSH
30
-
40
-
ns
/CAS to /RAS precharge time
tCRP
10
-
10
-
ns
Rev.0.1/Apr.01
6
HYMA6V16733F14HGTG
- continued -50
Parameter
-60
Symbol
Min
Max
Min
Max
Unit
Note
/OE to Din delay time
tODD
18
-
20
-
ns
5
/OE delay time from Din
tDZO
0
-
0
-
ns
6
/CAS delay time from Din
tDZC
0
-
0
-
ns
6
Transition time ( Rise and Fall)
tT
2
50
2
50
ns
7
Refresh period
tREF
-
64
-
64
ms
8K Ref.
Parameter
Symbol
Unit
Note
Read Cycles
-50
-60
Min
Max
Min
Max
Access time from /RAS
tRAC
-
50
-
60
ns
8, 9
Access time from /CAS
tCAC
-
18
-
20
ns
9,10,17
Access time from column address
tAA
-
30
-
35
ns
9,11,17
Access time from /OE
tOAC
-
18
-
20
ns
9
Read command set-up time
tRCS
0
-
0
-
ns
Read command hold time to /CAS
tRCH
0
-
0
-
ns
12
Read command hold time to /RAS
tRRH
0
-
0
-
ns
12
Column address to /RAS lead time
tRAL
30
-
35
-
ns
Column address to /CAS lead time
tCAL
13
-
18
-
ns
Output buffer turn off delay time from /CAS
tOFF
-
18
-
20
ns
13,21
Output buffer turn off delay time from /OE
tOEZ
-
18
-
20
ns
13
/CAS to Din delay time
tCDD
18
-
20
-
ns
5
/OE pulse width
tOEP
13
-
15
-
ns
Rev.0.1/Apr.01
7
HYMA6V16733F14HGTG
Write Cycles
-50
Parameter
-60
Symbol
Min
Max
Min
Max
Unit
Note
Write command set-up time
tWCS
0
-
0
-
ns
14
Write command hold time
tWCH
5
-
10
-
ns
21
Write command pulse width
tWP
10
-
10
-
ns
Write command to /RAS lead time
tRWL
20
-
20
-
ns
Write command to /CAS lead time
tCWL
8
-
10
-
ns
Data-in set-up time
tDS
0
-
0
-
ns
15
Data-in hold time
tDH
10
-
15
-
ns
15
Unit
Note
Read-Modify-Write Cycles
-50
Parameter
-60
Symbol
Min
Max
Min
Max
Read-modify-write cycle time
tRWC
128
-
140
-
ns
/RAS to /WE delay time
tRWD
72
-
84
-
ns
14
/CAS to /WE delay time
tCWD
30
-
34
-
ns
14
Column address to /WE delay time
tAWD
42
-
49
-
ns
14
/OE hold time from /WE
tOEH
13
-
15
-
ns
Refresh cycles
-50
Parameter
-60
Symbol
Unit
Min
Max
Min
Max
/CAS set-up time
( /CAS-before-/RAS Refresh Cycle)
tCSR
5
-
5
-
ns
/CAS hold time
( /CAS-before-/RAS Refresh Cycle)
tCHR
10
-
10
-
ns
/RAS precharge to /CAS hold time
tRPC
5
-
5
-
ns
/CAS precharge time in normal mode
tCPN
10
-
10
-
ns
Rev.0.1/Apr.01
Note
8
HYMA6V16733F14HGTG
Fast Page Mode Cycles
-50
Parameter
-60
Symbol
Unit
Min
Max
Min
Max
Note
Fast page mode cycle time
tPC
35
-
40
-
ns
Fast page mode /CAS precharge time
tCP
10
-
10
-
ns
Fast page mode /RAS pulse width
tRASP
-
100K
-
100K
ns
16
Access time from /CAS precharge
tACP
-
30
-
35
ns
9,17
/RAS hold time from /CAS precharge
tRHCP
30
-
35
-
ns
Fast page mode read-modify-write cycle
/CAS precharge to /WE delay time
tCPW
50
-
55
-
ns
Fast page mode read-modify-write cycle time
tPRWC
76
-
85
-
ns
Test Mode Cycles
-50
Parameter
-60
Symbol
Unit
Min
Max
Min
Max
Test mode /WE set-up time
tWS
0
-
0
-
ns
Test mode /WE hold time
tWH
10
-
10
-
ns
Note
Counter Test Cycles
-50
Parameter
/CAS precharge time in counter test cycle
Rev.0.1/Apr.01
-60
Symbol
tCPT
Unit
Min
Max
Min
Max
40
-
40
-
Note
ns
9
HYMA6V16733F14HGTG
Notes :
1. AC measurements assume t T = 2ns
2. AC initial pause of 200us is required after power up followed by a minimum of eight initialization cycles
( any combination of cycles containing /RAS-only refresh or /CAS-before-/RAS refresh)
3. Operation with the tRCD(max) limit insures that tRAC(max) can be met, t RCD(max) is specified as a
reference point only : if tRCD is greater than the specified tRCD(max) limit, then access time is
controlled exclusively by tCAC.
4. Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a
reference point only : if tRAD is greater than the specified tRAD(max) limit, then access time is
controlled exclusively by tAA.
5. Either tODD or tCDD must be satisfied.
6. Either tDZO or tDZC must be satisfied.
7. VIH(min) and VIL(max) are reference levels for measuring timing of input signals, also transition times
are measured between V IH(min) and VIL(max)
8. Assumes that tRCD<=tRCD(max) and tRAD<=tRAD(max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown
9. Measured with a load circuit equivalent to 1 TTL loads and 100pF.
10. Assumes that tRCD>=tRCD(max) and tRCD + tCAC(max) >= tRAD + tAA(max)
11. Assumes that tRAD>=tRAD(max) and tRCD + tCAC(max) <= tRAD + tAA(max)
12. Either tRCH of tRRH must be satified for a read cycles
13. tOFF(max), tOEZ(max), tOFR(max) and tWEZ(max) define the time at which the outputs achieve the
open circuit condition and is not referenced to output voltage levels
14 tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in
the data sheet as electrical characteristics only : If tWCS >=tWCS(min), the cycle is an early write
cycle and the data out pin will remain open circuit(high impedance) throughout the entire cycle :
If tRWD>=tRWD(min), tCWD>=tCWD(min), tAWD>=tAWD(min), the cycle is a read-modify-write and
the data output will contain data read from the selected cell : if neither of the above sets of conditions
is satified, the condition of the data out (at access time) is indeterminate.
15. tDS and tDH are refered to /CAS leading edge in early write cycles and to /WE leading edge in delayed
write or read-modify-write cycles
16. tRASP defineds /RAS pulse width in extended data out mode cycles
17. Access time is determined by the longest among tAA, tCAC and tACP
18 In delaying write or read-modify-write cycles, /OE must disable output buffer prior to applying data to
the device.
Rev.0.1/Apr.01
HYMA6V16733F14HGTG
19. When output buffers are enabled once, sustain the low impedence state until valid data is obtained.
when output buffer is turned on and off within a very short time, generally it causes large Vcc/Vss line
noise, which causes to degrade V IH min / VIL max level
20. tHPC(min) can be achieved during a series of EDO mode early write cycles or EDO mode read cycels
If both write and read operation are mixed in a EDO mode, /RAS cycle[EDO mode mix cycle (1)(2)]
minimum value of /CAS cycle t HPC[tCAS + tCP + 2tT] become greater than the specified tHPC(min)
value. The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle
(1) and (2)
21. Data output turns off and becomes high impedance from later rising edge of /RAS and /CAS.
Hold time and turn off time are specified by the timing specifications of later rising edge of /RAS and
/CAS between tOHR and tOH and between tOFR and tOFF
22. tDOH defines the time at which the output level go cross, VOL=0.8V, VOH=2.0V of output timing
reference level.
23. Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within 64ms
period on the condition a) and b) below
a) Enter self refresh mode within 15.6us after either burst refresh or distributed refresh at equal interval
to all refresh addresses are completed.
b) Start burst refresh or distributed refresh at equal interval to all refresh addresses within 15.6us after
exiting from self refresh mode
24. In case of entering from /RAS-only-refresh, It is necessary to execute CBR refresh before and after
self refresh mode according as note 23
25. For L-version, It is available to apply each 128ms and 31.2us instead of 64ms and 15.6us at note 23
26. At tRASS > 100us, self refresh mode is activated, and not active at tRASS < 10us, It is undefined within
the range of 10us < tRASS < 100us. For tRASS > 10us, It is necessary to satify tRPS
27. XXX : H or L [ H : VIH(min) <= VIN <=VIH(max), L : VIH(min) <=VIN <=VIH(max)]
///// : Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must be
applied VIH or VIL
Rev.0.1/Apr.01
HYMA6V16733F14HGTG
Timing Waveforms
tRAS
tRP
RAS
tCSH
tCRP
tRCD
tRSH
tCAS
tT
CAS
tRAD
tASR
ADDRESS
tRAL
tASC
tRAH
ROW
tCAH
COLUMN
tRRH
tRCS
tRCH
WE
tCAC
tOFF
tAA
High-Z
DOUT
DOUT
tRAC
tOEZ
tDZC
tCDD
High-Z
DIN
tDZO
tOAC
tOED
OE
*
Figure 1. Read Cycle
Rev.0.1/Apr.01
: Don`t care
HYMA6V16733F14HGTG
tRC
tRAS
tRP
RAS
tRSH
tT
tRCD
tCAS
tCRP
tCSH
CAS
tASR
ADDRESS
tRAH
tASC
ROW
tCAH
COLUMN
tWCS
tWCH
WE
tDS
DIN
tDH
DIN
High-Z
DOUT
*
**
: Don`t care
OE : Don`t care
*** tWCS >
= tWCS (min)
Figure 2. Early Write Cycle
Rev.0.1/Apr.01
HYMA6V16733F14HGTG
tRC
tRAS
tRP
RAS
tRSH
tT
tRCD
tCAS
tCRP
tCSH
CAS
tASR
ADDRESS
tRAH
tCAH
tASC
ROW
COLUMN
tCWL
tRCS
tRWL
tWP
WE
tDZC
tDH
tDS
High-Z
DIN
DIN
tOED
tDZO
tOEH
OE
tOEZ
High-Z
DOUT
**
INVALID
OUTPUT
*
: Don`t care
** Invalid DOUT comes out,
when OE is low level.
Figure 3 . Delayed Write Cycle
Rev.0.1/Apr.01
HYMA6V16733F14HGTG
tRWC
tRAS
tRP
RAS
tT
tRCD
tCAS
tCRP
CAS
tRAD
tRAH
tASR
ADDRESS
tASC
tCAH
COLUMN
ROW
tCWL
tRWL
tWP
tCWD
tAWD
tRCS
tRWD
WE
tAA
tRAC
tDZC
High-Z
DIN
tDH
tDS
tCAC
DIN
tOED
tOEH
High-Z
DOUT
DOUT
tDZO
tOAC
tOEZ
OE
*
Figure 4. Read Modify Write Cycle
Rev.0.1/Apr.01
: Don`t care
HYMA6V16733F14HGTG
tRC
tRAS
tRP
RAS
tCRP
tT
tRPC
tCRP
CAS
tASR
ADDRESS
tRAH
ROW
High-Z
DOUT
* OE,WE : Don`t care
** Rrfresh address :
A0~A12 (AX0 ~ AX12)
Figure 5. /RAS only Refresh Cycle
tRC
tRP
tRAS
tRC
tRP
tRAS
tRP
RAS
tRPC
tCPN
tT
tCSR
tRPC
tCHR
tCPN
tCRP
tCSR
tCHR
CAS
ADDRESS
tOFF
DOUT
INVALID
DOUT
High-Z
: Don`t care
*
**
WE : VIH
Figure 6. /CAS before /RAS Refresh Cycle
Rev.0.1/Apr.01
HYMA6V16733F14HGTG
tRC
tRC
tRAS
tRP
(Read)
tRAS
tRC
tRP
tRAS
(Refresh)
tRP
(Refresh)
RAS
tT
tCHR
tRSH
tRCD
tCRP
tCAS
CAS
tRAD
tASR
ADDRESS
tRAH
tRAL
tCAH
tASC
ROW
COLUMN
tRCH
tRCS
tRRH
WE
tCAC
tAA
tOFF
tRAC
DOUT
High-Z
DOUT
tDZC
tOEZ
High-Z
DIN
tCDD
tDZO
tOAC
tOED
OE
*
Figure 7. Hidden Refresh Cycle
Rev.0.1/Apr.01
: Don`t care
HYMA6V16733F14HGTG
tRASP
tRP
tRHCP
RAS
tT
tCSH
tRCD
tHPC
tCAS
tCP
tCAS
tRSH
tCP
tCAS
tCRP
CAS
tRAD
tRAL
tCSH
tASR
ADDRESS
tRAH
ROW
tASC
tCAH
tASC
COLUMN
tCAH
COLUMN
tASC
tCAH
COLUMNN
tRCH
tRCHA
tRCS
tRRH
tRCHC
WE
tOAC
OE
tRAC
tAA
tCAC
DOUT
tCPA
tAA
tCAC
High-Z
tCPA
tAA
tCAC
tOEZ
tDOH
DOUT 1
tOH
tDOH
DOUT 2
DOUT N
*
Figure 8. Fast Page Mode Read Cycle
Rev.0.1/Apr.01
tWEZ
tOHR
tOFR
tOFF
: Don`t care
HYMA6V16733F14HGTG
tRASP
tRP
tCPRH
RAS
tT
tHPC
tCSH
tCP
tCP
tCAS
tRSH
tCAS
tCAS
tRCHR
tRCHC
tRCH
tRCS
tCRP
tHPC
tCP
tCAS
CAS
tHPC
tRRH
tRCS
tRCH
WE
tRAL
tASC tCAH
tASR
ADDRESS
ROW
tASC
tASC
tCAH
tCAH
tASC
tCAH
tRAH
COLUMN 1
COLUMN 2
tCAL
COLUMN 3
tCAL
COLUMN N
tCAL
tCOL
tOFR
tOFF
tOHR
tOH
tCAL
tCOP
OE
tCPA
tAA
tOAC
tCAC
tAA
tRAC tWEZ
tOEZ
tCPA
tAA
tCAC
tCAC
tOAC
tCPA
tAA
tOEZ
tDOH
tOEZ
tCAC
tOAC
High-Z
DOUT
DOUT 1
DOUT 2
DOUT 2
DOUT 3
DOUT N
Figure 9. Fast Page Mode Read Cycle( /OE Control)*
* Note : FP Hi-Z control by /OE or /WE. /OE rising edge disables data outputs.
When /OE goes high during /CAS high, the data will not come out until next /CAS access.
When /WE goes low during /CAS high, the data will not come out until next /CAS access.
Rev.0.1/Apr.01
HYMA6V16733F14HGTG
tRP
tRASP
RAS
tT
tHPC
tCSH
tRCD
tCAS
tCP
tRSH
tCAS
tCRP
tCP
tCAS
CAS
tASR
tRAH
ADDRESS
tASC
ROW
tASC
tCAH
COLUMN 2
COLUMN 1
tWCS
tWCH
tWCS
tCAH
tASC
tCAH
COLUMN N
tWCH
tWCS
tWCH
WE
tDS
DIN
tDH
tDS
D IN 1
tDH
tDS
DIN 2
tDH
DIN N
High-Z
DOUT
* OE : Don`t care
** tWCS ¡ ÃtWCS (min)
***
Figure 10. Fast Page Mode Early Write Cycle
Rev.0.1/Apr.01
: Don`t care
HYMA6V16733F14HGTG
tRP
tRASP
RAS
tCP
tT
tCP
tCSH
tCRP
tHPC
tRCD
tCAS
tRSH
tCAS
tCAS
CAS
tRAD
tASR
tASC
tRAH
ADDRESS
tASC
tASC
tCAH
ROW
tCAH
tCAH
COLUMN 1
COLUMN 2
COLUMN N
tCWL
tRCS
tCWL
tRCS
tCWL
tRWL
tRCS
WE
tWP
tDZC
tDS
tWP
tDS
tDZC
tDH
DIN
tDH
tDZO
tOED
tDH
DIN 2
DIN 1
tDZO
tWP
tDS
tDZC
DIN N
tDZO
tOED
tOEH
tOED
tOEH
tOEH
OE
tCLZ
tCLZ
tOEZ
High-Z
DOUT
INVALID
DOUT
tCLZ
tOEZ
tOEZ
INVALID
DOUT
INVALID
DOUT
*
: Don`t care
> tCWL
** tOEH=
Figure 11. Fast Page Mode Delayed Write Cycle
Rev.0.1/Apr.01
HYMA6V16733F14HGTG
tRP
tRASP
RAS
tHPRWC
tT
tCRP
tCP
tRCD
tCAS
tRSH
tCP
tCAS
tCAS
CAS
tRAD
tASR
ADDRESS
tASC
tASC
tCAH
tRAH
ROW
tCAH
tCAH
COLUMN 1
tRCS
tASC
COLUMN 2
tRWD
tAWD
tCWD
COLUMN N
tRCS
tCPW
tAWD
tCWD
tDZC
tDS
tCWL
tRCS
tCPW
tAWD
tCWD
tDZC
tDS
tCWL
tCWL
tRWL
WE
tWP
tDZC
tDS
tWP
tDH
DIN
tWP
tDH
DIN 1
tDH
D IN 2
DIN N
tDZO
tDZO
tOED
tDZO
tOED
tOEH
tOAC
tCAC
tAA
tRAC
tOED
tOEH
tOEZ
OE
tOEH
tOEZ
tOAC
tCAC
tAA
tCPA
tCLZ
tOEZ
tOAC
tCAC
tCPA
tCLZ
DOUT 1
tAA
tCLZ
DOUT 2
DOUT N
DOUT
*
** tOEH
Figure 12. Fast Page Mode Read Modify Write Cycle
Rev.0.1/Apr.01
High-Z
High-Z
: Don`t care
>
= tCWL
HYMA6V16733F14HGTG
tRP
tRASP
RAS
tT
tCP
tCAS
tRCD
CAS
tCP
tCP
tCAS
tCRP
tCAS
tCAS
tCSH
tRCHC
tRSH
tWP
tWCS tWCH
tCPW
WE
tRRH tRCH
tRAL
tAWD
tRAH
tASC
ADDRESS
ROW
tASC
tASC
tCAH
tASR
COLUMN
1
COLUMN
2
tCAH
COLUMN
4
COLUMN
3
tRDD
tDS
tDH
tDS
tASC
tCAH
tCAH
tCDD
tDH
Din
DIN 1
High - Z
DIN 3
tWDD
tOED
OE
tCAC
tOAC
tAA
tCPA
Dout
High - Z
tDOH
tCAC
tOEZ
tAA
tCPA
DOUT 2
tCAC
tAA
tOAC
tCPA
DOUT 3
Rev.0.1/Apr.01
tOFF
tOH
DOUT 4
*
Figure 13. Fast Page Mode Mix Cycle (1)
tOFR
: Don`t care
tWEZ
tOEZ
HYMA6V16733F14HGTG
tRP
tRASP
RAS
tT
tCSH
tCP
tCAS
tRCD
CAS
tCP
tCAS
tRCHR
tRCS
tRAH
tASC
tRSH
tWP
tRCH
t
tASC
tCAH
tCAH
tCAH
COLUMN
4
COLUMN
3
COLUMN
2
COLUMN
1
ROW
tCAL
tDS
High - Z
tOED
tCOL
tCAC
tAA
tOEZ
tCPA
tOAC
DOUT 1
High - Z
tCOP
tOEZ
tCAC
tAA
tOAC
tCPA
Figure 14. Fast Page Mode Mix Cycle(2)
tOFF
tOH
tOFR
D OUT 4
DOUT 3
*
Rev.0.1/Apr.01
tRDD
tCDD
DIN 3
OE
tCAC
tAA
tOAC
tRAC
tCAL
tCAL
tDH
tDS
tDH
DIN 2
tOED
tRRH
RAL
tASC
tASC
tCAH
tCAL
Dout
tCAS
tCPW
tASR
Din
tCAS
tRCH tWCH
tWCS
WE
ADDRESS
tCRP
tCP
: Don`t care
tWEZ
tOEZ
HYMA6V16733F14HGTG
Set Cycle***
Test Mode Cycle
Reset Cycle*
Normal Mode
~
~
RAS
~
~
~
~
CAS
~
~
WE
*
CBR or RAS-only refresh
**
: Don`t care
***
Address, DIN , OE: Don`t care
Figure 15. Test Mode Cycle
tRC
tRP
tRAS
tRP
RAS
tRPC
tCSR
tCHR
tT
CAS
tCPN
tRPC
tCRP
tCPN
tWS
tWH
WE
ADDRESS
tOFF
High-Z
DOUT
INVALID D OUT
*
Figure 16. Test Mode Set Cycle
Rev.0.1/Apr.01
: Don`t care
HYMA6V16733F14HGTG
tRC
tRAS
tRP
RAS
tT
tCSR
tCHR
tCPT
tRSH
tCRP
tCAS
CAS
tCAH
tASC
ADDRESS
COLUMN
tWS
tWH
tRRH
tRCH
tRCS
WE
tDZC
tCDD
High-Z
DIN
tOED
tDZO
OE
tOAC
tCAC
tOEP
tOEZ
tOFF
tAA
tRAC
High-Z
DOUT
DOUT
*
: Don`t care
Figure 17. /CAS Before /RAS Refresh Counter Check Cycle ( Read )
Rev.0.1/Apr.01
HYMA6V16733F14HGTG
tRC
tRAS
tRP
RAS
tCSR
tCHR
tCPT
tRSH
tCRP
tCAS
tT
CAS
tASC
ADDRESS
tCAH
COLUMN
tWS
tWH
tWCS
tWCH
WE
tDS
DIN
tDH
DIN
OE
High-Z
DOUT
*
: Don`t care
Figure 18. /CAS Before /RAS Refresh Counter Check Cycle ( Write )
Rev.0.1/Apr.01
HYMA6V16733F14HGTG
Package Dimension
Unit : mil (mm)
(1mm = 1/1000inches)
700(17.78)
1500(38.10)
157.48(4.0)
5250(133.35)
1
84
"C"1450(36.83)
450(11.43)
"B"
2150(54.61)
"A"
250(6.35)
1700(43.18)
4550(115.57)
5013.78(127.35)
157.48(4.0) max.
157.48(4.0) min.
(Front Side)
168
85
(Rear Side)
39.37(1.0)
39.37(1.0)
R78.74
(2.0)
125(3.175)
50(1.27)
125(3.175)
39.37(1.0)
DETAIL "C"
78.74(2.0)
DETAIL "B"
Note :
1. Tolerances on all dimensions +/- 5 ( 0.127) unless otherwise spedified
2. Thickness includes Plating and / or Metallization
Rev.0.1/Apr.01
DETAIL "A"
100(2.54) min.
R78.74
(2.0)
5.9(0.15)
122.83(3.12)
78.74(2.0)
50(1.27)