. Preliminary IBM04184AQLAD IBM04364AQLAD 128K x 36 & 256K x 18 SRAM Features • 128K x 36 or 256K x 18 Organizations • Common I/O • • Asynchronous Output Enable and Power Down Inputs CMOS Technology • Synchronous Register Latch Mode Of Operation with Self-Timed Late Write • Single Differential Input and Output Clock • +3.3V Power Supply, 1.9V VDDQ, VREF & Ground • Pseudo HSTL Input and Output levels • Registered Addresses, Write Enables, Sync Select and Data Ins • Boundary Scan using limited set of JTAG 1149.1 functions • Byte Write Capability & Global Write Enable • 7 x 17 Bump Ball Grid Array Package with SRAM JEDEC Standard Pinout and Boundary SCAN Order • Programmable Impedance Output Drivers Description The IBM04184AQLAD and IBM04364AQLAD 4Mb SRAMS are Synchronous Register Latch Mode, high performance CMOS Static Random Access Memories that are versatile, wide I/O, and achieve 5.0ns access and cycle times. Dual differential K clocks are used to initiate the read/write operation, and all internal operations are self-timed. At the rising edge 03K4297.E35614 Revised 2/99 of the K Clock, all Addresses, Write-Enables, Sync Select, and Data Ins are registered internally. An internal write buffer allows write data to follow one cycle after addresses and controls. The chip is operated with a +3.3V core power supply, has a 1.9V or 1.5V output power supply, and is compatible with HSTL I/O interfaces and 1.5V I/O levels as well. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 1 of 24 IBM04184AQLAD IBM04364AQLAD 128K x 36 & 256K x 18 SRAM Preliminary x36 BGA Bump Layout (Top View) 1 2 3 A VDDQ SA5 SA7 B NC NC SA8 4 5 6 7 NC SA16 SA14 VDDQ NC SA11 NC NC C NC SA6 SA9 VDD SA10 SA15 NC D DQc18 DQc19 VSS ZQ VSS DQb10 DQb9 E DQc20 DQc21 VSS SS VSS DQb12 DQb11 F VDDQ DQc22 VSS G VSS DQb13 VDDQ G DQc23 DQc24 SBWc NC SBWb DQb15 DQb14 H DQc25 DQc26 VSS NC VSS DQb17 DQb16 J VDDQ VDD VREF VDD VREF VDD VDDQ K DQd34 DQd35 VSS K VSS DQa8 DQa7 L DQd32 DQd33 SBWd K SBWa DQa6 DQa5 M VDDQ DQd31 VSS SW VSS DQa4 VDDQ N DQd29 DQd30 VSS SA0 VSS DQa3 DQa2 P DQd27 DQd28 VSS SA1 VSS DQa1 DQa0 R NC SA4 M1* VDD M2* SA12 NC T NC NC SA3 SA2 SA13 NC ZZ VDDQ TMS TDI TCK TDO NC VDDQ U Note: * M1 and M2 are clock mode pins. For this application, M1 and M2 must connect to VDD and VSS, respectively. x18 BGA Bump Layout (Top View) 1 2 3 4 5 6 7 A VDDQ SA5 SA7 NC SA16 SA14 VDDQ B NC NC SA8 NC SA11 NC NC C NC SA6 SA9 VDD SA10 SA15 D DQb9 NC VSS ZQ VSS DQa1 NC E NC DQb12 VSS SS VSS NC DQa2 F VDDQ NC VSS G VSS DQa4 VDDQ G NC DQb15 SBWb NC VSS NC DQa5 H DQb16 NC VSS NC VSS DQa8 NC J VDDQ VDD VREF VDD VREF VDD VDDQ K NC DQb17 VSS K VSS NC DQa7 L DQb14 NC VSS K SBWa DQa6 NC M VDDQ DQb13 VSS SW VSS NC VDDQ N DQb11 NC VSS SA0 VSS DQa3 NC P NC DQb10 VSS SA1 VSS NC DQa0 R NC SA4 M1 VDD M2 SA13 NC NC T NC SA2 SA3 NC SA17 SA12 ZZ U VDDQ TMS TDI TCK TDO NC VDDQ Note: * M1 and M2 are clock mode pins. For this application, M1 and M2 must connect to VDD and VSS, respectively. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 2 of 24 03K4297.E35614 Revised 2/99 IBM04184AQLAD IBM04364AQLAD 128K x 36 & 256K x 18 SRAM Preliminary Pin Description SA0-SA17 Address Input G Asynchronous Output Enable DQ0-DQ35 Data I/O SS Synchronous Select K, K Differential Input Register Clocks M1, M2 Clock Mode Inputs - Selects Single or Dual Clock Operation. SW Write Enable, Global VREF(2) GTL/HSTL Input Reference Voltage SBWa Write Enable, Byte a (DQ0-DQ8) VDD Power Supply (+3.3V) SBWb Write Enable, Byte b (DQ9-DQ17) VSS Ground SBWc Write Enable, Byte c (DQ18-DQ26) VDDQ SBWd Write Enable, Byte d (DQ27-DQ35) ZZ Asynchronous Sleep Mode TMS,TDI,TCK IEEE 1149.1 Test Inputs (LVTTL levels) ZQ Output Driver Impedance Control TDO IEEE 1149.1 Test Output (LVTTL level) NC No Connect Output Power Supply Block Diagram WR Add Register 2:1 MUX RD Add Register Latch ZZ SW SW Register SW Register SBW Register SBW Register Row Decode SA0-SA17 K SS 128K x 36 or 256K x 18 Array Column Decode Read/Write Amp SBW Latch Match 2:1 MUX Write Buffer SS Register SS Register Data Out Latch G DQ0-DQ35 03K4297.E35614 Revised 2/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 3 of 24 IBM04184AQLAD IBM04364AQLAD 128K x 36 & 256K x 18 SRAM Preliminary SRAM Features Late Write Late Write function allows for write data to be registered one cycle after addresses and controls. This feature will alleviate SRAM data bus contention going from a Read to Write cycle by eliminating one dead cycle. Late Write is accomplished by buffering write addresses and data so that the write operation occurs during the next write cycle. In case a read cycle occurs after a write cycle, the address and write data information are stored temporarily in holding registers. During the first write cycle preceded by a read cycle, the SRAM array will be updated with address and data in the holding registers. Read cycle addresses are monitored to determine if read data is to be supplied from the SRAM array or the write buffer. The bypassing of the SRAM array occurs on a byte by byte basis. When one byte is written during a write cycle, read data from the last written address will have new byte data from the write buffer and remaining bytes from the SRAM array. Mode Control Mode control pins: M1 and M2 are used to select four different JEDEC standard read protocols. This SRAM supports the single Clock Register Latch (M1 = VDD, M2 = VSS). This data sheet only describes single differential Clock Register Latch functionality. Mode control inputs must be set with power up and must not change during SRAM operation. Power Down Mode Power Down Mode or “Sleep” Mode is enabled by switching asynchronous signal ZZ High. When powering the SRAM down, inputs should be dropped first followed by VREF then VDDQ; VDD must be dropped last. VDDQ can be simultaneously dropped with VDD. Programmable Impedance/Power Up Requirements An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow for the SRAM to adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of 15% is between 175Ω and 350Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by drifts in supply voltage and temperature. One evaluation occurs every 64 clock cycles and each evaluation may move the output driver impedance level only one step at a time toward the optimum level. The output driver has 32 discrete binary weighted steps. The impedance update of the output driver occurs when the SRAM is in High-Z. Write and Deselect operations will synchronously switch the SRAM into and out of High-Z, therefore triggering an update. The user may choose to invoke asynchronous G updates by providing a G setup and hold about the K Clock to guarantee the proper update. Power up requirements for the SRAM are that VDD must be powered before or simultaneously with VDDQ followed by VREF; inputs should be powered last. The limitation on VDDQ is that it must not exceed VDD by more than 0.4V during power up. In order to guarantee the optimum internally regulated supply voltage, the SRAM requires 4µs of power-up time after VDD reaches its operating range.To guarantee optimum output driver impedance after power up, the SRAM needs 2080 clock cycles followed by a single Low-Z to High-Z transition at the end of 2080 cycles. Sleep Mode Operation Sleep mode is a low power mode initiated by bringing the asynchronous ZZ pin HIGH. During sleep mode, all other inputs are ignored and outputs are brought to a High-Z state. Sleep mode current and output High Z are ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 4 of 24 03K4297.E35614 Revised 2/99 IBM04184AQLAD IBM04364AQLAD 128K x 36 & 256K x 18 SRAM Preliminary guaranteed after the specified sleep mode enable time. During sleep mode, the array data contents are preserved. Sleep mode must not be initiated until after all pending operations have completed, as any pending operation is not guaranteed to properly complete after sleep mode is initiated. Sense amp data is lost. Normal operation can be resumed by bringing ZZ low, but only after specified sleep mode recovery time. Ordering Information Part Number IBM04184AQLAD-5P IBM04184AQLAD-5 IBM04184AQLAD-6 IBM04364AQLAD-5P IBM04364AQLAD-5 IBM04364AQLAD-6 03K4297.E35614 Revised 2/99 Organization 256K x 18 256K x 18 256K x 18 128K x 36 128K x 36 128K x 36 Speed 5.0ns Access / 5.0ns Cycle 5.5ns Access / 5.5ns Cycle 6.0ns Access / 6.0ns Cycle 5.0ns Access / 5.0ns Cycle 5.5ns Access / 5.5ns Cycle 6.0ns Access / 6.0ns Cycle Leads 7 x 17 BGA 7 x 17 BGA 7 x 17 BGA 7 x 17 BGA 7 x 17 BGA 7 x 17 BGA ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 5 of 24 IBM04184AQLAD IBM04364AQLAD 128K x 36 & 256K x 18 SRAM Preliminary Output Enable Truth Table Operation G DQ Read L DOUT 0-35 Read H High-Z Sleep (ZZ=H) X High-Z Write (SW=L) X High-Z Deselect (SS=H) X High-Z Clock Truth Table K CLK ZZ SS SW SBWA SBWB SBWC SBWD DQ (n) DQ (n+1) Mode L→H L L H X X X X DOUT 0-35 X Read Cycle All Bytes L→H L L L L H H H High-Z DIN 0-8 Write Cycle 1st Byte L→H L L L H L H H High-Z DIN 9-17 Write Cycle 2nd Byte L→H L L L H H L H High-Z DIN 18-26 Write Cycle 3rd Byte L→H L L L H H H L High-Z DIN 27-35 Write Cycle 4th Byte L→H L L L L L L L High-Z DIN 0-35 Write Cycle All Bytes L→H L L L H H H H High-Z High-Z Abort Write Cycle L→H L H X X X X X High-Z X Deselect Cycle X H X X X X X X High-Z High-Z Sleep Mode Absolute Maximum Ratings Item Symbol Rating Units Notes Power Supply Voltage VDD -0.5 to 3.9 V 1 Input Voltage VIN -0.5 to VDD+0.5 V 1 VOUT -0.5 to VDD+0.5 V 1 TJ 0 to +110 °C 1 Storage Temperature TSTG -55 to +125 °C 1 Short Circuit Output Current IOUT 25 mA 1 Output Voltage Operating Temperature 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 6 of 24 03K4297.E35614 Revised 2/99 IBM04184AQLAD IBM04364AQLAD 128K x 36 & 256K x 18 SRAM Preliminary PBGA Thermal Characteristics Item Thermal Resistance Junction to Case Symbol Rating Units RΘJC 1 °C/W AC Input Characteristics Item Symbol Min AC Input Logic High (Volts) VIH (ac) VREF+0.4 AC Input Logic Low (Volts) VIL (ac) Clock Input Differential Voltage (Volts) VDIF (ac) VREF Peak to Peak ac Voltage (Volts) VREF (ac) Max Notes 3 VREF-0.4 0.4 3 2 5% VREF (dc) 1 1. The peak to peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF. Implies very stable signal. Sourcing from VDDQ not recommended. Separate board plane recommended. Do not use noisy signal line. 2. Performance is a function on VIH and VIL levels to clock inputs. 3. See AC Input Definition figure on page 9. AC Input Definition VIH (ac) VREF VIL (ac) 03K4297.E35614 Revised 2/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 7 of 24 IBM04184AQLAD IBM04364AQLAD 128K x 36 & 256K x 18 SRAM Preliminary Recommended DC Operating Conditions (TA=0 to 85°C) Parameter Symbol Min. Typ. Max. Units Notes VDD 3.135 3.3 3.465 V 1 VDDQ 1.4 1.9 2.0 V 1 Input High Voltage VIH VREF +0.1 — VDDQ + 0.3 V 1, 2 Input Low Voltage VIL -0.3 — VREF -0.1 V 1, 3 VREF 0.68 0.75 0.90 V 1 Clocks Signal Voltage VIN - CLK -0.3 — VDDQ + 0.3 V 1, 4 Differential Clocks Signal Voltage VDIF - CLK 0.1 — VDDQ + 0.6 V 1, 5 Clocks Common Mode Voltage VCM - CLK 0.55 — 0.90 V 1 IOUT — 5 8 mA Supply Voltage Output Driver Supply Voltage Input Reference Voltage Output Current 1. 2. 3. 4. 5. All voltages referenced to VSS. All VDD, VDDQ and VSS pins must be connected. VIH(Max)DC = VDDQ + 0.3V, VIH(Max)AC = VDD + 1.5V (pulse width ≤ 4.0ns). VIL(Min)DC = - 0.3V, VIL(Min)AC= -1.5V (pulse width ≤ 4.0ns). VIN-CLK specifies the maximum allowable DC excursions of each differential clock (K, K). VDIF-CLK specifies the minimum Clock differential voltage required for switching. Capacitance (TA=0 to 85°C, VDD=3.3V ±5%, f=1MHz) Parameter Input Capacitance Data I/O Capacitance (DQ0-DQ35) ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 8 of 24 Symbol Test Condition Max Units CIN VIN = 0V 4 pF COUT VOUT = 0V 5 pF 03K4297.E35614 Revised 2/99 IBM04184AQLAD IBM04364AQLAD 128K x 36 & 256K x 18 SRAM Preliminary DC Electrical Characteristics (TA= 0 to +85°C, VDD=3.3V ±5%) Parameter Symbol Min. Max. Units Notes Average Power Supply Operating Current- x36 (IOUT = 0, VIN = VIH or VIL, ZZ & SS = VIL) IDD5.0 IDD5.5 IDD6 — — 675 650 575 mA 1 Average Power Supply Operating Current - x18 (IOUT = 0, VIN = VIH or VIL, ZZ & SS = VIL) IDD5.0 IDD5.5 IDD6 — — 625 600 525 mA 1 Power Supply Standby Current (ZZ= VIH, All other inputs = VIH or VIL, IOUT = 0) ISBZZ 150 mA 1 (SS=VIH, ZZ=VIL, All other inputs=VIH or VIL, IOUT=0) ISBSS 200 mA 1 — Input Leakage Current, any input (VIN = VSS or VDD) ILI — +1 µA Output Leakage Current (VOUT = VSS or VDD, DQ in High-Z ILO — +1 µA Output “High” Level Voltage (IOH=-6mA @ VDDQ / 2 + 0.3) VOH VDDQ -.4 VDDQ V 2 Output “Low” Level Voltage (IOL=+6mA @ VDDQ / 2 -0.3) VOL VSS VSS +.4 V 2 1. IOUT = Chip Output Current. IEYC means current at 5ns cycle time for example. 2. Minimum Impedance Output Driver. Programmable Impedance Output Driver DC Electrical Characteristics (TA= 0 to +85°C, VDD=3.3V ±5%) Parameter Symbol Min. Max. Units Notes Output “High” Level Voltage VOH VDDQ / 2 VDDQ V 1 Output “Low” Level Voltage VOL VSS VDDQ / 2 V 2 1. IOH = (VDDQ / 2) / (RQ / 5) ±15% @ VOH = VDDQ / 2 For: 150Ω ≤ RQ ≤ 350Ω. 2. IOL = (VDDQ / 2) / (RQ / 5) ±15% @ VOL = VDDQ / 2 For: 150Ω ≤ RQ ≤ 350Ω. 03K4297.E35614 Revised 2/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 9 of 24 IBM04184AQLAD IBM04364AQLAD 128K x 36 & 256K x 18 SRAM Preliminary AC Test Conditions (TA=0 to 85°C, VDD=3.3V ±5%, VDDQ =1.9V) Parameter Symbol Conditions Units Input High Level VIH 1.3 V Input Low Level VIL 0.4 V VREF 0.85 V Differential Clocks Voltage VDIF-CLK 0.75 V Clocks Common Mode Voltage VCM-CLK 1.3 V Input Rise Time TR 0.5 ns Input Fall Time TF 0.5 ns 0.85 V Differential Cross Point V Input Reference Voltage I/O Signals Reference Level (except K Clock) Clocks Reference Level Output Load Conditions Notes 1 1. See AC Test Loading figure on page 10. AC Test Loading 50 Ω 16.7Ω 50 Ω 0.85V 5pF 16.7Ω DQ 50 Ω 16.7Ω 50 Ω 0.85V 5pF 0.85V ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 10 of 24 03K4297.E35614 Revised 2/99 IBM04184AQLAD IBM04364AQLAD 128K x 36 & 256K x 18 SRAM Preliminary AC Characteristics (TA=0 to +85°C, VDD = 3.3V ±5%, VDDQ = 1.9V, Clocks run from 0.9 to 1.7V, VREF = 0.85). -5P Parameter -5 -6 Symbol Units Min. Max. Min. Max. Min. Max. Notes Cycle Time tKHKH 5.0 — 5.5 — 6.0 — ns Clock High Pulse Width tKHKL 1.5 — 1.5 — 1.5 — ns Clock Low Pulse Width tKLKH 1.5 — 1.5 — 1.5 — ns Clock High to Output Valid tKHQV — 5.0 — 5.5 — 6.0 ns 1 Clock Low to Output Valid tKLQV — 2.4 — 2.5 — 2.7 ns 1 Address Setup Time tAVKH 0.4 — 0.5 — 0.5 — ns 3 Address Hold Time tKHAX 1.0 — 1.0 — 1.5 — ns Sync Select Setup Time tSVKH 0.5 — 0.5 — 0.5 — ns Sync Select Hold Time tKHSX 1.0 — 1.0 — 1.5 — ns Write Enables Setup Time tWVKH 0.5 — 0.5 — 0.5 — ns Write Enables Hold Time tKHWX 1.0 — 1.0 — 1.5 — ns Data In Setup Time tDVKH 0.4 — 0.5 — 0.5 — ns Data In Hold Time tKHDX 0.8 — 1.0 — 1.5 — ns Clock Low to Data Out Hold Time tKLQX 0.5 — 0.5 — 0.5 — ns 1 3 Clock Low to Output Active tKLQX4 0.5 — 0.5 — 0.5 — ns 1, 2 Clock High to Output High-Z tKHQZ — 2.5 — 2.5 — 2.5 ns 1, 2 Output Enable to High-Z tGHQZ — 2.5 — 2.5 — 2.5 ns 1, 2 Output Enable to Low-Z tGLQX 0.5 — 0.5 — 0.5 — ns 1, 2 Output Enable to Output Valid tGLQV — 2.0 — 2.0 — 2.0 ns 1 Sleep Mode Recovery TIme tZZR 5.0 — 5.5 — 6.0 — ns Sleep Mode Enable TIme tZZE — 5.0 — 5.5 — 6.0 ns 1. See AC Test Loading on page 12. 2. Verified by design and tested without guardband. 3. For the -5P sort, this spec is Verified by design to 0.4ns. Strobed at 0.3ns 03K4297.E35614 Revised 2/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 11 of 24 IBM04184AQLAD IBM04364AQLAD 128K x 36 & 256K x 18 SRAM Preliminary Timing Diagram (Read and Deselect Cycles) tKLKH tKHKL tKHKH K tAVKH A1 SA A2 A3 A3 tKHAX A4 tKHSX SS tSVKH tWVKH SW tGLQV tKHWX tKHQZ tKHQV G tGHQZ tGLQX tKLQV tKHQZ tKHQV tKLQV ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 12 of 24 Q4 Q3 Q2 DQ tKLQX4 tKLQV tKLQX 03K4297.E35614 Revised 2/99 IBM04184AQLAD IBM04364AQLAD 128K x 36 & 256K x 18 SRAM Preliminary Timing Diagram (Read and Write Cycles) tKLKH tKHKH tKHKL K tAVKH SA A2 A1 tSVKH A2 A3 A4 tKHAX SS tKHSX tKHWX tKHWX SW tWVKH tWVKH tKHWX tKHWX SBW tWVKH tWVKH tKLQV G tGHQZ DQ tKHQZ tKLQX4 Q1 D2 tKHQV Q3 tKHQZ D4 Q2 tKHDX tKHQV tDVKH tDVKH tKHDX NOTES: 1. D2 is the input data written in memory location A2. 2. Q2 is output data read from the write buffer, as a result of address A2 being a match from the last write cycle address. 03K4297.E35614 Revised 2/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 13 of 24 IBM04184AQLAD IBM04364AQLAD 128K x 36 & 256K x 18 SRAM Preliminary Timing Diagram (Sleep Mode) tKHKH K ZZ tZZR tZZE DQ ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 14 of 24 03K4297.E35614 Revised 2/99 IBM04184AQLAD IBM04364AQLAD 128K x 36 & 256K x 18 SRAM Preliminary IEEE 1149.1 Tap and Boundary Scan The SRAM provides a limited set of JTAG functions intended to test the interconnection between SRAM I/Os and printed circuit board traces or other components. There is no multiplexer in the path from I/O pins to the RAM core. In conformance with IEEE std. 1149.1, the SRAMs contain a TAP controller, Instruction register, Boundary Scan register, Bypass register and ID register. The TAP controller has a standard 16-state state machine that resets internally upon power-up, therefore, TRST signal is not required. Signal List • • • • TCK: TMS: TDI: TDO: Test Clock Test Mode Select Test Data In Test Data Out Caution: TCK, TMS, TDI inputs must be biased down, even if JTAG is not used. TCK tied off will not allow any data to be clocked in, however. JTAG Recommended DC Operating Conditions (TA=0 to 85°C) Parameter Symbol Min. Typ. Max. Units Notes JTAG Input High Voltage VIH1 2.2 — VDD+0.3 V 1 JTAG Input Low Voltage VIL1 -0.3 — 0.8 V 1 JTAG Output High Level VOH1 2.4 — — V 1, 2 JTAG Output Low Level VOL1 — — 0.4 V 1, 3 1. All JTAG Inputs/Outputs are LVTTL Compatible only. 2. IOH1 = -8mA at 2.4V. 3. IOL1 = +8mA at 0.4V. JTAG AC Test Conditions (TA=20 to 85°C, VDD=3.3V ±5%) Symbol Conditions Units Input Pulse High Level Parameter VIH1 3.0 V Input Pulse Low Level VIL1 0.0 V Input Rise Time TR1 2.0 ns Input Fall Time TF1 2.0 ns 1.5 V Input and Output Timing Reference Level Notes 1 1. See AC Test Loading figure on page 10. 03K4297.E35614 Revised 2/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 15 of 24 IBM04184AQLAD IBM04364AQLAD 128K x 36 & 256K x 18 SRAM Preliminary JTAG AC Characteristics (TA=0 to 85°C, VDD=3.3V ±5%) Parameter Symbol Min. Max. Units TCK Cycle Time tTHTH 20 — ns TCK High Pulse Width tTHTL 7 — ns TCK Low Pulse Width tTLTH 7 — ns TMS Setup tMVTH 4 — ns tTHMX 4 — ns TDI Setup tDVTH 4 — ns TDI Hold tTHDX 4 — ns TCK Low to Valid Data tTLOV — 7 ns . TMS Hold Notes 1 1. See AC Test Loading figure on page 10. JTAG Timing Diagram tTHTL tTHTH tTLTH TCK tTHMX TMS tTHDX tMVTH TDI tDVTH TDO tTLOV ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 16 of 24 03K4297.E35614 Revised 2/99 IBM04184AQLAD IBM04364AQLAD 128K x 36 & 256K x 18 SRAM Preliminary Scan Register Definition Register Name Bit Size x18 Bit Size x36 Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan * 51 70 * The Boundary Scan chain consists of the following bits: • 36 or 18 bits for Data Inputs Depending on x18 or x36 Configuration • 17 bits for SA0 - SA16 for x36, 18 bits for SA0 - SA15 for x18 • 4 bits for SBWa - SBWd in x36, 2 bits for SBWa and SBWb in x18 • 9 bits for K, K, ZQ, SS, G, SW, ZZ, M1 and M2 • 4 bits for Place Holders * K and K clocks connect to a differential receiver that generates a single-ended clock signal. This signal and its inverted value are used for Boundary Scan sampling. ID Register Definition Field Bit Number and Description Part Revision Number (31:28) Device Density and Configuration (27:18) Vendor Definition (17:12) Manufacture JEDEC Code (11:1) Start Bit (0) 256K x 18 0001 011 100 1011 001000 000 101 001 00 1 128K x 36 0001 011 010 1100 001000 000 101 001 00 1 Instruction Set Code Instruction 000 SAMPLE-Z 001 IDCODE 010 SAMPLE-Z 011 PRIVATE 100 SAMPLE 101 PRIVATE 110 PRIVATE 111 BYPASS Notes 1, 5 2 1, 5 4, 5 3 1. Places DQs in High-Z in order to sample all input data regardless of other SRAM inputs. 2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data. 3. BYPASS register is initiated to VSS when BYPASS instruction is invoked. The BYPASS register also holds the last serially loaded TDI when exiting the Shift DR state. 4. SAMPLE instruction does not place DQs in High-Z. 5. SRAM must not be in Sleep mode (ZZ = H) when SAMPLE-Z or SAMPLE instructions are invoked. List of IEEE 1149.1 standard violations: • • • • 7.2.1.b, e 7.7.1.a-f 10.1.1.b, e 10.7.1.a-d 03K4297.E35614 Revised 2/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 17 of 24 IBM04184AQLAD IBM04364AQLAD 128K x 36 & 256K x 18 SRAM Preliminary Boundary Scan Order (x36) (PH =Place Holder) Exit Order Signal Bump # Exit Order Signal Bump # Exit Order Signal Bump # 1 M2 5R 25 DQ13 6F 49 DQ26 2H 2 SA1 4P 26 DQ11 7E 50 DQ25 1H 3 SA2 4T 27 DQ12 6E 51 SBWc 3G 4 SA12 6R 28 DQ9 7D 52 ZQ 4D 5 SA13 5T 29 DQ10 6D 53 SS 4E 6 ZZ 7T 30 SA14 6A 54 C=0 2 4G 7 DQ1 6P 31 SA15 6C 55 C=1 2 4H 8 DQ0 7P 32 SA10 5C 56 SW 4M 9 DQ3 6N 33 SA16 5A 57 SBWd 3L 10 DQ2 7N 34 PH1 6B 58 DQ34 1K 11 DQ4 6M 35 SA11 5B 59 DQ35 2K 12 DQ6 6L 36 SA8 3B 60 DQ32 1L 13 DQ5 7L 37 PH1 2B 61 DQ33 2L 14 DQ8 6K 38 SA7 3A 62 DQ31 2M 15 DQ7 7K 39 SA9 3C 63 DQ29 1N 16 SBWa 5L 40 SA6 2C 64 DQ30 2N 17 K 4L 41 SA5 2A 65 DQ27 1P 18 K 4K 42 DQ19 2D 66 DQ28 2P 19 G 4F 43 DQ18 1D 67 SA3 3T 20 SBWb 5G 44 DQ21 2E 68 SA4 2R 21 DQ16 7H 45 DQ20 1E 69 SA0 4N 22 DQ17 6H 46 DQ22 2F 70 M1 3R 23 DQ14 7G 47 DQ24 2G 24 DQ15 6G 48 DQ23 1G 1. Input of PH register connected to VSS. 2. Balls 4G and 4H are unused C Clock pins in this application ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 18 of 24 03K4297.E35614 Revised 2/99 IBM04184AQLAD IBM04364AQLAD 128K x 36 & 256K x 18 SRAM Preliminary Boundary Scan Order (x18) (PH =Place Holder) Exit Order Signal Bump # Exit Order Signal Bump # 1 M2 5R 27 PH1 2B 2 SA12 6T 28 SA7 3A 3 SA1 4P 29 SA9 3C 4 SA13 6R 30 SA6 2C 5 SA17 5T 31 SA5 2A 6 ZZ 7T 32 DQ9 1D 7 DQ0 7P 33 DQ12 2E 8 DQ3 6N 34 DQ15 2G 9 DQ6 6L 35 DQ16 1H 10 DQ7 7K 36 SBWb 3G 11 SBWa 5L 37 ZQ 4D 12 K 4L 38 SS 4E 13 K 4K 39 C=02 4G 14 G 4F 40 C=12 4H 15 DQ8 6H 41 SW 4M 16 DQ5 7G 42 DQ17 2K 17 DQ4 6F 43 DQ14 1L 18 DQ2 7E 44 DQ13 2M 19 DQ1 6D 45 DQ11 1N 20 SA14 6A 46 DQ10 2P 21 SA15 6C 47 SA3 3T 22 SA10 5C 48 SA4 2R 23 SA16 5A 49 SA0 4N 24 PH1 6B 50 SA2 2T 25 SA11 5B 51 M1 3R 26 SA8 3B 1. Input of PH register connected to VSS. 2. Balls 4G and 4H are unused C Clock pins in this application 03K4297.E35614 Revised 2/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 19 of 24 IBM04184AQLAD IBM04364AQLAD 128K x 36 & 256K x 18 SRAM Preliminary TAP Controller State Machine 1 Test Logic Reset 0 0 Run Test Idle 1 1 Select DR 0 0 1 1 Select IR 1 Capture IR Capture DR 0 0 Shift DR 0 Shift IR 0 1 1 1 1 Exit1 IR Exit1 DR 0 0 0 0 Pause DR Pause IR 1 1 Exit2 DR Exit2 IR 0 1 1 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 20 of 24 1 Update DR 0 0 Update IR 1 0 03K4297.E35614 Revised 2/99 IBM04184AQLAD IBM04364AQLAD 128K x 36 & 256K x 18 SRAM Preliminary 7 x 17 BGA Dimensions 20.32 0.84 REF (119X)∅ 0.89 ± 0.04 Solder Ball 0.035” ± 0.0015(mils) 7 6 3.19 REF 5 4 3 2 1 U T R P N M L K 7.62 1.27 J H G F E D C B A 22.00 16.764 14.00 12.7 REF 0.625±.254 Under fill Indicates A1 Location PLATE CHIP Structural Adhesive 0.1778 Ref Under fill PLATE 2.549 ± 0.13 0.701 ± 0.099 0.71 ± 0.05 Typ Note: All dimensions in Millimeters Unless Otherwise noted 03K4297.E35614 Revised 2/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 21 of 24 IBM04184AQLAD IBM04364AQLAD 128K x 36 & 256K x 18 SRAM Preliminary References Rev “D” - Last Character in Part Number (D) The following documents give recommendations, restrictions, and limitations for 2nd level attach process: C4 SRAM Assembly Guide for Single Sided Assembly Double Sided 4Meg Coupled Cap PBGA Card Assembly Guide Qualification information, including scope of application conditions qualified, is available from your marketing representative. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 22 of 24 03K4297.E35614 Revised 2/99 IBM04184AQLAD IBM04364AQLAD 128K x 36 & 256K x 18 SRAM Preliminary Revision Log Rev Contents of Modification 9/97 Initial Release 11/97 Added -5P sort. 5/98 Updated -5P sort. Added Tri-state timing test definition. 6/98 Updated AC input data. Changed Programmable Impedance tolerance to ±15% and 2080 max cycle update. Changed Rev B to Rev D. Added references for Rev D and changed package diagram. Added Sleep mode statement. Updated mode pins. Minor boundary scan update. 2/99 Tightened the BGA ball diameter tolerance. 03K4297.E35614 Revised 2/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 23 of 24 International Business Machines Corp.1999 Copyright Printed in the United States of America All rights reserved IBM and the IBM logo are registered trademarks of the IBM Corporation. This document may contain preliminary information and is subject to change by IBM without notice. IBM assumes no responsibility or liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. 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