ETC IP101

IP101
Single port 10/100 Fast Ethernet Transceiver
1.0 Features
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2.0 General Description
10/100Mbps TX/FX
Full-duplex or half-duplex
Supports Auto MDI/MDIX function
Fully compliant with IEEE 802.3/802.3u
Supports IEEE 802.3u auto-negotiation
Supports MII / RMII / SNI interface
IEEE 802.3 full duplex control specification
Supports Automatic Power Saving mode
Supports
BaseLine
Wander
(BLW)
compensation
Supports Interrupt function
Supports repeater mode
Single 3.3V power supply with built-in 2.5V
regulator
DSP-based PHY Transceiver technology
Using either 25MHz crystal or 50MHz
REF_CLK as clock source
Flexible LED display for speed, duplex, link,
activity and collision
Supports flow control to communicate with
other MAC through MDC and MDIO
0.25u, CMOS technology
48-pin LQFP
Copyright © 2003, IC Plus Corp.
Confidential, All rights reserved.
Advanced, Specification subject to change without notice
IP101 is an IEEE 802.3/802.3u compliant single-port
Fast Ethernet Transceiver for both 100Mbps and
10Mbps operations. It supports Auto MDI/MDIX
function to simplify the network installation and reduce
the system maintenance cost. To improve the system
performance, IP101 provides a hardware interrupt pin
to indicate the link, speed and duplex status change.
IP101 also provides Media Independent Interface (MII)
/ Serial Network Interface (SNI) or Reduced Media
Independent Interface (RMII) to connect with different
types of 10/100Mb Media Access Controller (MAC).
IP101 is designed to use category 5 unshielded
twisted-pair cable or Fiber-Optic cables connecting to
other LAN devices. A PECL interface is supported to
connect with an external 100Base-FX fiber optical
transceiver.
IP101 Transceiver is fabricated with advanced CMOS
technology, which the chip only requires 3.3V as
power supply and consumes very low power in the
Auto Power Saving mode. IP101 can be implemented
as Network Interface Adapter with RJ-45 for
twisted-pair connection or MAU for Fiber Connection.
It can also be easily implemented into HUB, Switch,
Router, Access Point, Advanced Communication
Riser (ACR) and Communication and Networking
Riser (CNR).
1 / 33
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IP101-DS-R0.02
Feb. 24, 2003
IP101
3.0 Transmit and Receive Data Path Block Diagram
MII/SNI/
RMII
Interface
TXD
100Mbps
4B/5B
Encoder
RXD
100Mbps
10Mbps
4B/5B
Decoder
10Mbps
Serial to
Parallel
100Mbps
100Mbps
MII Registers
10Mbps
FX
Descrambler
Machester/
NRZ
Decoder
Scrambler
100Mbps
5B
FX
Serial to
Parallel
100Mbps
5B
10Mbps
AutoNegotiation
Mux
Clock
Recovery
100Mbps
100Mbps
Clock
Recovery
10Mbps
Parallel to
Serial
100Mbps
Parallel to
Serial
MLT3/NRZI
Decoder
100Mbps
FX
10Mbps
NRZI/MLT-3
Encoder
NRZ/
Manchester
Encoder
100Mbps
10Mbps
FX
Squelch
100Mbps
DSP Engine
10Mbps
100Mbps
10Mbps
D/A & Line Driver
TXO
RJ-45
Connector
RXI
Figure 1: Flow chart of IP101
Copyright © 2003, IC Plus Corp.
Confidential, All rights reserved.
Advanced, Specification subject to change without notice.
2 / 33
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IP101-DS-R0.02
Feb. 24, 2003
IP101
25. MDC
26. MDIO
27. TEST_ON
28. RTSET
29. AGND
30. MDI_RN
31. MDI_RP
32. REGOUT
33. MDI_TN
34. MDI_TP
35. AGND
36. AVDD33
4.0 Pin Assignments
37. AN_ENA
24. RX_ER
/FIBMOD
38. DPLX
23. CRS
/LEDMOD
39. SPD
22. RX_DV
/CRS_DV
40. RPTR
21. RXD0
41. APS
20. RXD1
42. RESET_N
19. RXD2
IP101
43. ISOL
18. RXD3
Fast Ethernet Single Phy Transceiver Chip
48 pins LQFP package
44. MII_SNIB
17. DGND
12. LED2/
PHYAD2
11. DGND
10. LED1/
PHYAD1
9. LED0/
PHYAD0
8. REGIN
13. LED3/
PHYAD3
7. TX_CLK/
REF_CLK
48. INTR
6. TXD0
14. DVDD33
5. TXD1
47. X2
4. TXD2
15. LED4/
PHYAD4
3. TXD3
46. X1
2. TX_EN
16. RX_CLK
1. COL
/RMII
45. DGND
Figure 2 : IP101 pins assignment
IP101-DS-R0.02
Feb. 24, 2003
3 / 33
Copyright © 2003, IC Plus Corp.
Confidential, All rights reserved.
Advanced, Specification subject to change without notice.
NOT APPROVED BY TECHNICAL DOCUMENT CONTROL
IP101
5.0 Pin Descriptions
Type
LI
I/O
Description
Type
Description
Latched Input in power up or reset
PD
Internal Pull-Down
Bi-directional input and output
PU
Internal Pull-Up
I
Input
O
Output
Pin no.
P
OD
Label
Type
Power
Open Drain
Description
MII and PCS Interface - Management Interface Pins
25
MDC
I
26
MDIO
I/O
Management Data Interface Clock: This pin provides a clock
reference to MDIO. The clock rate can be up to 10MHz.
Management Data interface Input/Output: The function of this
pin is to transfer management information between PHY and
MAC.
MII and PCS Interface – Media Independent Interface (MII) Pins
2
TX_EN
I
(PD)
Transmit Enable: This pin is an active high input. At high status,
it indicates the nibble data in TXD[3:0] is valid.
7
TX_CLK
O
Transmit Clock: This pin provides a continuous 25MHz clock at
100Mbps and 2.5Mbps as timing reference for TXD[3:0] and
TX_EN when the chip operates under MII and SNI modes. This
pin is an input pin operates as RMII reference clock (REF_CLK)
under RMII mode.
3, 4, 5, 6
TXD[3:0]
I
Transmit Data: When TX_EN is set low, MAC will transmit data
through these 4 lines to PHY which the transmission is
synchronizing with TX_CLK.
22
RX_DV
O
Receive Data Valid: At high status stands for data flow is present
within RXD[0:3] lines and low means no data exchange occurred.
16
RX_CLK
O
Receive Clock: This pin provides 25MHz for 100Mbps
transmission or 2.5Mhz for 10Mbps transmission and RX_DV pin
uses this pin as its reference under MII or SNI mode. While under
RMII mode this pin is driven low.
18, 19,
20, 21
RXD[3:0]
O
Receive Data: These 4 data lines are transmission path for PHY
to send data to MAC and they are synchronizing with RX_CLK.
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Advanced, Specification subject to change without notice.
4 / 33
NOT APPROVED BY TECHNICAL DOCUMENT CONTROL
IP101-DS-R0.02
Feb. 24, 2003
IP101
5.0 Pin Descriptions (continued)
Pin no.
Label
Type
Description
MII and PCS Interface – Media Independent Interface (MII) Pins
24
RX_ER/
FIBMOD
O/LI
(PD)
Receive error: This pin outputs a high status when errors
occurred in the decoded data in the transmission.
Fiber Mode: During power on reset, this pin status is latched to
determine at which media mode to operate:
1: Fiber mode
0: UTP mode
An internal weak pull low resistor sets this to the default of UTP
mode. It is possible to use an external 5.1KΩpull high resistor to
enable fiber mode.
After power on, the pin operates as the Receive Error pin.
1
COL/RMII
O/LI
(PD)
Collision Detected: When this pin outputs a high status signal it
means collision is detected.
RMII Mode: During power on reset, this pin status is latched and
arranged with MII/SNIB (pin44) to determine MAC interface
RMII MII/SNIB
1
X
RMII Interface
0
1
MII Interface
0
0
SNII Interface
(Notice: This pin is pulled down internally)
CRS/LEDMOD
O
(PD)
Carrier Sense: When signal output from this pin is high indicates
the transmission is in process and at low status means the line is
in idle state.
LEDMOD: During power on reset, this pin status is latched to
determine at which LED mode to operate, please refer to the LED
pins description.
(Notice: This pin is pulled down internally)
23
RMII (Reduced MII)
7
REF_CLK
2
TX_EN
I
I
(PD)
Reference Clock: This pin is an input pin operates as RMII
reference clock (REF_CLK) under RMII mode. 25MHz Crystal
Input and Output, X1 & X2, should be disconnected when
REF_CLK is used as the clock source of IP108.
Transmit Enable: For MAC to indicate transmit operation
5,6
TXD[1:0]
I
24
RX_ER
I/O
22
CRS_DV
O
Carrier Sense and Receive Data Valid
20, 21
RXD[1:0]
O
Received two-bit Data
IP101-DS-R0.02
Feb. 24, 2003
Transmit two-bit Data
Receive Error
5 / 33
Copyright © 2003, IC Plus Corp.
Confidential, All rights reserved.
Advanced, Specification subject to change without notice.
NOT APPROVED BY TECHNICAL DOCUMENT CONTROL
IP101
5.0 Pin Descriptions (continued)
Pin no.
Label
Type
Description
SNI (Serial Network Interface): 10Mbps only
2
TX_EN
I
(PD)
Transm it Enable: Indicate transmit operation to MAC
7
TX_CLK
O
Transmit Clock: 10MHz, generate either by PHY or by external
6
TXD0
I
Transmit Serial Data
16
RX_CLK
O
Receive Clock: 10MHz, clock recovery from received data
21
RXD0
O
Received Serial Data
1
COL
O
Collision Detect
23
CRS
O
Carrier Sense
Cable Transmission Interface
34
33
MDI_TP
MDI_TN
O
O
Transmit Output Pair: Differential pair shared by 100Base-TX,
100Base-FX and 10Base-T modes. When configured as
100Base-TX, output is an MLT-3 encoded waveform. When
configured as 100Base-FX, the output is pseudo-ECL level.
31
30
MDI_RP
MDI_RN
I
I
Receive Input Pair: Differential pair shared by 100Base-TX,
100Base-FX, and 10Base-T modes.
IC Configuration Options
43
ISOL
I
(PD)
Set high to this pin will isolate IP101 from other MAC. This action
will also isolate the MDC/MDIO management interface. The
power usage is at minimum when this pin is activated. This pin
can be directly connected to GND or VCC. (An internal weak
pulled-down is used to be inactive as a default)
40
RPTR
I
(PD)
Enable this pin to high will put the IP101 into repeater mode. This
pin can be directly connected to GND or VCC. (An internal weak
pulled-down is used to be inactive as a default)
39
SPD
LI/O
(PU)
This pin is latched to input during a power on or reset condition.
Set high to put the IP101 into 100Mbps operation. This pin can be
directly connected to GND or VCC. (An internal weak pulled-up is
used to set 100Mbps as a default)
38
DPLX
LI/O
(PU)
This pin is latched to input during a power on or reset condition.
Set high to enable full duplex. This pin can be directly connected
to GND or VCC. (An internal weak pulled-up is used to set full
duplex as a default)
37
AN_ENA
LI/O
(PU)
This pin is latched to input during a power on or reset condition. Set
high to enable auto-negotiation mode, set low to force mode. This
pin can be directly connected to GND or VCC. (An internal weak
pulled-up is used to enable N-WAY as a default)
41
APS
I
(PU)
Set high to put the IP101 into APS mode. This pin can be directly
connected to GND or VCC. Refer to Section 7.7 for more
information. (An internal weak pulled-up is used to enable APS
mode as a default)
44
MII_SNIB
LI/O
(PU)
This pin is latched to input during a power on or reset condition.
Pull high to set the IP101 into MII mode operation. Set low for SNI
mode. This pin can be directly connected to GND or VCC. (An
internal weak pulled-up is used to set MII mode as a default)
Copyright © 2003, IC Plus Corp.
Confidential, All rights reserved.
Advanced, Specification subject to change without notice.
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NOT APPROVED BY TECHNICAL DOCUMENT CONTROL
IP101-DS-R0.02
Feb. 24, 2003
IP101
5.0 Pin Descriptions (continued)
Pin no.
Label
Type
Description
LED and PHY Address Configuration
These five pins are latched into the IP101 during power up reset to configure PHY address [0:4] used for MII
management register interface. And then, in normal operation after initial reset, they are used as driving pins for
status indication LED. The driving polarity, active low or active high, is determined by each latched status of the
PHY address [4:0] during power-up reset. If latched status is high then it will be active low, and if latched status is
nd
Low then it will be active high. Moreover, IP101 provides 2 LED modes. If 2 LED mode is selected by pulling up
pin CRS, only 3 LEDs are needed for status indication. Default is first LED mode.
LED mode 1
LED mode 2
LED0
LINK
LINK /ACT(blinking)
LED1
FULL DUPLEX
FULL DUPLEX /COL(blinking)
LED2
10BT /ACT(blinking)
10BT
LED3
100BT /ACT(blinking)
100BT
LED4
COL
9
PHYAD0/
LED0
LI/O
PHY Address [0]
Status:
Mode1: Active when linked.
Mode2: Active when linked and blinking when transmitting or
receiving data.
10
PHYAD1/
LED1
LI/O
PHY Address [1]
Status:
Mode1: Active when in Full Duplex operation.
Mode2: Active when in Full Duplex operation and blinking when
collisions occur.
12
PHYAD2/
LED2
LI/O
PHY Address [2]
Status:
Mode1: Active when linked in 10Base-T mode, and blinking when
transmitting or receiving data.
Mode2: Active when linked in 10Base-T mode.
13
PHYAD3/
LED3
LI/O
PHY Address [3]
Status:
Mode1: Active when linked in 100Base-TX and blinking when
transmitting or receiving data.
Mode2: Active when linked in 100Base-TX mode.
15
PHYAD4/
LED4
LI/O
PHY Address [4]
Status:
Mode1: Active when collisions occur.
Mode2: Reserved.
Clock and Miscellaneous - Crystal Input/Output Pins
47
X2
O
25MHz Crystal Output: Connects to crystal to provide the
25MHz output. It must be left open when X1 is driven with an
external 25MHz oscillator. It must be left open when X1 is driven
with an external 25MHz oscillator or set to low with a pull down
resistor.
46
X1
I
25MHz Crystal Input: Connects to crystal to provide the 25MHz
crystal input. If a 25MHz oscillator is used, connect X1 to the
oscillator’s output. If X1 is set to low with a pull down resistor, a
50MHz clock could be applied to pin7 as clock source.
IP101-DS-R0.02
Feb. 24, 2003
7 / 33
Copyright © 2003, IC Plus Corp.
Confidential, All rights reserved.
Advanced, Specification subject to change without notice.
NOT APPROVED BY TECHNICAL DOCUMENT CONTROL
IP101
5.0 Pin Descriptions (continued)
Pin no.
Label
Type
Description
Clock and Miscellaneous - Miscellaneous Pins
42
RESET_N
I
RESET_N: Enable a low status signal will reset the chip. For a
complete reset function, this pin must be asserted low for at least
10ms.
48
INTR
I/O
(OD)
Interrupt Pin: When the MII register 17:<15> is set to high, this
pin is used as an interrupt pin (Notice: this is an open drain output,
so an external pulled-up resistor is needed)
27
TEST_ON
(PD)
Test Enable: Set this pin to high to enable test mode, while for
normal operation, this pin does not need to be connected. (An
internal weak pulled-down is used to disable test mode as a
default)
28
ISET
I
Transmit Bias Resistor Connection: This pin should be
connected to GND via a 6.2KO (1%) resistor to define driving
current for transmit DAC. The resistance value may be changed,
depending on experimental results of the IP101.
Power and Ground
32
REGOUT
P
Regulator Power Output: This is a regulator power output for
IP101 digital circuitry.
36
AVDD33
P
3.3V Analog power input: This is a 3.3V power supply for analog
circuitry, and it should be decoupled carefully.
29,35
AGND
P
Analog Ground: These 2 pins should connect to motherboard’s
GND.
8
REGIN
P
Regulator Power Input: This is a regulator power input from
Pin32. No external regulator needed.
DVDD33
P
3.3V Digital Power input: This is a 3.3V power supply for digital
circuitry.
DGND
P
Digital Ground: These 3 pins should connect to motherboard’s
GND.
14
11,17,45
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NOT APPROVED BY TECHNICAL DOCUMENT CONTROL
IP101-DS-R0.02
Feb. 24, 2003
IP101
6.0 Register Descriptions
This section will explain the meaning and usage for each of the registers available in the IP101.
The first 7 registers, i.e., Register 0 to Register 6, are defined according to IEEE 802.3 standard, while the rest
registers are defined by IC Plus Corp. and they are for internal use or reserved for other usage.
The first 2 registers contain the basic control and status register defined by IEEE standard.
Each register has its own default value, and it is placed in the right block of each register title.
Register 0 : MII Control Register
Default value (h):
3100
Address
Name
Description/Usage
15
Reset
When set, this action will bring both status and control registers
of the PHY to default state. This bit is self-clearing.
1 = Software reset
0 = Normal operation
0, RW
14
Loop-back
This bit enables loop-back of transmit data to the receive data
path, i.e., TXD to RXD.
1 = enable loop-back
0 = normal operation
0, RW
13
Speed
Selection
This bit sets the speed of transmission.
1 = 100Mbps
0 = 10Mbps
During 100Base-FX mode, and when this bit = 1, it indicates
read only.
1, RW
12
AutoNegotiation
Enable
This bit determines the auto-negotiation function.
1 = enable auto-negotiation; bits 13 and 8 will be ignored.
0 = disable auto-negotiation; bits 13 and 0:<8> will determine
the link speed and the data transfer mode, under this condition.
When 100Base-FX mode is enabled, and this bit=0, it indicates
read only.
1, RW
11
Power Down
This bit will turn down the power of the PHY chip and the
internal crystal oscillator circuit if this bit is enabled. The MDC
and MDIO are still activated for accessing to the MAC.
1 = power down
0 = normal operation
0, RW
10
Isolate
1=electrically Isolate PHY from MII but not isolate MDC and MDIO
0=normal operation
0,RW
9
Restart AutoNegotiation
This bit allows the Nway auto-negotiation function to be reset.
1 = restart auto-negotiation
0 = normal operation
0, RW
8
Duplex Mode
This bit sets the duplex mode if auto-negotiation is disabled (bit
12=0)
1 = full duplex
0 = half duplex
After completing auto-negotiation, this bit will reflect the duplex
status.(1: Full duplex, 0: Half duplex)
When 100Base-FX mode is enabled, this bit can be set
through the MDC/MDIO SMI interface or DUPLEX pin.
1, RW
7
Collision Test
1=enable COL signal test
0=disable COL signal test
0,RW
6:0
Reserved
IP101-DS-R0.02
Feb. 24, 2003
9 / 33
Copyright © 2003, IC Plus Corp.
Confidential, All rights reserved.
Advanced, Specification subject to change without notice.
NOT APPROVED BY TECHNICAL DOCUMENT CONTROL
IP101
6.0 Register Descriptions (continued)
Register 1 : MII Status Register
Description/Usage
Default value (h):
7849
Address
Name
15
100Base-T4
1 = enable 100Base-T4 support
0 = suppress 100Base-T4 support
0, RO
14
100Base-TX
Full Duplex
1 = enable 100Base-TX full duplex support
0 = suppress 100Base-TX full duplex support
1, RO
13
100BASE-TX
Half Duplex
1 = enable 100Base-TX half duplex support
0 = suppress 100Base-TX half duplex support
1, RO
12
10Base-T Full
Duplex
1 = enable 10Base-T full duplex support
0 = suppress 10Base-T full duplex support
1, RO
11
10_Base-T
Half Duplex
1 = enable 10Base-T half duplex support
0 = suppress 10Base-T half duplex support
1, RO
10:7
Reserved
6
MF Preamble
Suppression
5
AutoNegotiation
Complete
4
Remote Fault
3
AutoNegotiation
1 = Link had not been experienced fail state
0 = Link had been experienced fail state
2
Link Status
1 = valid link established
0 = no valid link established
0, RO/LL
1
Jabber Detect
1 = jabber condition detected
0 = no jabber condition detected
0, RO/LH
0
Extended
Capability
1 = extended register capability
0 = basic register capability only
1, RO
0, RO
The IP101 will accept management frames with preamble
suppressed. The IP101 accepts management frames without
preamble. A Minimum of 32 preamble bits are required for the
first SMI read/write transaction after reset. One idle bit is
required between any two management transactions as per
IEEE802.3u specifications
1, RO
1 = auto-negotiation process completed
0 = auto-negotiation process not completed
0, RO
1 = remote fault condition detected (cleared on read)
0 = no remote fault condition detected
When in 100Base-FX mode, this bit means an in-band signal
Far-End-Fault is detected.
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Advanced, Specification subject to change without notice.
10 / 33
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0, RO/LH
1, RO
IP101-DS-R0.02
Feb. 24, 2003
IP101
6.0 Register Descriptions (continued)
Register 2 : PHY Identifier Register 1
Address
Name
15:0
PHYID1
Description/Usage
PHY identifier ID for software recognize IP101
Default value (h):
0243
0X0243, RO
Register 3 : PHY Identifier Register 2
Address
Name
15:0
PHYID2
Description/Usage
PHY identifier ID for software recognize
Default value (h):
0C50
0X0C50, RO
Note : Register 2 and register 3 identifier registers altogether consist of Vender model, model revision number and
Organizationally Unique identifier (OUI) information. Total of 32 bits allocate in these 2 registers and they can
return all zeroes in all bits if desired. Register 2 contains OUI’s most significant bits and OUI’s lest significant bits,
Vender model, Model revision number are allocated in register 3.
IP101-DS-R0.02
Feb. 24, 2003
11 / 33
Copyright © 2003, IC Plus Corp.
Confidential, All rights reserved.
Advanced, Specification subject to change without notice.
NOT APPROVED BY TECHNICAL DOCUMENT CONTROL
IP101
6.0 Register Descriptions (continued)
Register 4 lists the advertised abilities during auto-negotiation for what will be transmitted to IP101’s Link Partner.
Register 4 : Auto-Negotiation Advertisement Register
Address
Name
15
NP
14
Reserved
13
RF
12
Reserved
11
Asymmetric.
Pause
10
Pause
9
T4
8
TX Full
Duplex
7
TX
6
10 Full
Duplex
5
10
4:0
Selector
Description/Usage
Next Page bit.
0 = transmitting the primary capability data page
1 = transmitting the protocol specific data page
Default value (h):
0001
0, RO
0, RO
1 = advertise remote fault detection capability
0 = do not advertise remote fault detection capability
0, RW
0, RO
1 = asymmetric flow control is supported by local node
0 = asymmetric flow control is NOT supported by local node
0, RW
1 = flow control is supported by local node
0 = flow control is NOT supported by local node
0, RW
1 = 100Base-T4 is supported by local node
0 = 100Base-T4 not supported by local node
0, RO
1 = 100Base-TX full duplex is supported by local node
0 = 100Base-TX full duplex not supported by local node
1, RW
1 = 100Base-TX is supported by local node
0 = 100Base-TX not supported by local node
1, RW
1 = 10Base-T full duplex supported by local node
0 = 10Base-T full duplex not supported by local node
1, RW
1 = 10Base-T is supported by local node
0 = 10Base-T not supported by local node
1, RW
Binary encoded selector supported by this node. Currently
only CSMA/CD <00001> is specified. No other protocols are
supported.
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Advanced, Specification subject to change without notice.
12 / 33
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<00001>, RO
IP101-DS-R0.02
Feb. 24, 2003
IP101
6.0 Register Descriptions (continued)
Register 5 describes the advertised abilities of the Link Partner’s PHY when it is receiving data during the process of
auto-negotiation. If next-pages are supported, this register may change after the auto-negotiation has established.
Register 5 : Auto-Negotiation Link Partner Ability Register
Address
Name
15
Next Page
14
Description/Usage
Default value (h):
0080
Next Page bit.
0 = transmitting the primary capability data page
1 = transmitting the protocol specific data page
0, RO
Acknowledge
1 = link partner acknowledges reception of local node’s
capability data word
0 = no acknowledgement
0, RO
13
Remote Fault
1 = link partner is indicating a remote fault
0 = link partner does not indicate a remote fault
0, RO
12
Reserved
11
Asymmetric.
Pause
10
Pause
9
T4
8
TXFD
7
100BASE-TX
6
10FD
5
4:0
IP101-DS-R0.02
Feb. 24, 2003
0, RO
1 = asymmetric flow control is supported by local node
0 = asymmetric flow control is NOT supported by local node
0, RO
1 = flow control is supported by Link partner
0 = flow control is NOT supported by Link partner
0, RO
1 = 100Base-T4 is supported by link partner
0 = 100Base-T4 not supported by link partner
0, RO
1 = 100Base-TX full duplex is supported by link partner
0 = 100Base-TX full duplex not supported by link partner
0, RO
1 = 100Base-TX is supported by link partner
0 = 100Base-TX not supported by link partner
This bit will also be set after the link in 100Base is established
by parallel detection.
1, RO
1 = 10Base-T full duplex is supported by link partner
0 = 10Base-T full duplex not supported by link partner
0, RO
10Base-T
1 = 10Base-T is supported by link partner
0 = 10Base-T not supported by link partner
This bit will also be set after the link in 10Base is established
by parallel detection.
0, RO
Selector
Link Partner’s binary encoded node selector Currently only
CSMA/CD <00001> is specified
13 / 33
<00000>, RO
Copyright © 2003, IC Plus Corp.
Confidential, All rights reserved.
Advanced, Specification subject to change without notice.
NOT APPROVED BY TECHNICAL DOCUMENT CONTROL
IP101
6.0 Register Descriptions (continued)
Register 6 defines more auto-negotiation registers to meet the requirement.
Register 6 : Auto-Negotiation Expansion Register
Address
Name
15:5
Reserved
4
MLF
3
LP_NP_ABLE
2
Description/Usage
Default value (h):
0000
This bit is always set to 0.
This status indicates if a multiple link fault has occurred.
1 = fault occurred
0 = no fault occurred
0, RO
This status indicates if the link partner supports Next Page
negotiation.
1 = supported
0 = not supported
0, RO
NP_ABLE
This bit indicates if the device is able to send additional Next
Pages.
0, RO
1
PAGE_RX
This bit will be set if a new link code word page has been
received. It is cleared automatically after the auto-negotiation
link partner’s ability register (register 5) is read by the
management.
0, RO
0
LP_NW_ABLE
1 = link partner supports Nway auto-negotiation.
0, RO
Copyright © 2003, IC Plus Corp.
Confidential, All rights reserved.
Advanced, Specification subject to change without notice.
14 / 33
NOT APPROVED BY TECHNICAL DOCUMENT CONTROL
IP101-DS-R0.02
Feb. 24, 2003
IP101
6.0 Register Descriptions (continued)
Register 16 and register 17 are defined by IC Plus Corp. and it is for internal testing purpose.
Register 16 : PHY Spec. Control Register
Address
Name
15
Debug Mode
14:12
Reserved
11
Description/Usage
Default value (h):
0000
0 = IP101 operates at normal mode
1 = IP101 operates at debug mode
(Notice the functionalities of bit 16:<14>, 16:<13>, 16:<12>,
and 16:<4:0> depend on the setting of this bit 16:<15>
0, R/W
MDI disable
Set high to disable the automatic switch of MDI and MDI-X
modes
0, R/W
10
Heart Beat
Enable
Heart beat function enable at 10Base-T
0, R/W
9
Jabber
Enable
Jabber function enable at 10Base-T
0, R/W
Far-End Fault To enable or disable the functionality of Far-End Fault
Enable/Disable Mode
Enable
Disable
100Base-TX
1
0
100Base-FX
0
1
0, R/W
8
7
Analog
Power Saving
Disable
6
Reserved
5
Bypass DSP
reset
4:3
Reserved
2
Repeater
Mode
1
0
IP101-DS-R0.02
Feb. 24, 2003
Set high to disable the power saving during auto-negotiation
0, R/W
0, R/W
Set high to bypass the reset DSP mechanism in PCS
sub-layer
0, R/W
Set high to put IP101 into repeater mode
0, R/W
APS Mode
Set high to enable Auto Power Saving mode
0, R/W
Analog Off
Set high to power down analog transceiver
0, R/W
15 / 33
Copyright © 2003, IC Plus Corp.
Confidential, All rights reserved.
Advanced, Specification subject to change without notice.
NOT APPROVED BY TECHNICAL DOCUMENT CONTROL
IP101
6.0 Register Descriptions (continued)
Register 17 : PHY Interrupt Ctrl/Status Register
Address
Name
15
INTR pin
used
14:12
Reserved
11
All Mask
10
Description/Usage
Default value (h):
0E00
Set high to enable pin48 as an interrupt pin, or high
impedance is presented at this pin
0, R/W
When this bit is set high, changes in all events will not cause
an interrupt
1, R/W
Speed Mask
When this bit is set high, changes in speed mode will not
cause an interrupt
1, R/W
9
Duplex Mask
When this bit is set high, changes in duplex mode will not
cause an interrupt
1, R/W
8
Link Mask
When this bit is set high, changes in link status will not cause
an interrupt
1, R/W
7
Arbiter State
Enable
When this bit is set high, changes in N-WAY arbiter state
machine will cause an interrupt
0, R/W
6
Arbiter State
Change
Flag to indicate N-WAY arbiter change interrupt
0, R/W
5:3
Reserved
2
Link Status
Change
1
0
0, R/W
Flag to indicate link status change interrupt
0, R/W
Speed
Change
Flag to indicate speed change interrupt
0, R/W
Duplex
Change
Flag to indicate duplex change interrupt
0, R/W
Copyright © 2003, IC Plus Corp.
Confidential, All rights reserved.
Advanced, Specification subject to change without notice.
16 / 33
NOT APPROVED BY TECHNICAL DOCUMENT CONTROL
IP101-DS-R0.02
Feb. 24, 2003
IP101
7.0 Functional Description
IP101 10/100Mbps Ethernet PHY Transceiver
integrates 100 Base-TX, 100 Base-FX and 10 Base-T
modules into a single chip. IP101 acts as an interface
between physical signaling and Media Access
Controller (MAC).
IP101 has several major functions:
1. PCS layer (Physical Coding Sub-Layer): This
function contains transmit, receive and carrier
sense functional circuitries.
2. Management interface: Media Independent
Interface (MII) or Reduced Management Interface
(RMII)
registers
contains
information
for
communication with other MAC.
3. Auto-Negotiation: Communication conditions
between 2 PHY transceivers. IP101 advertise its
own ability and also detects corresponding
operational mode from the other party, eventually
both sides will come to an agreement for their
optimized transmission mode.
IP101’s major features included:
1. Flow Control ability
2. LED configuration access
3. Operation modes for both full and half duplex
4. APS (Auto Power Saving) mode
5. Base Line Wander (BLW) compensation
6. Auto MDI/MDIX function
7. Interrupt function
8. Repeater Mode
(5B) data is decoded into four bits nibble data. The
decoded 4 bit (4B) data is then forwarded through
MII to the repeater, switch or MAC device. The SSD
is then converted into 4B 5 nibbles and the ESD
and IDLE Codes are replaced by 4B 0 nibbles data.
The decoded data is driven onto the corresponding
MII port or shared MII port. Receiving an invalid
code group will cause PHY to assert the MII RXER
signal.
3.
Scrambler/Descrambler: Repetitive patterns exist
in 4B/5B encoded data which result in large RF
spectrum peaks and keep the system from being
approved by regulatory agencies. The peak in the
radiated signal is reduced significantly by
scrambling the transmitted signal. Scrambler adds
a random generator to the data signal output. The
resulting signal is with fewer repetitive data
patterns. The scrambled data stream is
descrambled at the receiver by adding another
random generator to the output. The receiver’s
random generator has the same function as the
transmitter’s
random
generator.
Scrambler
operation is dictated by the 100Base-X and
TP_FDDI standards.
4.
NRZI/MLT-3(Manchester) Encoder and Decoder:
100 Base-TX Transmission requires to encode the
data into NRZ format and again converted into
MLT-3 signal, while 10 Base-T will convert into
Manchester form after NRZ coding. This helps to
remove the high frequency noise generated by the
twisted pair cables. At receiving end, the coding is
reversed from MLT-3 (Manchester) signal back to
NRZ format.
5.
Clock Recovery: The receiver circuit recovers
data from the input stream by regenerating clocking
information embedded in the serial stream. The
clock recovery block extracts the RXCLK from the
transition of received
6.
DSP Engine: This block includes Adaptive
equalizer and Base Line Wander correction
function.
Major Functional Block Description
The functional blocks diagram is referred to Figure 1:
1.
2.
4B/5B encoder: 100 Base-X transmissions require
converting 4-bit nibble data into 5-bit wide data
code-word format. Transmitting data is packaged
by J/K codes at the start of packet and by T/R
codes at the end of packet in the 4B/5B block.
When transmit error has occurred during a
transmitting process, the H error code will be sent.
The idle code is sent between two packets.
4B/5B Decoder: The decoder performs the 5B/4B
decoding from the received code-groups. The 5 bits
IP101-DS-R0.02
Feb. 24, 2003
17 / 33
Copyright © 2003, IC Plus Corp.
Confidential, All rights reserved.
Advanced, Specification subject to change without notice.
NOT APPROVED BY TECHNICAL DOCUMENT CONTROL
IP101
Transmission Description
The scrambled data are descrambled and converted
back to 4 bits–wide format data and then feed into
MAC.
10Mbps Transmit flow path:
TXD g Parallel to Serial g NRZI/Manchester Encoder
g D/A & line driver g TXO
100Mbps FX Transmit:
After MAC passes data to PHY via 4 bits nibbles, the
data are serialized in the parallel to serial converter.
The converter outputs NRZI coded data which the data
are then mapped to Manchester code within the
Manchester Encoder. Before transmitting to the
physical medium, the Manchester coded data are
shaped by D/A converter to fit the physical medium.
TXD g 4B/5B Encoder g Parallel to Serial g D/A &
line driver g TXO
10Mbps Receive:
RXI g DSP (Clock Recovery) g Serial to Parallel g
4B/5B Decoder g RXD
RXI g Squelch g Clock Recovery g Manchester/NRZ
Decoder g Serial to Parallel g RXD
The squelch block determines valid data from both AC
timing and DC amplitude measurement. When a valid
data is present in the medium, squelch block will
generate a signal to indicate the data has received. The
data receive are coded in Manchester form, and are
decoded in the Manchester to NRZ Decoder. Then the
data are mapped to 4 bits nibbles and transmitted onto
MAC interface.
100Mbps TX Transmit:
TXD g 4B/5B Encoder g Scrambler g NRZI/MLT-3
Encoder g D/A & line driver g TXO
The major differences between 10Mbps transmission
and 100Mbps transmission are that 100Mbps
transmission requires to be coded from 4-bit wide
nibbles to 5 bits wide data coding, and after that the
data are scrambled through scrambler to reduce the
radiated energy generated by the 4B/5B conversion.
Then the data is converted into NRZI form and again
from NRZI coded form into MLT-3 form. The MLT-3
data form is fed into D/A converter and shaped to fit the
physical medium transmission.
100Mbps TX Receive:
RXI g DSP g Serial to Parallel g Descrambler g
4B/5B Decoder g RXD
The received data first go through DSP engines which
includes adaptive equalizer and base-line wander
correction mechanism. The adaptive equalizer will
compensate the loss of signals during the transmission,
while base-line wander monitors and corrects the
equalization process. If a valid data is detected then the
data are parallelized in Serial to Parallel block, which it
converts NRZI coded data form back to scrambled data.
Copyright © 2003, IC Plus Corp.
Confidential, All rights reserved.
Advanced, Specification subject to change without notice.
Fiber transmission first encodes the data into 5-bits
wide data format. The data are then serialized and then
converted to fit the physical medium transmission.
100Mbps FX Receive:
The received data contains the information periodically,
and for Fiber Receive, the Clock recovery extracts the
data from the clock cycle. The extracted data is
parallelized into 5-bits wide data, which are then
converted back to nibble-formed information.
MII and Management Control Interface
Media Independent Interface (MII) is described in
clause 22 in the IEEE 802.3u standard. The main
function of this interface is to provide a communication
path between PHY and MAC/Repeater. It can operate
either in 10Mb or 100Mb environment, and operate at
2.5MHz frequency for 10Mb clock data rate or 25MHz
frequency for 100Mb data rate transmission. MII
consists of 4 bit wide data path for both transmit and
receive. The transmission pins consists of TXD[3:0],
TX_EN and TXC, and at receiving MII pins have
RXD[3:0], RXER, RX_DV and RXC. The Management
control pins include MDC and MDIO. MDC,
Management Data Clock, provides management data
clock at maximum of 10MHz as a reference for MDIO,
Management Data Input/Output. CRS, Carrier Sense,
is used for signaling data transmission is in process
while COL, Collision, is used for signaling the
occurrence of collision during transmission.
Transmitting a packet, MAC will first assert TX_EN and
convert the information into 4 bit wide data and then
pass the data to IP101. IP101 will sample the data
according to TX_CLK until TX_EN is low.
While receiving a packet, IP101 asserts RX_DV high
when data present in the medium through RXD[3:0] bus
lines. IP101 samples received data according to
RX_CLK until the medium is back to idle state.
18 / 33
NOT APPROVED BY TECHNICAL DOCUMENT CONTROL
IP101-DS-R0.02
Feb. 24, 2003
IP101
RMII Interface
Auto-Negotiation and Related Information
Reduced Media Independent Interface (RMII) is
defined to provide a fewer pins data transmission
condition. The management interface, MDC and MDIO,
are identical to the MII defined in IEEE 802.3. RMII
supports 10/100Mb data rates and the clock source is
provided by a single 50MHz clock from either external
or within IP101. This clock is used as reference for
transmit, receive and control. RMII provides
independent 2 bit wide transmit and receive data path,
i.e., TXD[1:0] and RXD[1:0]. CRS_DV is asserted when
the receive medium is not idle and de-asserted when
the medium is idle.
IP101 supports clause 28 in the IEEE 802.3u standard.
IP101 can be operated either in 10Mbps/100Mbps or
half/full duplex transmission mode. IP101 also supports
flow control mechanism to prevent any collision in the
network. If the other end does not support N-Way
function, IP101 will link at half duplex mode and enter
parallel detection.
At beginning of auto-negotiation, IP101 will advertise its
own ability by sending FLP waveform out to the other
end and also listening signals from the other end. IP101
will place itself into correct connection speed depends
on the received signals. If NLP signal is replied from the
other end, IP101 will enter 10Mbps, while active idle
pulses (unique 100Mbps pattern) IP101 will go to
100Mbps mode instead.
Before any transmission occurs, CRS_DV should be
de-asserted and value “00” should be present in both
TXD[1:0] and RXD[1:0]. When transmission begins,
IP101 will send “01” (TXD[1:0] = 01) for preamble to
indicate SFD, and also assert TX_EN synchronous with
first nibble of the preamble. TX_EN should be
de-asserted until the end of the data transmission. At
receiving mechanism, by receiving “01” means a valid
data is available. If False carrier is detected, RXD[1:0]
shall be “10” until the end of the transmission.
th
At 10Mbps mode, every 10 cycle of REF_CLK will be
sampled in RXD[1:0] and TXD[1:], because the
REF_CLK frequency is 10 times faster than the data
rate of the 10Mbps.
SNI Interface
The IP101 also provides serial-network interface for
legacy MACs, when the chip operates at 10BASE-T
either by NWAY resolved result or by forced mode. To
setup for this mode of operation, pull both the MII/SNIB
and the COL/RMII pins to low.
The transaction protocol of SNI interface is almost
identical to that of MII interface, except of data bit width
and clock rate. This interface consists of 10Mbps
transmit and receive clock generated by PHY’s digital
phase-locked loop (DPLL), 10Mbps transmit and
receive serial data, transmit enable, collision detect,
and carry sense signals.
IP101-DS-R0.02
Feb. 24, 2003
Once the negotiation has completed with the other
party, IP101 will configure itself to the desired
connection mode, i.e., 10/100Mbps or Half/Full duplex
modes. If there is no detection of link pulses within
1200ms~1500mS, IP101 will enter Link Fail State and
restart auto-negotiation procedure.
The auto-negotiation information is stored in the
IP101’s MII registers. These registers can be modified
and monitor the IP101’s N-Way status. The reset
auto-negotiation in register 0 of MII registers can be set
at any time to restart auto-negotiation.
The flow control ability is also included in the IP101
chip. If MAC supports flow control condition, then flow
control will be enabled by setting bit 10 (Pause) of the
Register 4.
Pin 37 (AN_ENA), 38 (DLPX), 39 (SPD) can be
configured manually to set IP101’s transmission ability.
1. Enabling Pin 37 (set high) will put IP101 to N-Way
mode, if set low to pin 37, it will put IP101 into
forced mode.
2. Pin 38 will configure Duplex ability of IP101, at high,
IP101 is set to Full-Duplex and low will let IP101
enter half duplex mode.
3. Pin 39 determines the speed of connection. If the
pin is pulled high, IP101 is set at 100Mbps, while at
low will make IP101 to connect at 10Mbps speed.
19 / 33
Copyright © 2003, IC Plus Corp.
Confidential, All rights reserved.
Advanced, Specification subject to change without notice.
NOT APPROVED BY TECHNICAL DOCUMENT CONTROL
IP101
LED Configuration
Various Link indications are displayed by LEDs.
LED
Function
LED0
Link status: Active indicates the link has established
LED1
Duplex operation: Active indicates duplex operation is on
LED2
10Mbps Transmission: Active indicates 10Mbps connection has established
LED3
100Mbps Transmission: Active indicates 100Mbps connection has established
LED4
Collision detect: Active indicates Collision has occurred
Table 4-1: LED Configuration
LED pins also include the information of PHY address, the default PHY address is set at 00001b (01h). The PHY
address can be modified by changing the LED circuitry. The modification can be arranged as follow:
VDD33
R27
R27
5.1k ohm
5.1k ohm
R26
LED
LEDx {X=0:4}
D6
R26
LEDx {X=0:4}
5.1k ohm
LED
D6
5.1k ohm
Figure 3: PHY address Configuration
The left diagram will enable the specific PHY address to 1, if it is connected to VDD33. The diagram on the right
shows the configuration for setting PHY address to 0, when the circuit is connected to ground.
By setting either one of the bits according to the diagram will allow one to modify PHY addresses from PHYAD0 to
PHYAD4.
Copyright © 2003, IC Plus Corp.
Confidential, All rights reserved.
Advanced, Specification subject to change without notice.
20 / 33
NOT APPROVED BY TECHNICAL DOCUMENT CONTROL
IP101-DS-R0.02
Feb. 24, 2003
IP101
Power-Down Modes
Repeater Modes
IP101 can be power-down by 4 methods. These 4
methods are as follow:
1. Power Down in bit 11 of Register 0: Enable this bit
will disconnect the power to IP101 and also internal
clock, but MDC and MDIO are still activated.
2. APS mode in bit 1 of Register 16: Set high to this
bit will let PHY into power saving mode
3. Analog off in bit 0 of Register 16: Enable this bit will
put IP101 in analog off state. This will power down
all analog functions but not internal 25MHz
oscillator.
4. ISOL pin (pin 43): Set high will isolate IP101 from
MAC and disable management interface (MDC and
MDIO). The power usage is at minimum when this
pin is activated.
To enter Repeater mode, one can either set pin 40
(RPTR) to high or set 1 to bit 2 of Register 16 will allow
IP101 to enter Repeater mode. If IP101 is used in
repeater, CRS will be high if IC is in process of
receiving packets, while IP101 is used in a network
interface card, CRS will be generated in both
transmitting and receiving packets.
IP101-DS-R0.02
Feb. 24, 2003
Miscellaneous
ISET (pin 28) should be connected to GND via a 6.2k
ohm resistor with 1% accuracy to ensure a correct
driving current for transmit DAC.
Set low to pin 42, REST_N, for at least 10ms will reset
all functions available in IP101. The bit 15 of Register 0
will put PHY into its default status.
21 / 33
Copyright © 2003, IC Plus Corp.
Confidential, All rights reserved.
Advanced, Specification subject to change without notice.
NOT APPROVED BY TECHNICAL DOCUMENT CONTROL
IP101
8.0 Electrical Characteristics (D.C. Characteristic)
Absolute Maximum Rating
Minimum
Typical
Maximum
Supply Voltage
Symbol
Conditions
3.0 V
3.3V
3.6V
Storage Temp
-55°C
125°C
Power Dissipation
Symbol
IP101
Auto Power Saving Mode
27mA
Analog off Mode
8mA
Power Down Mode
4mA
Isolate Mode
3mA
100 Full
136mA
100 Half
140mA
10 Full
149mA
10 Half
149mA
10 Transmit
149mA
10 Receive
149mA
10 IDLE
73mA
Operating Condition
Symbol
Conditions
Vcc
3.3V Supply voltage
TA
Operating Temperature
Minimum
Typical
Maximum
3.0 V
3.3V
3.6V
0°C
70°C
Supply Voltage
Symbol
Specific Name
Condition
Min
Max
VIH
Input High Vol.
0.5*Vcc
Vcc+0.5V
VIL
Input Low Vol.
-0.5V
0.3*Vcc
VOH
Output High Vol.
0.9*Vcc
Vcc
VOL
Output Low Vol.
IOZ
Tri-state Leakage
Vout=Vcc or GND
IIN
Input Current
Vin=Vcc or GND
Icc
Average Operating Supply Current
Iout=0mA
PECL VIH
PECL Input High Vol
Vdd-1.16V
Vdd-0.88V
PECL VIL
PECL Input Low Vol.
Vdd-1.81V
Vdd-1.47V
PECL VOH
PECL Output High Vol.
Vdd-1.02V
PECL VOL
PECL Output Low Vol.
Copyright © 2003, IC Plus Corp.
Confidential, All rights reserved.
Advanced, Specification subject to change without notice.
0.1*Vcc
200mA
Vdd-1.62V
22 / 33
NOT APPROVED BY TECHNICAL DOCUMENT CONTROL
IP101-DS-R0.02
Feb. 24, 2003
IP101
9.0 Layout Guideline
General Layout Guideline
prevent large EMI effect.
- Keep ground region as one continuous and
Best performance depends on good layout. The
following recommendation steps will help customer to
gain maximum performance.
Create good power source to minimize noise from
switching power source.
- All components are qualified, especially high noise
component, such as clock component.
- Use bulk capacitors between power plane and
ground plane for 4 layers board, signals trace on
component and bottom side, power plane on third
layer, and ground layer on second layer.
- Use decoupling capacitors to decouple high
frequency noise between chip’s power and ground,
must be as close as possible to IP101.
- The clock trace length to IP101 must be equal the
clock trace length to MAC.
- Use guard traces to protect clock traces if possible
- Avoid signals path parallel to clock signals path,
because clock signals will interference with other
parallel signals, degrading signal quality, such as
MDC and X1signals.
- The clock must be low jitter with less than 0.5ns for
25/50/125Mhz 100ppm.
- Avoid highly speed signal across ground gap to
IP101-DS-R0.02
Feb. 24, 2003
-
unbroken plane.
Place a gap between the system and chassis
grounds.
No any ground loop exists on the chassis ground.
Twisted Pair recommendation
When routing the TD+/- signal traces from IP101 to
transformer, the traces should be as short as possible,
the termination resistors should be as close as possible
to the out put of the TD+/- pair of IP101. Center tap of
primary winding of these transformers must be
connected to analog 2.5V respectively. It is
recommended that RD+/- trace pair be route such that
the space between it and others is three times space,
which can separate individual traces from one another.
It is recommended that offers chassis ground in the
area between transformer and media connector (RJ-45
port), this isolates the analog signals from external
noise sources and reduces EMI effect. Note the usage
of the vias, it is best not use via to place anywhere
other than in close proximity to device, in order to
minimize impedance variations in a given signal trace.
23 / 33
Copyright © 2003, IC Plus Corp.
Confidential, All rights reserved.
Advanced, Specification subject to change without notice.
NOT APPROVED BY TECHNICAL DOCUMENT CONTROL
IP101
10.0 Circuit Diagram
There are 3 suggested circuit diagrams for IP101.
10.1 MII interface with UTP
R1
VDD33 5.1K
Chip Diagram
VDD33
R3
5.1K
U1
MDC
MDIO
TXD0
TXD1
TXD2
TXD3
TX_EN
TX_CLK
RX_DV
RXD0
RXD1
RXD2
RXD3
RX_CLK
COL
CRS/LEDMOD
RX_ER/FIBMOD
CRS/LEDMOD
To set the LED
mode 2 on
Y1
C6 25.000Mhz
20P
C7
20P
25
26
6
5
4
3
2
7
22
21
20
19
18
16
1
23
24
46
47
PHYAD0/LED0
PHYAD1/LED1
PHYAD2/LED2
PHYAD3/LED3
PHYAD4/LED4
9
10
12
13
15
REGIN
VDD33
INT
8
14
48
*
R13
11
17
45
5.1k
MDC
MDIO
TXD0
TXD1
TXD2
TXD3
TX_EN
TX_CLK/REF_CLK
RX_DV
RXD0
RXD1
RXD2
RXD3
RX_CLK
COL/RMII
CRS/LEDMOD
RX_ER/FIBMOD
X1
X2
REGOUT
AVDD33
AGND
AGND
IP101
TEST_ON
MDI_RP
MDI_RN
MDI_TN
MDI_TP
PHYAD0/LED0
PHYAD1/LED1
PHYAD2/LED2
PHYAD3/LED3
PHYAD4/LED4
ISET
ISOL
RPTR
SPD
DPLX
AN_ENA
LDPS
MII_SNIB
RESET_N
REGIN
DVDD33
INTR
REGOUT
AVDD33
32
36
29
35
27
Floating or
pull-low
31
30
MDI_RP
MDI_RN
33
34
28
43
40
39
38
37
41
44
42
MDI_TN
MDI_TP
ISOL
RPTR
SPD
DPLX
AN_ENA
LDPS
MII_SNIB
R8
6.2K
BANDGAP
REGISTER
DGND
DGND
DGND
IP101 LQFP48
C16
0.1U
RESET_N
R14
0
RESET_N
R16
0
VDD33
R15
5.1K
* : Optional ,but recommended
Pin48 could be short VDD33 if
interrupt funtion is not
used.
Default setting
C17
0.1U
RESET Circuitry
Title
IP101 Chip Circuit Diagram
Size
Document Number
Custom
Date:
Transformer
Rev
<RevCode>
MII UTP
Tuesday, February 18, 2003
Sheet
1
of
3
* : Optional ,but recommended
C1
0.1U
*
R2
50(1%)
R3
50(1%)
CH_GND
*
C3
5pF
C4
5pF
for EMI supression
U2
U3
1
1
MDI_RP
2
MDI_RN
3
15
MDI_TN
14
16
MDI_TP
RD+
RX+
RD-
CT
CT
RX-
TD-
TX-
CT
CMT
TD+
TX+
7
2
5
3
6
4
11
5
12
6
10
7
*
16PT8520CX DIP
R6
50(1%)
R7
50(1%)
C8
5pF
R14 *
C10
0.1U
*
Only 1 resister is needed
if 2 CT of transformer
have been shorted inside.
R8
0 ohm
8
C9
5pF
TX+
TXC5
0.1U
RX+
N/C
N/C
C6
0.1U
RXN/C
N/C
GND
9
RJ8-45
R10
75
R11
75
R12
75
R13
75
CH_GND
(CONNECT TO CHASSIS GND)
C13
CH_GND
0 ohm
0.01U/3KV
REGOUT
REGOUT
*
C14
C15
0.01U
0.1U
*
C11
0.01U
*
C12
0.1U
Title
IP101 Chip Circuit Diagram
Size
Document Number
Custom
Date:
Copyright © 2003, IC Plus Corp.
Confidential, All rights reserved.
Advanced, Specification subject to change without notice.
Tuesday, February 18, 2003
24 / 33
NOT APPROVED BY TECHNICAL DOCUMENT CONTROL
Rev
<RevCode>
MII UTP
Sheet
2
of
3
IP101-DS-R0.02
Feb. 24, 2003
IP101
10.1 MII interface with UTP (continued)
LED and PHY address Configuration
Power: 5V ~ 3.3V
VCC5V
C22
10U
U4
INPUT
This schematic sets PHY address to
00001b.
OUTPUT
ADJ/GND
R19
3
2
VDD33
1
VDD33
C24
10U
P0PHYAD0/LED0
LM1117
R20
5.1K
510 ohm
D1
LED
R21
P0PHYAD1/LED1
5.1K
D2
LED
R22
REGOUT and REGIN connection
Analog and
Digital 3.3V
connection
510 ohm
R23
P0PHYAD2/LED2
D3
5.1K
L1
R24
REGOUT
LED
R26
5.1K
D4
LED
C18
22U
*
C19
0.1U
C20
*
C21
0.01U
0.1U
R27
510 ohm
R28
* : Optional ,but recommended
P0PHYAD4/LED4
5.1K
D5
LED
LED1
Dupx
REGIN
BEAD SMD
510 ohm
P0PHYAD3/LED3
LED0
Link
REGOUT
510 ohm
LED2
10Act
LED3
100Act
L2
VDD33
Hardwire Configuration network:
R29
LED4
COL
AVDD33
BEAD
C16
0.1U
1. This configuration shows
Enable: Auto negotiation, Full duplex, 100Mbps,
Link Down Power Saving, MII interface
Disable: Isolate, Repeater mode
2. These senven configuration pins could be
connected to VDD or GND directly.
Title
IP101 Chip Circuit Diagram
Size
A
Date:
IP101-DS-R0.02
Feb. 24, 2003
25 / 33
Document Number
Rev
<RevCode>
MII UTP
Tuesday, February 18, 2003
Sheet
3
of
3
Copyright © 2003, IC Plus Corp.
Confidential, All rights reserved.
Advanced, Specification subject to change without notice.
NOT APPROVED BY TECHNICAL DOCUMENT CONTROL
IP101
10.2 RMII interface with UTP connection
U1
Chip Diagram
VDD33
R1
5.1K
MDC
MDIO
P0TXD0
P0TXD1
VDD33
25
26
6
5
4
3
2
7
22
21
20
19
18
16
1
23
24
46
47
P0TX_EN
REF_CLK
P0CRS_DV
P0RXD0
P0RXD1
R4
5.1k
P0COL
P0RX_ER/FIBMOD
R5
C7
20P
5.1k
9
10
12
13
15
REGIN
VDD33
P0INT
8
14
48
11
17
45
R15
*
* : Optional ,but recommended
P0PHYAD0/LED0
P0PHYAD1/LED1
P0PHYAD2/LED2
P0PHYAD3/LED3
P0PHYAD4/LED4
5.1k
MDC
MDIO
TXD0
TXD1
TXD2
TXD3
TX_EN
TX_CLK/REF_CLK
CRS_DV
RXD0
RXD1
RXD2
RXD3
RX_CLK
COL/RMII
CRS
RX_ER/FIBMOD
X1
X2
TEST_ON
MDI_RP
MDI_RN
MDI_TN
MDI_TP
ISET
ISOL
RPTR
SPD
DPLX
AN_ENA
LDPS
MII_SNIB
RESET_N
REGIN
DVDD33
INTR
AVDD33
C2
0.1U
29
35
AGND
AGND
PHYAD0/LED0
PHYAD1/LED1
PHYAD2/LED2
PHYAD3/LED3
PHYAD4/LED4
REGOUT
32
36
REGOUT
AVDD33
27
31
30
MDI_RP
MDI_RN
33
34
MDI_TN
MDI_TP
28
43
40
39
38
37
41
44
42
P0ISO
P0RPTR
P0SPD
P0DPLX
P0AN_ENA
P0LDPS
P0MII_SNIB
R9
6.2K (1%)
DGND
DGND
DGND
IP101 LQFP48
R16
0
C16
0.1U
BAND GAP
REGISTER
RESET_N
RESET_N
R18
0
VDD33
R17
5.1K
C17
0.1U
RESET Circuitry
Title
IP101 Chip Circuit Diagram
Size
Document Number
Custom
Date:
Transformer
Rev
<RevCode>
RMII UTP
Tuesday, February 18, 2003
Sheet
1
of
3
* : Optional ,but recommended
C1
0.1U
*
R2
50(1%)
R3
50(1%)
CH_GND
*
C3
5pF
C4
5pF
for EMI supression
U2
U3
1
1
MDI_RP
2
MDI_RN
3
15
MDI_TN
14
16
MDI_TP
RD+
RX+
RD-
CT
CT
RX-
TD-
TX-
CT
CMT
TD+
TX+
7
2
5
3
6
4
11
5
12
6
10
7
*
16PT8520CX DIP
R6
50(1%)
R7
50(1%)
C8
5pF
R14 *
C10
0.1U
*
Only 1 resister is needed
if 2 CT of transformer
have been shorted inside.
R8
0 ohm
8
C9
5pF
TX+
TXC5
0.1U
RX+
N/C
N/C
C6
0.1U
RXN/C
N/C
GND
9
RJ8-45
R10
75
R11
75
R12
75
R13
75
CH_GND
(CONNECT TO CHASSIS GND)
C13
CH_GND
0 ohm
0.01U/3KV
REGOUT
*
REGOUT
C14
C15
0.01U
0.1U
*
C11
0.01U
*
C12
0.1U
Title
IP101 Chip Circuit Diagram
Size
Document Number
Custom
Date:
Copyright © 2003, IC Plus Corp.
Confidential, All rights reserved.
Advanced, Specification subject to change without notice.
Tuesday, February 18, 2003
26 / 33
NOT APPROVED BY TECHNICAL DOCUMENT CONTROL
Rev
<RevCode>
RMII UTP
Sheet
2
of
3
IP101-DS-R0.02
Feb. 24, 2003
IP101
10.2 RMII interface with UTP connection (continued)
LED and PHY address
Configuration
CLOCK
U4
L2
1
VDD33
4
CHOKE SMD
C22
0.1UF
This schematic sets PHY address to
00001b.
2
C23
4.7UF
C24
1UF
C25
10UF
R25
0
3
OSC 50MHZ (HALF)
REF_CLK
R19
RER_CLK
VDD33
P0PHYAD0/LED0
R20
5.1K
510 ohm
Oscillator's clock MUST be at same
distance from all chipsets.
D1
LED
R21
P0PHYAD1/LED1
5.1K
D2
LED
R22
REGOUT and REGIN connection
Analog and
Digital 3.3V
connection
510 ohm
R23
P0PHYAD2/LED2
D3
5.1K
L1
R24
REGOUT
LED
R26
5.1K
D4
LED
C18
22U
*
C19
0.1U
C20
*
C21
0.01U
0.1U
R27
510 ohm
R28
* : Optional ,but recommended
P0PHYAD4/LED4
5.1K
D5
LED
LED1
Dupx
REGIN
BEAD SMD
510 ohm
P0PHYAD3/LED3
LED0
Link
REGOUT
510 ohm
LED2
10Act
LED3
100Act
L2
VDD33
Hardwire Configuration network:
R29
LED4
COL
AVDD33
BEAD
C16
0.1U
1. This configuration shows
Enable: Auto negotiation, Full duplex, 100Mbps,
Link Down Power Saving, MII interface
Disable: Isolate, Repeater mode
2. These senven configuration pins could be
connected to VDD or GND directly.
Title
IP101 Chip Circuit Diagram
Size
A
Date:
IP101-DS-R0.02
Feb. 24, 2003
27 / 33
Document Number
Rev
<RevCode>
RMII UTP
Tuesday, February 18, 2003
Sheet
3
of
3
Copyright © 2003, IC Plus Corp.
Confidential, All rights reserved.
Advanced, Specification subject to change without notice.
NOT APPROVED BY TECHNICAL DOCUMENT CONTROL
IP101
10.3 Fiber connection for both MII and RMII circuits
Chip Diagram
VDD33
R3
5.1K
R1
VDD33 5.1K
U1
MDC
MDIO
TXD0
TXD1
TXD2
TXD3
TX_EN
TX_CLK
RX_DV
RXD0
RXD1
RXD2
RXD3
RX_CLK
COL
CRS/LEDMOD
RX_ER/FIBMOD
CRS/LEDMOD
To set the LED
mode 2 on
R7
VDD33 5.1K
Y1
C5 25.000Mhz
20P
C6
20P
25
26
6
5
4
3
2
7
22
21
20
19
18
16
1
23
24
46
47
PHYAD0/LED0
PHYAD1/LED1
PHYAD2/LED2
PHYAD3/LED3
PHYAD4/LED4
9
10
12
13
15
REGIN
VDD33
INT
8
14
48
R16
11
17
45
5.1k
MDC
MDIO
TXD0
TXD1
TXD2
TXD3
TX_EN
TX_CLK/REF_CLK
RX_DV
RXD0
RXD1
RXD2
RXD3
RX_CLK
COL/RMII
CRS/LEDMOD
RX_ER/FIBMOD
X1
X2
REGOUT
AVDD33
AGND
AGND
IP101
TEST_ON
MDI_RP
MDI_RN
MDI_TN
MDI_TP
PHYAD0/LED0
PHYAD1/LED1
PHYAD2/LED2
PHYAD3/LED3
PHYAD4/LED4
ISET
ISOL
RPTR
SPD
DPLX
AN_ENA
LDPS
MII_SNIB
RESET_N
REGIN
DVDD33
INTR
32
36
REGOUT
AVDD33
29
35
27
Floating or
pull-low
31
30
33
34
28
43
40
39
38
37
41
44
42
2
2
MDI_TN
MDI_TP
2
2
ISOL
RPTR
SPD
DPLX
AN_ENA
LDPS
MII_SNIB
DGND
DGND
DGND
R13
6.2K
BANDGAP
REGISTER
Default setting
IP101 LQFP48
R17
0
RESET_N
RESET_N
C10
0.1U
MDI_RP
MDI_RN
R19
VDD33
0
R18
5.1K
Pin48 could be short VDD33 if
interrupt funtion is not
used.
C11
0.1U
RESET Circuitry
Title
IP101 Chip Circuit Diagram
Size
Document Number
Custom
Date:
Rev
<RevCode>
MII Fiber
Tuesday, February 18, 2003
Sheet
1
of
3
Fiber Connection
VCC5V
REGOUT
C2
0.01U/25V
R5
100ohm(1%)
1
MDI_TP
1
1
1
MDI_TN
MDI_RN
MDI_RP
R6
100ohm(1%)
R2
R3
120(1%) 120(1%)
C3
470u/25V
9
C4
0.01U/25V
C5
0.01U/25V
8
7
6
R9
600 (1%)
R8
600 (1%)
5
4
R13
82(1%)
R14
82(1%)
3
C7
0.01U/25V
2
1
C8
0.01U/25V
R11
8.2Kohm(1%)
R12
8.2Kohm(1%)
R17
130 (1%)
R18
130 (1%)
GND
TD+
TDVCC
VCC
SD+
RDRD+
GND
Agilent 5103T
C9
0.01U/25V
Title
IP101 Chip Circuit Diagram
Size
Document Number
Custom
Date:
Copyright © 2003, IC Plus Corp.
Confidential, All rights reserved.
Advanced, Specification subject to change without notice.
Tuesday, February 18, 2003
28 / 33
NOT APPROVED BY TECHNICAL DOCUMENT CONTROL
Rev
<RevCode>
MII Fiber
Sheet
2
of
3
IP101-DS-R0.02
Feb. 24, 2003
IP101
10.3 Fiber connection for both MII and RMII circuits (continued)
LED and PHY address Configuration
Power: 5V ~ 3.3V
VCC5V
C22
10U
U4
3
INPUT
This schematic sets PHY address to
00001b.
2
OUTPUT
R19
VDD33
1
ADJ/GND
VDD33
C24
10U
P0PHYAD0/LED0
LM1117
R20
5.1K
510 ohm
D1
LED
R21
P0PHYAD1/LED1
5.1K
D2
LED
R22
REGOUT and REGIN connection
Analog and
Digital 3.3V
connection
510 ohm
R23
P0PHYAD2/LED2
D3
5.1K
L1
R24
REGOUT
LED
R26
5.1K
D4
LED
C18
22U
*
C19
0.1U
C20
*
C21
0.01U
0.1U
R27
510 ohm
R28
* : Optional ,but recommended
P0PHYAD4/LED4
5.1K
D5
LED
LED1
Dupx
REGIN
BEAD SMD
510 ohm
P0PHYAD3/LED3
LED0
Link
REGOUT
510 ohm
LED2
10Act
LED3
100Act
L2
VDD33
Hardwire Configuration network:
R29
LED4
COL
AVDD33
BEAD
C16
0.1U
1. This configuration shows
Enable: Auto negotiation, Full duplex, 100Mbps,
Link Down Power Saving, MII interface
Disable: Isolate, Repeater mode
2. These senven configuration pins could be
connected to VDD or GND directly.
Title
IP101 Chip Circuit Diagram
Size
A
Date:
IP101-DS-R0.02
Feb. 24, 2003
29 / 33
Document Number
Rev
<RevCode>
MII Fiber
Tuesday, February 18, 2003
Sheet
3
of
3
Copyright © 2003, IC Plus Corp.
Confidential, All rights reserved.
Advanced, Specification subject to change without notice.
NOT APPROVED BY TECHNICAL DOCUMENT CONTROL
IP101
10.3 Fiber connection for both MII and RMII circuits (continued)
Chip Diagram
U1
VDD33
R1
5.1K
MDC
MDIO
P0TXD0
P0TXD1
25
26
6
5
4
3
2
7
22
21
20
19
18
16
1
23
24
46
47
VDD33
P0TX_EN
REF_CLK
P0CRS_DV
P0RXD0
P0RXD1
R4
5.1k
P0COL
P0RX_ER/FIBMOD
R5
5.1k
C7
20P
*
P0PHYAD0/LED0
P0PHYAD1/LED1
P0PHYAD2/LED2
P0PHYAD3/LED3
P0PHYAD4/LED4
9
10
12
13
15
REGIN
VDD33
P0INT
8
14
48
R15
5.1k
11
17
45
MDC
MDIO
TXD0
TXD1
TXD2
TXD3
TX_EN
TX_CLK/REF_CLK
CRS_DV
RXD0
RXD1
RXD2
RXD3
RX_CLK
COL/RMII
CRS
RX_ER/FIBMOD
X1
X2
REGOUT
AVDD33
AGND
AGND
TEST_ON
MDI_RP
MDI_RN
MDI_TN
MDI_TP
PHYAD0/LED0
PHYAD1/LED1
PHYAD2/LED2
PHYAD3/LED3
PHYAD4/LED4
ISET
ISOL
RPTR
SPD
DPLX
AN_ENA
LDPS
MII_SNIB
RESET_N
REGIN
DVDD33
INTR
32
36
REGOUT
C2
0.1U
29
35
27
31
30
MDI_RP
MDI_RN
33
34
MDI_TN
MDI_TP
28
43
40
39
38
37
41
44
42
P0ISO
P0RPTR
P0SPD
P0DPLX
P0AN_ENA
P0LDPS
P0MII_SNIB
DGND
DGND
DGND
R9
6.2K (1%)
R16
0
IP101 LQFP48
BAND GAP
REGISTER
RESET_N
RESET_N
C16
0.1U
AVDD33
R18
0
VDD33
R17
5.1K
C17
0.1U
RESET Circuitry
* : Optional ,but recommended
Title
IP101 Chip Circuit Diagram
Size
Document Number
Custom
Date:
Rev
<RevCode>
RMII Fiber
Tuesday, February 18, 2003
Sheet
1
of
3
Fiber Connection
VCC5V
REGOUT
C2
0.01U/25V
R5
100ohm(1%)
R6
100ohm(1%)
R2
120(1%)
C3
470u/25V
9
GND
R3
120(1%)
C4
0.01U/25V
C5
0.01U/25V
MDI_TP
MDI_TN
MDI_RN
MDI_RP
8
7
6
R9
600 (1%)
R8
600 (1%)
5
4
R13
82(1%)
R14
82(1%)
3
C7
0.01U/25V
2
1
C8
0.01U/25V
R17
130 (1%)
R11
8.2Kohm(1%)
R18
130 (1%)
C9
0.01U/25V
TD+
TDVCC
VCC
SD+
RDRD+
GND
Agilent 5103T
R12
8.2Kohm(1%)
Title
IP101 Chip Circuit Diagram
Size
Document Number
Custom
Date:
Copyright © 2003, IC Plus Corp.
Confidential, All rights reserved.
Advanced, Specification subject to change without notice.
Tuesday, February 18, 2003
30 / 33
NOT APPROVED BY TECHNICAL DOCUMENT CONTROL
Rev
<RevCode>
RMII Fiber
Sheet
2
of
3
IP101-DS-R0.02
Feb. 24, 2003
IP101
10.3 Fiber connection for both MII and RMII circuits (continued)
LED and PHY address
Configuration
CLOCK
U4
L2
1
VDD33
4
CHOKE SMD
C22
0.1UF
This schematic sets PHY address to
00001b.
2
C23
4.7UF
C24
1UF
C25
10UF
R25
0
3
OSC 50MHZ (HALF)
REF_CLK
R19
RER_CLK
VDD33
P0PHYAD0/LED0
R20
5.1K
510 ohm
Oscillator's clock MUST be at same
distance from all chipsets.
D1
LED
R21
P0PHYAD1/LED1
5.1K
D2
LED
R22
REGOUT and REGIN connection
Analog and
Digital 3.3V
connection
510 ohm
R23
P0PHYAD2/LED2
D3
5.1K
L1
R24
REGOUT
LED
R26
5.1K
D4
LED
C18
22U
*
C19
0.1U
C20
*
C21
0.01U
0.1U
R27
510 ohm
R28
* : Optional ,but recommended
P0PHYAD4/LED4
5.1K
D5
LED
LED1
Dupx
REGIN
BEAD SMD
510 ohm
P0PHYAD3/LED3
LED0
Link
REGOUT
LED3
100Act
AVDD33
BEAD
C16
0.1U
1. This configuration shows
Enable: Auto negotiation, Full duplex, 100Mbps,
Link Down Power Saving, MII interface
Disable: Isolate, Repeater mode
2. These senven configuration pins could be
connected to VDD or GND directly.
510 ohm
LED2
10Act
L2
VDD33
Hardwire Configuration network:
R29
LED4
COL
Title
IP101 Chip Circuit Diagram
Size
A
Date:
Document Number
Rev
<RevCode>
RMII Fiber
Tuesday, February 18, 2003
Sheet
3
of
3
11.0 Order Information
Part No.
PIN
Notice
IP101
48 PIN LQFP
-
IP101-DS-R0.02
Feb. 24, 2003
31 / 33
Copyright © 2003, IC Plus Corp.
Confidential, All rights reserved.
Advanced, Specification subject to change without notice.
NOT APPROVED BY TECHNICAL DOCUMENT CONTROL
IP101
12.0 Package and Mechanical Specification
48
37
1
36
D
PH
12
25
13
HE
24
"E"
b 12"
e
12
A
A2
θ
E
13
GAUGE PLANE
A1
F y
c
F
SEATING
PLANE
D
0.254
12"
L
L1
DETAIL "E"
24
25
2
2
1
36
48
unit
Symbol
A
A1
A2
b
c
D
E
e
Hd
He
L
L1
y
e
37
mm
1.600MAX.
0.050~0.150
1.400±0.05
0.200TYP
0.127TYP
7.000±0.100
7.000±0.100
0.500TYP
9.000±0.250
9.000±0.250
0.600±0.150
1.000REF
0.100MAX.
0”~7”
inch
0.0630MAX.
0.0020~0.0059
0.0551±0.0020
0.0078TYP
0.0050TYP
0.2756±0.0039
0.2756±0.0039
0.0196TYP
0.3543±0.0098
0.3543±0.0098
0.0236±0.006
0.0393REF
0.0039MAX.
0”~7”
Copyright © 2003, IC Plus Corp.
Confidential, All rights reserved.
Advanced, Specification subject to change without notice.
Notes:
1. DIMENSION D & E DO NOT INCLUDE MOLD FLASH OR
PROTRUSION.
2. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION /
INTRUSION.
3. MAX. END FLASH IS 0.15MM.
4. MAX. DAMBAR PROTRUSION IS 0.13MM.
5. GENERAL APPEARANCE SPEC SHOULD BE BASED ON FINAL
VISUAL INSPECTION SPEC.
32 / 33
NOT APPROVED BY TECHNICAL DOCUMENT CONTROL
IP101-DS-R0.02
Feb. 24, 2003
IP101
IC Plus Corp.
Headquarter
10F, No.47, Lane 2, Kwang-Fu Road, Sec. 2,
Hsin-Chu City, Taiwan 300, R.O.C.
TEL : 886-3-575-0275
FAX : 886-3-575-0475
Website : www.icplus.com.tw
IP101-DS-R0.02
Feb. 24, 2003
Sales Office
4F, No. 106, Hsin-Tai-Wu Road, Sec.1,
Hsi-Chih, Taipei Hsien, Taiwan 221, R.O.C.
TEL : 886-2-2696-1669
FAX : 886-2-2696-2220
33 / 33
Copyright © 2003, IC Plus Corp.
Confidential, All rights reserved.
Advanced, Specification subject to change without notice.
NOT APPROVED BY TECHNICAL DOCUMENT CONTROL