DS91M040 125 MHz Quad M-LVDS Transceiver General Description Features The DS91M040 is a quad M-LVDS transceiver designed for driving / receiving clock or data signals to / from up to four multipoint networks. M-LVDS (Multipoint LVDS) is a new family of bus interface devices based on LVDS technology specifically designed for multipoint and multidrop cable and backplane applications. It differs from standard LVDS in providing increased drive current to handle double terminations that are required in multipoint applications. Controlled transition times minimize reflections that are common in multipoint configurations due to unterminated stubs. M-LVDS devices also have a very large input common mode voltage range for additional noise margin in heavily loaded and noisy backplane environments. A single DS91M040 channel is a half-duplex transceiver that accepts LVTTL/LVCMOS signals at the driver inputs and converts them to differential M-LVDS signal levels. The receiver inputs accept low voltage differential signals (LVDS, BLVDS, M-LVDS, LVPECL and CML) and convert them to 3V LVCMOS signals. The DS91M040 supports both M-LVDS type 1 and type 2 receiver inputs. ■ DC - 125 MHz / 250 Mbps low jitter, low skew, low power operation ■ Wide Input Common Mode Voltage Range allows up to ±2V of GND noise Conforms to TIA/EIA-899 M-LVDS Standard Pin selectable M-LVDS receiver type (1 or 2) Controlled transition times (2.0 ns typ) minimize reflections 8 kV ESD on M-LVDS I/O pins protects adjoining components ■ Flow-through pinout simplifies PCB layout ■ Small 5 mm x 5 mm LLP-32 space saving package ■ ■ ■ ■ Applications ■ Multidrop / Multipoint clock and data distribution ■ High-Speed, Low Power, Short-Reach alternative to TIA/ EIA-485/422 ■ Clock distribution in AdvancedTCA (ATCA) and MicroTCA (μTCA) backplanes Typical Application 30042202 © 2008 National Semiconductor Corporation 300422 www.national.com DS91M040 125 MHz Quad M-LVDS Transceiver May 13, 2008 DS91M040 Ordering Information Order Number Receiver Input Function Package Type DS91M040TSQ Type 1 or 2 Quad M-LVDS Transciever LLP-32 Connection Diagram 30042201 Logic Diagram 30042203 www.national.com 2 DS91M040 Pin Descriptions Number Name I/O, Type Description 1, 3, 5, 7 RO O, LVCMOS Receiver output pin. 26, 28, 13, 15 RE I, LVCMOS Receiver enable pin: When RE is high, the receiver is disabled. When RE is low, the receiver is enabled. There is a 300 kΩ pullup resistor on this pin. 25, 27, 14, 16 DE I, LVCMOS Driver enable pin: When DE is low, the driver is disabled. When DE is high, the driver is enabled. There is a 300 kΩ pulldown resistor on this pin. 2, 4, 6, 8 DI I, LVCMOS Driver input pin. 31, DAP GND Power 17, 19, 21, 23 A I/O, M-LVDS Ground pin and pad. Non-inverting driver output pin/Non-inverting receiver input pin 18, 20, 22, 24 B I/O, M-LVDS Inverting driver output pin/Inverting receiver input pin 11, 12, 29, 30 VDD Power 32 FSEN1 I, LVCMOS Power supply pin, +3.3V ± 0.3V Failsafe enable pin with a 300 kΩ pullup resistor. This pin enables Type 2 receiver on inputs 0 and 2. FSEN1 = L --> Type 1 receiver inputs FSEN1 = H --> Type 2 receiver inputs 9 FSEN2 I, LVCMOS Failsafe enable pin with a 300 kΩ pullup resistor. This pin enables Type 2 receiver on inputs 1 and 3. FSEN2 = L --> Type 1 receiver inputs FSEN2 = H --> Type 2 receiver inputs 10 MDE I, LVCMOS Master enable pin. When MDE is H, the device is powered up. When MDE is L, the device overrides all other control and powers down. M-LVDS Receiver Types The EIA/TIA-899 M-LVDS standard specifies two different types of receiver input stages. A type 1 receiver has a conventional threshold that is centered at the midpoint of the input amplitude, VID/2. A type 2 receiver has a built in offset that is 100mV greater then VID/2. The type 2 receiver offset acts as a failsafe circuit where open or short circuits at the input will always result in the output stage being driven to a low logic state. 30042240 FIGURE 1. M-LVDS Receiver Input Thresholds 3 www.national.com DS91M040 Absolute Maximum Ratings (Note 4) ESD Susceptibility HBM (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. CDM (Note 3) Power Supply Voltage −0.3V to +4V LVCMOS Input Voltage −0.3V to (VDD + 0.3V) LVCMOS Output Voltage −0.3V to (VDD + 0.3V) M-LVDS I/O Voltage −5.5V to +5.5V M-LVDS Output Short Circuit Current Duration Continuous Junction Temperature +140°C Storage Temperature Range −65°C to +150°C Lead Temperature Range Soldering (4 sec.) +260°C Maximum Package Power Dissipation @ +25°C SQ Package 833 mW Derate SQ Package 6.67 mW/°C above +25°C Package Thermal Resistance θJA +150°C/W θJC +63.8°C/W ≥8 kV ≥250V ≥1250V MM (Note 2) Note 1: Human Body Model, applicable std. JESD22-A114C Note 2: Machine Model, applicable std. JESD22-A115-A Note 3: Field Induced Charge Device Model, applicable std. JESD22-C101-C Recommended Operating Conditions Supply Voltage, VDD Voltage at Any Bus Terminal Min Typ Max Units 3.0 3.3 3.6 V −1.4 +3.8 V (Separate or Common-Mode) Differential Input Voltage VID LVTTL Input Voltage High VIH 2.0 LVTTL Input Voltage Low VIL 0 Operating Free Air Temperature TA −40 +25 2.4 VDD 0.8 V V V +85 °C DC Electrical Characteristics (Notes 5, 6, 7, 9) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units 650 mV M-LVDS Driver |VAB| Differential output voltage magnitude RL = 50Ω, CL = 5 pF ΔVAB Change in differential output voltage magnitude between logic states Figures 2, 4 VOS(SS) Steady-state common-mode output voltage RL = 50Ω, CL = 5 pF |ΔVOS(SS)| Change in steady-state common-mode output voltage between logic states Figures 2, 3 VA(OC) Maximum steady-state open-circuit output voltage Figure 5 VB(OC) Maximum steady-state open-circuit output voltage VP(H) Voltage overshoot, low-to-high level output (Note 12) VP(L) Voltage overshoot, high-to-low level output (Note 12) 480 −50 0 +50 mV 0.3 1.6 2.1 V 0 +50 mV 0 2.4 V 0 2.4 V 1.2VSS V RL = 50Ω, CL = 5pF, CD = 0.5 pF Figures 7, 8 −0.2VS V S IIH High-level input current (LVTTL inputs) VIH = 2.0V -15 15 μA IIL Low-level input current (LVTTL inputs) VIL = 0.8V -15 15 μA VCL Input Clamp Voltage (LVTTL inputs) IIN = -18 mA -1.5 IOS Differential short-circuit output current (Note 8) Figure 6 -43 43 mA V M-LVDS Receiver VIT+ VIT− Positive-going differential input voltage threshold Negative-going differential input voltage threshold See Function Tables See Function Tables VOH High-level output voltage (LVTTL output) IOH = −8mA VOL Low-level output voltage (LVTTL output) IOL = 8mA IOZ TRI-STATE output current VO = 0V or 3.6V IOSR Short-circuit receiver output current (LVTTL output) VO = 0V www.national.com 4 Type 1 16 50 mV Type 2 100 150 mV Type 1 −50 20 mV Type 2 50 94 mV 2.4 2.7 V 0.28 −10 -50 0.4 V 10 μA -90 mA Parameter Conditions Min Typ Max Units 32 µA +20 µA M-LVDS Bus (Input and Output) Pins IA Transceiver input/output current IB Transceiver input/output current VA = 3.8V, VB = 1.2V VA = 0V or 2.4V, VB = 1.2V −20 VA = −1.4V, VB = 1.2V −32 VB = 0V or 2.4V, VA = 1.2V −20 VB = −1.4V, VA = 1.2V −32 IAB Transceiver input/output differential current (IA − IB) VA = VB, −1.4V ≤ V ≤ 3.8V IA(OFF) Transceiver input/output power-off current IB(OFF) Transceiver input/output power-off current µA VB = 3.8V, VA = 1.2V VA = 3.8V, VB = 1.2V, DE = VCC = 1.5V −20 VA = −1.4V, VB = 1.2V, DE = VCC = 1.5V −32 −20 VB = −1.4V, VA = 1.2V, DE = VCC = 1.5V −32 −4 +20 µA +4 µA 32 µA +20 µA µA VB = 3.8V, VA = 1.2V, DE = VCC = 1.5V VB = 0V or 2.4V, VA = 1.2V, DE = VCC = 1.5V µA µA −4 VA = 0V or 2.4V, VB = 1.2V, DE = VCC = 1.5V 32 32 µA +20 µA µA IAB(OFF) Transceiver input/output power-off differential current (IA(OFF) − IB(OFF)) VA = VB, −1.4V ≤ V ≤ 3.8V, VDD = 1.5V, DE = 1.5V CA Transceiver input/output capacitance VDD = OPEN CB Transceiver input/output capacitance CAB Transceiver input/output differential capacitance CA/B Transceiver input/output capacitance balance (CA/ CB) 1 +4 µA 7.8 pF 7.8 pF 3 pF SUPPLY CURRENT (VCC) ICCD Driver Supply Current RL = 50Ω, DE = H, RE = H 67 75 mA ICCZ TRI-STATE Supply Current DE = L, RE = H 22 26 mA ICCR Receiver Supply Current DE = L, RE = L 32 38 mA ICCPD Power Down Supply Current MDE = L 3 5 mA Note 4: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Note 5: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed. Note 6: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD and ΔVOD. Note 7: Typical values represent most likely parametric norms for VDD = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed. Note 8: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Note 9: CL includes fixture capacitance and CD includes probe capacitance. 5 www.national.com DS91M040 Symbol DS91M040 Switching Characteristics (Notes 10, 11, 17) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units DRIVER AC SPECIFICATIONS tPLH Differential Propagation Delay Low to High RL = 50Ω, CL = 5 pF, 1.5 3.3 5.5 ns tPHL Differential Propagation Delay High to Low CD = 0.5 pF 1.5 3.3 5.5 ns tSKD1 Pulse Skew (Notes 12, 13) Figures 7, 8 30 125 ps tSKD2 Channel-to-Channel Skew (Notes 12, 14) 100 200 ps tSKD3 Part-to-Part Skew (Notes 12, 15) 0.8 1.6 ns tSKD4 Part-to-Part Skew (Notes 12, 16) 4 ns tTLH Rise Time (Note 12) 1.2 2.0 3.0 ns tTHL Fall Time (Note 12) 1.2 2.0 3.0 ns tPZH Enable Time (Z to Active High) RL = 50Ω, CL = 5 pF, 7.5 11.5 ns tPZL Enable Time (Z to Active Low ) CD = 0.5 pF 8.0 11.5 ns tPLZ Disable Time (Active Low to Z) Figures 9, 10 7.0 11.5 ns tPHZ Disable Time (Active High to Z) 7.0 11.5 ns 4.5 ns RECEIVER AC SPECIFICATIONS tPLH Propagation Delay Low to High CL = 15 pF 1.5 3.0 tPHL Propagation Delay High to Low Figures 11, 12, 13 1.5 3.1 4.5 ns tSKD1A Pulse Skew (Receiver Type 1) (Notes 12, 13) 55 325 ps tSKD1B Pulse Skew (Receiver Type 2) (Notes 12, 13) 475 800 ps tSKD2 Channel-to-Channel Skew (Notes 12, 14) 60 300 ps tSKD3 Part-to-Part Skew (Notes 12, 15) 0.6 1.2 ns tSKD4 Part-to-Part Skew (Notes 12, 16) 3 ns tTLH Rise Time (Note 12) 0.3 1.1 1.6 ns tTHL Fall Time (Note 12) 0.3 0.65 1.6 ns tPZH Enable Time (Z to Active High) RL = 500Ω, CL = 15 pF 3 5.5 ns tPZL Enable Time (Z to Active Low) Figures 14, 15 3 5.5 ns tPLZ Disable Time (Active Low to Z) 3.5 5.5 ns tPHZ Disable Time (Active High to Z) 3.5 5.5 ns 500 ms GENERIC AC SPECIFICATIONS tWKUP Wake Up Time (Note 12) (Master Device Enable (MDE) time) fMAX Maximum Operating Frequency (Note 12) 125 MHz Note 10: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed. Note 11: Typical values represent most likely parametric norms for VDD = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed. Note 12: Specification is guaranteed by characterization and is not tested in production. Note 13: tSKD1, |tPLHD − tPHLD|, Pulse Skew, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel. Note 14: tSKD2, Channel-to-Channel Skew, is the difference in propagation delay (tPLHD or tPHLD) among all output channels. Note 15: tSKD3, Part-to-Part Skew, is defined as the difference between the minimum and maximum differential propagation delays. This specification applies to devices at the same VDD and within 5°C of each other within the operating temperature range. Note 16: tSKD4, Part-to-Part Skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min| differential propagation delay. Note 17: CL includes fixture capacitance and CD includes probe capacitance. Note 18: Measured on a clock edge with a histogram and an acummulation of 1500 histogram hits. Input stimulus jitter is subracted geometrically. www.national.com 6 DS91M040 Test Circuits and Waveforms 30042214 FIGURE 2. Differential Driver Test Circuit 30042224 FIGURE 3. Differential Driver Waveforms 30042222 FIGURE 4. Differential Driver Full Load Test Circuit 30042212 FIGURE 5. Differential Driver DC Open Test Circuit 7 www.national.com DS91M040 30042225 FIGURE 6. Differential Driver Short-Circuit Test Circuit 30042216 FIGURE 7. Driver Propagation Delay and Transition Time Test Circuit 30042218 FIGURE 8. Driver Propagation Delays and Transition Time Waveforms www.national.com 8 DS91M040 30042219 FIGURE 9. Driver TRI-STATE Delay Test Circuit 30042221 FIGURE 10. Driver TRI-STATE Delay Waveforms 30042215 FIGURE 11. Receiver Propagation Delay and Transition Time Test Circuit 9 www.national.com DS91M040 30042217 FIGURE 12. Type 1 Receiver Propagation Delay and Transition Time Waveforms 30042223 FIGURE 13. Type 2 Receiver Propagation Delay and Transition Time Waveforms 30042213 FIGURE 14. Receiver TRI-STATE Delay Test Circuit www.national.com 10 DS91M040 30042220 FIGURE 15. Receiver TRI-STATE Delay Waveforms 11 www.national.com DS91M040 Truth Tables DS91M040 Transmitting Inputs Outputs RE DE DI B A X X X H H L H L X L H Z H L Z X — Don't care condition Z — High impedance state DS91M040 as Type 2 Receiving DS91M040 as Type 1 Receiving Inputs Output Inputs Output FSEN RE DE A−B RO FSEN RE DE A−B R L L L H L L L L L H L L ≥ +0.15V ≤ +0.05V H L ≥ +0.05V ≤ −0.05V H L L L H L L 0V X X Z H H L H L L 0V X L Z X — Don't care condition Z — High impedance state L X — Don't care condition Z — High impedance state DS91M040 Type 1 Receiver Input Threshold Test Voltages Applied Voltages Resulting Differential Input Voltage Resulting Common-Mode Input Voltage Receiver Output VIA VIB VID VICM R 2.400V 0.000V 3.800V 3.750V −1.350V −1.400V 0.000V 2.400V 3.750V 3.800V −1.400V −1.350V 2.400V −2.400V 0.050V −0.050V 0.050V −0.050V 1.200V 1.200V 3.775V 3.775V −1.375V −1.375V H L H L H L H — High Level L — Low Level Output state assumes that the receiver is enabled (RE = L) DS91M040 Type 2 Receiver Input Threshold Test Voltages Applied Voltages Resulting Differential Input Voltage Resulting Common-Mode Input Voltage Receiver Output VIA VIB VID VIC R 2.400V 0.000V 3.800V 3.800V −1.250V −1.350V 0.000V 2.400V 3.650V 3.750V −1.400V −1.400V 2.400V −2.400V 0.150V 0.050V 0.150V 0.050V 1.200V 1.200V 3.725V 3.775V −1.325V −1.375V H L H L H L H — High Level L — Low Level Output state assumes that the receiver is enabled (RE = L) www.national.com 12 DS91M040 Typical Performance 30042250 30042252 Driver Rise Time as a Function of Temperature Driver Propagation Delay (tPLHD) as a Function of Temperature 30042251 Driver Fall Time as a Function of Temperature 30042253 Driver Propagation Delay (tPHLD) as a Function of Temperature 30042258 Driver Output Signal Amplitude as a Function of Resistive Load 13 www.national.com DS91M040 30042254 30042256 Driver Power Supply Current as a Function of Frequency Receiver Propagation Delay (tPLHD) as a Function of Input Common Mode Voltage 30042255 Receiver Power Supply Current as a Function of Frequency www.national.com 30042257 Receiver Propagation Delay (tPHLD) as a Function of Input Common Mode Voltage 14 DS91M040 Physical Dimensions inches (millimeters) unless otherwise noted Order Number DS91M040TSQ See NS package Number SQA32A (See AN-1187 for PCB Design and Assembly Recommendations) 15 www.national.com DS91M040 125 MHz Quad M-LVDS Transceiver Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Design Support Amplifiers www.national.com/amplifiers WEBENCH www.national.com/webench Audio www.national.com/audio Analog University www.national.com/AU Clock Conditioners www.national.com/timing App Notes www.national.com/appnotes Data Converters www.national.com/adc Distributors www.national.com/contacts Displays www.national.com/displays Green Compliance www.national.com/quality/green Ethernet www.national.com/ethernet Packaging www.national.com/packaging Interface www.national.com/interface Quality and Reliability www.national.com/quality LVDS www.national.com/lvds Reference Designs www.national.com/refdesigns Power Management www.national.com/power Feedback www.national.com/feedback Switching Regulators www.national.com/switchers LDOs www.national.com/ldo LED Lighting www.national.com/led PowerWise www.national.com/powerwise Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors Wireless (PLL/VCO) www.national.com/wireless THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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