ETC NBC12430/D

NBC12430
3.3 V/5 VProgrammable
PLL Synthesized Clock
Generator
50 MHz to 800 MHz
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The NBC12430 is a general purpose, PLL based synthesized clock
source. The VCO will operate over a frequency range of 400 MHz to
800 MHz. The VCO frequency is sent to the N-output divider, where
it can be configured to provide division ratios of 1, 2, 4, or 8. The VCO
and output frequency can be programmed using the parallel or serial
interfaces to the configuration logic. Output frequency steps of
250 KHz, 500 KHz, 1.0 MHz, 2.0 MHz can be achieved using a
16 MHz crystal, depending on the output dividers settings. The PLL
loop filter is fully integrated and does not require any external
components.
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Best-in-Class Output Jitter Performance, ±20 ps Peak-to-Peak
MARKING
DIAGRAMS
1 28
NBC12430
AWLYYWW
PLCC-28
FN SUFFIX
CASE 776
50 MHz to 800 MHz Programmable Differential PECL Outputs
Fully Integrated Phase-Lock-Loop with Internal Loop Filter
Parallel Interface for Programming Counter and Output Dividers
During Power-Up
Minimal Frequency Overshoot
Serial 3-Wire Programming Interface
Crystal Oscillator Interface
NBC12430
LQFP-32
FA SUFFIX
CASE 873A
AWLYYWW
32
1
Operating Range: VCC = 3.135 V to 5.25 V
CMOS and TTL Compatible Control Inputs
A
WL
YY
WW
Pin Compatible with Motorola MC12430
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
 Semiconductor Components Industries, LLC, 2003
April, 2003 - Rev. 3
1
Package
Shipping
NBC12430FN
PLCC-28
37 Units/Rail
NBC12430FNR2
PLCC-28
500 Tape & Reel
NBC12430FA
LQFP-32
250 Units/Tray
NBC12430FAR2
LQFP-32
2000 Tape & Reel
Publication Order Number:
NBC12430/D
NBC12430
+3.3 or 5.0 V
1
PLL_VCC
1 MHz
FREF
PHASE
DETECTOR
16
+3.3 or 5.0 V
3
XTAL_SEL
VCO
2
FREF_EXT
4
9-BIT M
COUNTER
XTAL1
10-20MHz
2
OSC
400-800
MHz
21, 25
24
23
N
(1, 2, 4, 8)
FOUT
FOUT
20
5
TEST
XTAL2
LATCH
LATCH
6
OE
VCC
28
S_LOAD
LATCH
7
P_LOAD
0
1
0
27
S_DATA
1
2- BIT SR
9- BIT SR
3- BIT SR
26
S_CLOCK
8 → 16
17, 18
22, 19
9
2
M[8:0]
N[1:0]
Figure 1. NBC12430 Block Diagram (28-Lead PLCC)
Table 1. Output Division
Table 2. XTAL_SEL And OE
GND
19
TEST
20
VCC
21
VCC
22
GND
23
FOUT
24
FOUT
GND
25
VCC
TEST
XTAL
Enabled
VCC
1
FREF_EXT
Disabled
GND
0
XTAL_SEL
OE
FOUT
Input
2
4
8
1
FOUT
Output Division
00
01
10
11
VCC
N [1:0]
32
31
30
29
28
27
26
25
PLL_VCC
1
15
M[7]
PLL_VCC
4
21
M[8]
20
M[7]
2
14
M[6]
PLL_VCC
5
FREF_EXT
FREF_EXT
6
19
M[6]
XTAL_SEL
3
13
M[5] XTAL_SEL
7
18
M[5]
17
4
12
M[4]
XTAL1
8
XTAL1
M[4]
5
6
7
8
9
10
11
Figure 2. 28-Lead PLCC (Top View)
9
10
11
12
13
14
15
16
N/C
N[0]
M[3]
3
M[2]
N[1]
22
M[1]
23
16
M[0]
2
28
P_LOAD
N/C
OE
24
XTAL2
1
S_LOAD
N[0] S_CLOCK
S_DATA
M[8]
S_LOAD
M[3]
17
M[2]
27
M[1]
S_DATA
M[0]
N[1]
P_LOAD
18
OE
26
XTAL2
S_CLOCK
Figure 3. 32-Lead LQFP (Top View)
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2
NBC12430
The following gives a brief description of the functionality of the NBC12430 Inputs and Outputs. Unless explicitly stated,
all inputs are CMOS/TTL compatible with either pull-up or pull-down resistors. The PECL outputs are capable of driving two
series terminated 50 transmission lines on the incident edge.
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PIN FUNCTION DESCRIPTION
Pin Name
Function
Description
INPUTS
XTAL1, XTAL2
Crystal Inputs
These pins form an oscillator when connected to an external series-resonant
crystal.
S_LOAD*
CMOS/TTL Serial Latch Input
(Internal Pulldown Resistor)
This pin loads the configuration latches with the contents of the shift registers. The
latches will be transparent when this signal is HIGH; thus, the data must be stable
on the HIGH-to-LOW transition of S_LOAD for proper operation.
S_DATA*
CMOS/TTL Serial Data Input
(Internal Pulldown Resistor)
This pin acts as the data input to the serial configuration shift registers.
S_CLOCK*
CMOS/TTL Serial Clock Input
(Internal Pulldown Resistor)
This pin serves to clock the serial configuration shift registers. Data from S_DATA
is sampled on the rising edge.
P_LOAD**
CMOS/TTL Parallel Latch Input
(Internal Pullup Resistor)
This pin loads the configuration latches with the contents of the parallel inputs
.The latches will be transparent when this signal is LOW; therefore, the parallel
data must be stable on the LOW-to-HIGH transition of P_LOAD for proper operation.
M[8:0]**
CMOS/TTL PLL Loop Divider
Inputs (Internal Pullup Resistor)
These pins are used to configure the PLL loop divider. They are sampled on the
LOW-to-HIGH transition of P_LOAD. M[8] is the MSB, M[0] is the LSB.
N[1:0]**
CMOS/TTL Output Divider Inputs
(Internal Pullup Resistor)
These pins are used to configure the output divider modulus. They are sampled
on the LOW-to-HIGH transition of P_LOAD.
OE**
CMOS/TTL Output Enable Input
(Internal Pullup Resistor)
Active HIGH Output Enable. The Enable is synchronous to eliminate possibility of
runt pulse generation on the FOUT output.
FREF_EXT*
CMOS/TTL Input
(Internal Pulldown Resistor)
This pin can be used as the PLL Reference
XTAL_SEL**
CMOS/TTL Input
(Internal Pullup Resistor)
This pin selects between the crystal and the FREF_EXT source for the PLL reference signal. A HIGH selects the crystal input.
FOUT, FOUT
PECL Differential Outputs
These differential, positive-referenced ECL signals (PECL) are the outputs of the
synthesizer.
TEST
PECL Output
The function of this output is determined by the serial configuration bits T[2:0].
VCC
Positive Supply for the Logic
The positive supply for the internal logic and output buffer of the chip, and is connected to +3.3 V or +5.0 V.
PLL_VCC
Positive Supply for the PLL
This is the positive supply for the PLL and is connected to +3.3 V or +5.0 V.
GND
Negative Power Supply
These pins are the negative supply for the chip and are normally all connected to
ground.
OUTPUTS
POWER
* When left Open, these inputs will default LOW.
** When left Open, these inputs will default HIGH.
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3
NBC12430
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
37.5 k
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity (Note 1)
> 2 kV
> 150 V
> 1 kV
PLCC
LQFP
Flammability Rating
Oxygen Index: 28 to 34
Level 1
Level 2
UL 94 V-0 @ 0.125 in
Transistor Count
2011
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2)
Parameter
Symbol
Condition 1
Condition 2
Rating
Units
VCC
Positive Supply
GND = 0 V
-
6
V
VI
Input Voltage
GND = 0 V
VI VCC
6
V
Iout
Output Current
Continuous
Surge
-
50
100
mA
mA
TA
Operating Temperature Range
-
-
0 to +70
°C
Tstg
Storage Temperature Range
-
-
-65 to +150
°C
JA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
28 PLCC
28 PLCC
63.5
43.5
°C/W
°C/W
JC
Thermal Resistance (Junction to Case)
Standard Board
28 PLCC
22 to 26
°C/W
JA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
32 LQFP
32 LQFP
80
55
°C/W
°C/W
JC
Thermal Resistance (Junction to Case)
Standard Board
32 LQFP
12 to 17
°C/W
Tsol
Wave Solder
<2 to 3 sec @ 248°C
-
265
°C
2. Maximum Ratings are those values beyond which device damage may occur.
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4
NBC12430
DC CHARACTERISTICS (VCC = 3.3 V ± 5%)
0°C
Symbol
Characteristic
25°C
70°C
Condition
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
VIH
LVCMOS/
LVTTL
Input HIGH Voltage
VCC = 3.3 V
2.0
-
-
2.0
-
-
2.0
-
-
V
VIL
LVCMOS/
LVTTL
Input LOW Voltage
VCC = 3.3 V
-
-
0.8
-
-
0.8
-
-
0.8
V
IIN
Input Current
-
-
1.0
-
-
1.0
-
-
1.0
mA
VOH
PECL
Output HIGH Voltage
FOUT
FOUT
TEST
VCC = 3.3 V
(Notes 3, 4)
2.155
-
2.405
2.155
-
2.405
2.155
-
2.405
V
VOL
PECL
Output LOW Voltage
FOUT
FOUT
TEST
VCC = 3.3 V
(Notes 3, 4)
1.355
-
1.605
1.355
-
1.605
1.355
-
1.605
V
ICC
Power Supply Current
VCC
PLL_VCC
45
17
57
30
80
30
45
17
58
24
80
30
45
17
61
25
80
30
mA
mA
3. FOUT/FOUT and TEST output levels will vary 1:1 with VCC variation.
4. FOUT/FOUT and TEST outputs are terminated through a 50 resistor to VCC - 2.0 V.
DC CHARACTERISTICS (VCC = 5.0 V ± 5%)
0°C
Symbol
Characteristic
25°C
70°C
Condition
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
VIH
CMOS/
TTL
Input HIGH Voltage
VCC = 5.0 V
2.0
-
-
2.0
-
-
2.0
-
-
V
VIL
CMOS/
TTL
Input LOW Voltage
VCC = 5.0 V
-
-
0.8
-
-
0.8
-
-
0.8
V
IIN
Input Current
-
-
1.0
-
-
1.0
-
-
1.0
mA
VOH
PECL
Output HIGH Voltage
FOUT
FOUT
TEST
VCC = 5.0 V
(Notes 5, 6)
3.855
-
4.105
3.855
-
4.105
3.855
-
4.105
V
VOL
PECL
Output LOW Voltage
FOUT
FOUT
TEST
VCC = 5.0 V
(Notes 5, 6)
3.055
-
3.305
3.055
-
3.305
3.055
-
3.305
V
ICC
Power Supply Current
VCC
PLL_VCC
50
18
58
24
85
30
50
18
60
24
85
30
50
18
64
24
85
30
mA
mA
5. FOUT/FOUT and TEST output levels will vary 1:1 with VCC variation.
6. FOUT/FOUT and TEST outputs are terminated through a 50 resistor to VCC - 2.0 V.
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5
NBC12430
AC CHARACTERISTICS (VCC = 3.135 V to 5.25 V ± 5%; TA = 0° to 70°C) (Note 8)
Characteristic
Symbol
Condition
S_CLOCK
XTAL Oscillator
FREF_EXT
(Note 7)
Min
Max
Unit
10
10
10
20
(Note 9)
MHz
400
50
800
800
MHz
-
10
ms
-
20
ps
FMAXI
Maximum Input Frequency
FMAXO
Maximum Output Frequency
tLOCK
Maximum PLL Lock Time
tjitter
Cycle-to-Cycle Jitter (Peak-to-Peak)
ts
Setup Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to P_LOAD
20
20
20
-
ns
th
Hold Time
S_DATA to S_CLOCK
M, N to P_LOAD
20
20
-
ns
tpwMIN
Minimum Pulse Width
S_LOAD
P_LOAD
50
50
-
ns
DCO
Output Duty Cycle
47.5
52.5
%
tr, tf
Output Rise/Fall
175
425
ps
VCO (Internal)
FOUT
(1)
See Applications Section
FOUT
20%-80%
7. 10 MHz is the maximum frequency to load the feedback divide registers. S_CLOCK can be switched at higher frequencies when used as
a test clock in TEST_MODE 6.
8. FOUT/FOUT and TEST outputs are terminated through a 50 resistor to VCC - 2.0 V.
9. Maximum frequency on FREF_EXT is a function of setting the appropriate M counter value, 160 MHz M 511 MHz, for the VCO to
operate within the valid range of 400 MHz fVCO 800 MHz. The internal phase detector can handle up to 100 MHz on its input.
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6
NBC12430
FUNCTIONAL DESCRIPTION
The internal oscillator uses the external quartz crystal as
the basis of its frequency reference. The output of the
reference oscillator is divided by 16 before being sent to the
phase detector. With a 16 MHz crystal, this provides a
reference frequency of 1 MHz. Although this data sheet
illustrates functionality only for a 16 MHz crystal, Table 3,
any crystal in the 10-20 MHz range can be used, Table 5.
The VCO within the PLL operates over a range of 400 to
800 MHz. Its output is scaled by a divider that is configured
by either the serial or parallel interfaces. The output of this
loop divider is also applied to the phase detector.
The phase detector and the loop filter force the VCO
output frequency to be M times the reference frequency by
adjusting the VCO control voltage. Note that for some
values of M (either too high or too low), the PLL will not
achieve loop lock.
The output of the VCO is also passed through an output
divider before being sent to the PECL output driver. This
output divider (N divider) is configured through either the
serial or the parallel interfaces and can provide one of four
division ratios (1, 2, 4, or 8). This divider extends the
performance of the part while providing a 50% duty cycle.
The output driver is driven differentially from the output
divider and is capable of driving a pair of transmission lines
terminated into 50 to VCC-2.0 V. The positive reference
for the output driver and the internal logic is separated from
the power supply for the phase-locked loop to minimize
noise induced jitter.
The configuration logic has two sections: serial and
parallel. The parallel interface uses the values at the M[8:0]
and N[1:0] inputs to configure the internal counters.
Normally upon system reset, the P_LOAD input is held
LOW until sometime after power becomes valid. On the
LOW-to-HIGH transition of P_LOAD, the parallel inputs
are captured. The parallel interface has priority over the
serial interface. Internal pull-up resistors are provided on
the M[8:0] and N[1:0] inputs to reduce component count in
the application of the chip.
The serial interface logic is implemented with a fourteen
bit shift register scheme. The register shifts once per rising
edge of the S_CLOCK input. The serial input S_DATA must
meet setup and hold timing as specified in the AC
Characteristics section of this document. With P_LOAD
held high, the configuration latches will capture the value of
the shift register on the HIGH-to-LOW edge of the
S_LOAD input. See the programming section for more
information.
The TEST output reflects various internal node values and
is controlled by the T[2:0] bits in the serial data stream. See
the programming section for more information.
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Table 3. Programming VCO Frequency Function Table
VCO
Frequency
Freq
ency
(MHz)
256
128
64
32
16
8
4
2
1
M Count*
M8
M7
M6
M5
M4
M3
M2
M1
M0
400
200
0
1
1
0
0
1
0
0
0
402
201
0
1
1
0
0
1
0
0
1
404
202
0
1
1
0
0
1
0
1
0
406
203
0
1
1
0
0
1
0
1
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
794
397
1
1
0
0
0
1
1
0
1
796
398
1
1
0
0
0
1
1
1
0
798
399
1
1
0
0
0
1
1
1
1
800
400
1
1
0
0
1
0
0
0
0
*With 16 MHz crystal.
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7
NBC12430
PROGRAMMING INTERFACE
The input frequency and the selection of the feedback
divider M is limited by the VCO frequency range and
fXTAL. M must be configured to match the VCO frequency
range of 400 to 800 MHz in order to achieve stable PLL
operation.
Programming the NBC12430 is accomplished by
properly configuring the internal dividers to produce the
desired frequency at the outputs. The output frequency can
by represented by this formula:
FOUT (FXTAL 16) 2M N
(eq. 1)
where FXTAL is the crystal frequency, M is the loop divider
modulus, and N is the output divider modulus. Note that it
is possible to select values of M such that the PLL is unable
to achieve loop lock. To avoid this, always make sure that M
is selected to be 200 ≤ M ≤ 400 for a 16 MHz input reference.
Assuming that a 16 MHz reference frequency is used the
above equation reduces to:
FOUT 2M N
(eq. 2)
Substituting the four values for N (1, 2, 4, 8) yields:
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Table 4. Programmable Output Divider Function Table
N1
N0
N Divider
FOUT
Output Frequency
Range (MHz)*
1
1
1
M2
400-800
0
0
2
M
200-400
0
1
4
M 2
100-200
1
0
8
M 4
50-100
*For crystal frequency of 16 MHz.
The user can identify the proper M and N values for the
desired frequency from the above equations. The four output
frequency ranges established by N are 400- 800 MHz,
200- 400 MHz, 100- 200 MHz and 50- 100 MHz, respectively.
From these ranges, the user will establish the value of N
required. The value of M can then be calculated based on
equation 1. For example, if an output frequency of 131 MHz
was desired, the following steps would be taken to identify the
appropriate M and N values. 131 MHz falls within the
frequency range set by an N value of 4; thus, N [1:0] = 01.
For N = 4, FOUT = M ÷ 2 and M = 2 x FOUT. Therefore,
M = 131 x 2 = 262, so M[8:0] = 100000110. Following this
same procedure, a user can generate any whole frequency
desired between 50 and 800 MHz. Note that for N > 2,
fractional values of FOUT can be realized. The size of the
programmable frequency steps (and thus, the indicator of the
fractional output frequencies achievable) will be equal to
FXTAL ÷ 16 ÷ N.
For input reference frequencies other than 16 MHz, see
Table 5, which shows the usable VCO frequency and M
divider range.
(eq. 3)
M max fVCOmax 2(fXTAL 16)
(eq. 4)
The value for M falls within the constraints set for PLL
stability. If the value for M fell outside of the valid range, a
different N value would be selected to move M in the
appropriate direction.
The M and N counters can be loaded either through a
parallel or serial interface. The parallel interface is
controlled via the P_LOAD signal such that a LOW to HIGH
transition will latch the information present on the M[8:0]
and N[1:0] inputs into the M and N counters. When the
P_LOAD signal is LOW, the input latches will be
transparent and any changes on the M[8:0] and N[1:0] inputs
will affect the FOUT output pair. To use the serial port, the
S_CLOCK signal samples the information on the S_DATA
line and loads it into a 14 bit shift register. Note that the
P_LOAD signal must be HIGH for the serial load operation
to function. The Test register is loaded with the first three
bits, the N register with the next two, and the M register with
the final nine bits of the data stream on the S_DATA input.
For each register, the most significant bit is loaded first (T2,
N1, and M8). A pulse on the S_LOAD pin after the shift
register is fully loaded will transfer the divide values into the
counters. The HIGH to LOW transition on the S_LOAD
input will latch the new divide values into the counters.
Figures 4 and 5 illustrate the timing diagram for both a
parallel and a serial load of the NBC12430 synthesizer.
M[8:0] and N[1:0] are normally specified once at
power-up through the parallel interface, and then possibly
again through the serial interface. This approach allows the
application to come up at one frequency and then change or
fine-tune the clock as the ability to control the serial
interface becomes available.
The TEST output provides visibility for one of the several
internal nodes as determined by the T[2:0] bits in the serial
configuration stream. It is not configurable through the
parallel interface. The T2, T1, and T0 control bits are preset
to ‘000’ when P_LOAD is LOW so that the PECL FOUT
outputs are as jitter-free as possible. Any active signal on the
TEST output pin will have detrimental affects on the jitter
of the PECL output pair. In normal operations, jitter
specifications are only guaranteed if the TEST output is
static. The serial configuration port can be used to select one
of the alternate functions for this pin.
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8
M min fVCOmin 2(fXTAL 16) and
NBC12430
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁ
Table 5. NBC12430 Frequency Operating Range
Output Frequency (MHz) for
fXTAL = 16 MHz and for N =
VCO Frequency (MHz) Range for a Crystal Frequency (MHz) of:
1
2
4
8
500
400
200
100
50
472.5
525
420
210
105
52.5
440
495
550
440
220
110
55
402.5
460
517.5
575
460
230
115
57.5
011110000
420
480
540
600
480
240
120
60
011111010
437.5
500
562.5
625
500
250
125
62.5
260
100000100
455
520
585
650
520
260
130
65
270
100001110
405
472.5
540
607.5
675
540
270
135
67.5
280
100011000
420
490
560
630
700
560
280
140
70
290
100100010
435
507.5
580
652.5
725
580
290
145
72.5
300
100101100
450
525
600
675
750
600
300
150
75
310
100110110
465
542.5
620
697.5
775
620
310
155
77.5
320
101000000
400
480
560
640
720
800
640
320
160
80
330
101001010
412.5
495
577.5
660
742.5
660
330
165
82.5
340
101010100
425
510
595
680
765
680
340
170
85
350
101011110
437.5
525
612.5
700
787.5
700
350
175
87.5
360
101101000
450
540
630
720
720
360
180
90
370
101110010
462.5
555
647.5
740
740
370
185
92.5
380
101111100
475
570
665
760
760
380
190
95
390
110000110
487.5
585
682.5
780
780
390
195
97.5
400
110010000
500
600
700
800
800
400
200
100
410
110011010
512.5
615
717.5
420
110100100
525
630
735
430
110101110
537.5
645
752.5
440
110111000
550
660
770
450
111000010
562.5
675
787.5
460
111001100
575
690
470
111010110
587.5
705
480
111100000
600
720
490
111101010
612.5
735
500
111110100
625
750
510
111111110
637.5
765
M
M[8:0]
10
12
14
16
160
010100000
400
170
010101010
425
180
010110100
405
450
190
010111110
427.5
475
200
011001000
400
450
210
011010010
420
220
011011100
230
011100110
240
250
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9
18
20
NBC12430
Most of the signals available on the TEST output pin are
useful only for performance verification of the NBC12430
itself. However, the PLL bypass mode may be of interest at
the board level for functional debug. When T[2:0] is set to
110, the NBC12430 is placed in PLL bypass mode. In this
mode the S_CLOCK input is fed directly into the M and N
dividers. The N divider drives the FOUT differential pair
and the M counter drives the TEST output pin. In this mode
the S_CLOCK input could be used for low speed board level
functional test or debug. Bypassing the PLL and driving
FOUT directly gives the user more control on the test clocks
sent through the clock tree. Figure 6 shows the functional
setup of the PLL bypass mode. Because the S_CLOCK is a
CMOS level the input frequency is limited to 250 MHz or
less. This means the fastest the FOUT pin can be toggled via
the S_CLOCK is 250 MHz as the minimum divide ratio of
the N counter is 1. Note that the M counter output on the
TEST output will not be a 50% duty cycle due to the way the
divider is implemented.
T2
T1
T0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
TEST (Pin 20)
SHIFT REGISTER OUT
HIGH
FREF
M COUNTER OUT
FOUT
LOW
PLL BYPASS
FOUT 4
M[8:0]
N[1:0]
M, N
P_LOAD
Figure 4. Parallel Interface Timing Diagram
S_CLOCK
T2 T1
S_DATA
T0
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
First
Bit
S_LOAD
M0
Last
Bit
Figure 5. Serial Interface Timing Diagram
FREF_EXT
MCNT
VCO_CLK
PLL 12430
0
N
(1, 2, 4, 8)
1
SCLOCK
FOUT
(VIA ENABLE GATE)
SEL_CLK
M COUNTER
LATCH
Reset
SDATA
SHIFT
REG
T0
14- BIT
T1
T2
SLOAD
PLOAD
FDIV4
MCNT
LOW
FOUT
MCNT
FREF
HIGH
7
TEST
MUX
0
DECODE
•
•
T2=T1=1, T0=0: Test Mode
SCLOCK is selected, MCNT is on TEST output, SCLOCK N is on FOUT pin.
PLOAD acts as reset for test pin latch. When latch reset, T2 data is shifted out TEST pin.
Figure 6. Serial Test Clock Block Diagram
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10
TEST
NBC12430
APPLICATIONS INFORMATION
Using the On-Board Crystal Oscillator
Power Supply Filtering
The NBC12430 features a fully integrated on-board
crystal oscillator to minimize system implementation costs.
The oscillator is a series resonant, multivibrator type design
as opposed to the more common parallel resonant oscillator
design. The series resonant design provides better stability
and eliminates the need for large on chip capacitors. The
oscillator is totally self contained so that the only external
component required is the crystal. As the oscillator is
somewhat sensitive to loading on its inputs, the user is
advised to mount the crystal as close to the NBC12430 as
possible to avoid any board level parasitics. To facilitate
co-location, surface mount crystals are recommended, but
not required. Because the series resonant design is affected
by capacitive loading on the crystal terminals, loading
variation introduced by crystals from different vendors
could be a potential issue. For crystals with a higher shunt
capacitance, it may be required to place a resistance across
the terminals to suppress the third harmonic. Although
typically not required, it is a good idea to layout the PCB
with the provision of adding this external resistor. The
resistor value will typically be between 500 and 1 K.
The oscillator circuit is a series resonant circuit and thus,
for optimum performance, a series resonant crystal should
be used. Unfortunately, most crystals are characterized in a
parallel resonant mode. Fortunately, there is no physical
difference between a series resonant and a parallel resonant
crystal. The difference is purely in the way the devices are
characterized. As a result, a parallel resonant crystal can be
used with the NBC12430 with only a minor error in the
desired frequency. A parallel resonant mode crystal used in
a series resonant circuit will exhibit a frequency of
oscillation a few hundred ppm lower than specified (a few
hundred ppm translates to kHz inaccuracies). In a general
computer application, this level of inaccuracy is immaterial.
Table 6 below specifies the performance requirements of the
crystals to be used with the NBC12430.
The NBC12430 is a mixed analog/digital product and as
such, it exhibits some sensitivities that would not necessarily
be seen on a fully digital product. Analog circuitry is
naturally susceptible to random noise, especially if this noise
is seen on the power supply pins. The NBC12430 provides
separate power supplies for the digital circuitry (VCC) and
the internal PLL (PLL_VCC) of the device. The purpose of
this design technique is to try and isolate the high switching
noise of the digital outputs from the relatively sensitive
internal analog phase-locked loop. In a controlled
environment such as an evaluation board, this level of
isolation is sufficient. However, in a digital system
environment where it is more difficult to minimize noise on
the power supplies, a second level of isolation may be
required. The simplest form of isolation is a power supply
filter on the PLL_VCC pin for the NBC12430.
Figure 7 illustrates a typical power supply filter scheme.
The NBC12430 is most susceptible to noise with spectral
content in the 1 KHz to 1 MHz range. Therefore, the filter
should be designed to target this range. The key parameter
that needs to be met in the final filter design is the DC voltage
drop that will be seen between the VCC supply and the
PLL_VCC pin of the NBC12430. From the data sheet, the
PLL_VCC current (the current sourced through the
PLL_VCC pin) is typically 24 mA (30 mA maximum).
Assuming that a minimum of 2.8 V must be maintained on
the PLL_VCC pin, very little DC voltage drop can be
tolerated when a 3.3 V VCC supply is used. The resistor
shown in Figure 7 must have a resistance of 10-15 to meet
the voltage drop criteria. The RC filter pictured will provide
a broadband filter with approximately 100:1 attenuation for
noise whose spectral content is above 20 KHz. As the noise
frequency crosses the series resonant point of an individual
capacitor, it’s overall impedance begins to look inductive
and thus increases with increasing frequency. The parallel
capacitor combination shown ensures that a low impedance
path to ground exists for frequencies well above the
bandwidth of the PLL.
Table 6. Crystal Specifications
Parameter
Value
Crystal Cut
Fundamental AT Cut
Resonance
Series Resonance*
Frequency Tolerance
±75 ppm at 25°C
Frequency/Temperature Stability
±150 ppm 0 to 70°C
Operating Range
0 to 70°C
Shunt Capacitance
5-7 pF
Equivalent Series Resistance (ESR)
50 to 80 Correlation Drive Level
100 W
Aging
5 ppm/Yr
(First 3 Years)
3.3 V or
5.0 V
3.3 V or
5.0 V
RS = 10-15 PLL_VCC
22 F
NBC12430
0.01 F
VCC
0.01 F
* See accompanying text for series versus parallel resonant
discussion.
Figure 7. Power Supply Filter
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11
L=1000 H
R=15 NBC12430
between VCC and GND for the bypass capacitors.
Combining good quality general purpose chip capacitors
with good PCB layout techniques will produce effective
capacitor resonances at frequencies adequate to supply the
instantaneous switching current for the NBC12430 outputs.
It is imperative that low inductance chip capacitors are used.
It is equally important that the board layout not introduce
any of the inductance saved by using the leadless capacitors.
Thin interconnect traces between the capacitor and the
power plane should be avoided and multiple large vias
should be used to tie the capacitors to the buried power
planes. Fat interconnect and large vias will help to minimize
layout induced inductance and thus maximize the series
resonant point of the bypass capacitors.
A higher level of attenuation can be achieved by replacing
the resistor with an appropriate valued inductor. Figure 7
shows a 1000 H choke. This value choke will show a
significant impedance at 10 KHz frequencies and above.
Because of the current draw and the voltage that must be
maintained on the PLL_VCC pin, a low DC resistance
inductor is required (less than 15 ). Generally, the
resistor/capacitor filter will be cheaper, easier to implement,
and provide an adequate level of supply filtering.
The NBC12430 provides sub-nanosecond output edge
rates and therefore a good power supply bypassing scheme
is a must. Figure 8 shows a representative board layout for
the NBC12430. There exists many different potential board
layouts and the one pictured is but one. The important aspect
of the layout in Figure 8 is the low impedance connections
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
C1
ÉÉ
ÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
C1
R1
1
C3
C2
R1 = 10-15 C1 = 0.01 F
C2 = 22 F
C3 = 0.1 F
XTAL
ÉÉ
ÉÉ
= VCC
= GND
= Via
Figure 8. PCB Board Layout for NBC12430 (28 PLCC)
Although the NBC12430 has several design features to
minimize the susceptibility to power supply noise (isolated
power and grounds and fully differential PLL), there still
may be applications in which overall performance is being
degraded due to system power supply noise. The power
supply filter and bypass schemes discussed in this section
should be adequate to eliminate power supply noise-related
problems in most designs.
Note the dotted lines circling the crystal oscillator
connection to the device. The oscillator is a series resonant
circuit and the voltage amplitude across the crystal is
relatively small. It is imperative that no actively switching
signals cross under the crystal as crosstalk energy coupled
to these lines could significantly impact the jitter of the
device. Special attention should be paid to the layout of the
crystal to ensure a stable, jitter free interface between the
crystal and the on-board oscillator. Note the provisions for
placing a resistor across the crystal oscillator terminals as
discussed in the crystal oscillator section of this data sheet.
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12
NBC12430
Jitter Performance of the NBC12430
Care must be taken that the measured edge is the edge
immediately following the trigger edge. These scopes can
also store a finite number of period durations and
post-processing software can analyze the data to find the
maximum and minimum periods.
Recent hardware and software developments have
resulted in advanced jitter measurement techniques. The
Tektronix TDS-series oscilloscopes have superb jitter
analysis capabilities on non-contiguous clocks with their
histogram and statistics capabilities. The Tektronix
TDSJIT2/3 Jitter Analysis software provides many key
timing parameter measurements and will extend that
capability by making jitter measurements on contiguous
clock and data cycles from single-shot acquisitions.
M1 by Amherst was used as well and both test methods
correlated.
This test process can be correlated to earlier test methods
and is more accurate. All of the jitter data reported on the
NBC12430 was collected in this manner. Figure 11 shows
the jitter as a function of the output frequency. The graph
shows that for output frequencies from 25 to 400 MHz the
jitter falls within the 20 ps peak-to-peak specification.
The general trend is that as the output frequency is increased,
the output edge jitter will decrease.
Figure 12 illustrates the RMS jitter performance of the
NBC12430 across its specified VCO frequency range. Note
that the jitter is a function of both the output frequency as
well as the VCO frequency. However, the VCO frequency
shows a much stronger dependence. The data presented has
not been compensated for trigger jitter.
Long-Term Period Jitter is the maximum jitter
observed at the end of a period’s edge when compared to the
position of the perfect reference clock’s edge and is specified
by the number of cycles over which the jitter is measured.
The number of cycles used to look for the maximum jitter
varies by application but the JEDEC spec is 10,000 observed
cycles.
The NBC12430 exhibits long term and cycle-to-cycle
jitter, which rivals that of SAW based oscillators. This jitter
performance comes with the added flexibility associated
with a synthesizer over a fixed frequency oscillator. The
jitter data presented should provide users with enough
information to determine the effect on their overall timing
budget. The jitter performance meets the needs of most
system designs while adding the flexibility of frequency
margining and field upgrades. These features are not
available with a fixed frequency SAW oscillator.
Jitter is a common parameter associated with clock
generation and distribution. Clock jitter can be defined as the
deviation in a clock’s output transition from its ideal
position.
Cycle-to-Cycle Jitter (short-term) is the period
variation between two adjacent cycles over a defined
number of observed cycles. The number of cycles observed
is application dependent but the JEDEC specification is
1000 cycles.
T0
T1
TJITTER(cycle- cycle) = T1 - T0
Figure 9. Cycle-to-Cycle Jitter
RMS
or one
Sigma
Jitter
Time
Typical
Gaussian
Distribution
Peak-to-Peak Jitter (6 sigma)
Jitter Amplitude
Peak-to-Peak Jitter is the difference between the
highest and lowest acquired value and is represented as the
width of the Gaussian base.
Figure 10. Peak-to-Peak Jitter
There are different ways to measure jitter and often they
are confused with one another. The typical method of
measuring jitter is to look at the timing signal with an
oscilloscope and observe the variations in period-to-period
or cycle-to-cycle. If the scope is set up to trigger on every
rising or falling edge, set to infinite persistence mode and
allowed to trace sufficient cycles, it is possible to determine
the maximum and minimum periods of the timing signal.
Digital scopes can accumulate a large number of cycles,
create a histogram of the edge placements and record
peak-to-peak as well as standard deviations of the jitter.
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13
25
25
20
20
RMS JITTER (ps)
RMS JITTER (ps)
NBC12430
15
10
N=8
N=4
15
10
5
5
N=1
N=2
0
400
0
500
600
700
800
100
VCO FREQUENCY (MHz)
200
300
400
500
600
700
OUTPUT FREQUENCY (MHz)
Figure 12. RMS Jitter vs. Output Frequency
Figure 11. RMS Jitter vs. VCO Frequency
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14
800
NBC12430
S_DATA
S_CLOCK
tHOLD
tSET- UP
Figure 13. Set-Up and Hold
S_DATA
S_LOAD
tHOLD
tSET- UP
Figure 14. Set-Up and Hold
M[8:0]
N[1:0]
P_LOAD
tHOLD
tSET- UP
Figure 15. Set-Up and Hold
FOUT
FOUT
Pulse Width
tPERIOD
Figure 16. Output Duty Cycle
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15
DCO pw
PERIOD
NBC12430
FOUT
D
Receiver
Device
Driver
Device
FOUT
D
50 50 V TT
V TT = V CC - 2.0 V
Figure 17. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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16
NBC12430
PACKAGE DIMENSIONS
PLCC-28
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776-02
ISSUE E
0.007 (0.180)
B
Y BRK
-N-
M
T L−M
0.007 (0.180)
U
M
N
S
T L−M
S
S
N
S
D
Z
-M-
-L-
W
28
D
X
0.010 (0.250)
G1
T L−M
S
N
S
S
V
1
VIEW D-D
A
0.007 (0.180)
R
0.007 (0.180)
Z
C
M
M
T L−M
T L−M
S
S
N
N
S
0.007 (0.180)
H
0.004 (0.100)
J
0.010 (0.250)
S
-T-
T L−M
S
N
N
S
S
K
SEATING
PLANE
F
VIEW S
G1
T L−M
K1
E
G
M
S
S
VIEW S
NOTES:
1. DATUMS −L−, −M−, AND −N− DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM −T−, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.485
0.495
0.485
0.495
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
−−−
0.025
−−−
0.450
0.456
0.450
0.456
0.042
0.048
0.042
0.048
0.042
0.056
−−−
0.020
2
10
0.410
0.430
0.040
−−−
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17
MILLIMETERS
MIN
MAX
12.32
12.57
12.32
12.57
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
−−−
0.64
−−−
11.43
11.58
11.43
11.58
1.07
1.21
1.07
1.21
1.07
1.42
−−−
0.50
2
10
10.42
10.92
1.02
−−−
0.007 (0.180)
M
T L−M
S
N
S
NBC12430
PACKAGE DIMENSIONS
A
32
A1
-T-, -U-, -Z-
LQFP-32
FA SUFFIX
PLASTIC LQFP PACKAGE
CASE 873A-02
ISSUE A
4X
25
0.20 (0.008) AB T−U Z
1
AE
-U-
-TB
P
V
17
8
BASE
METAL
DETAIL Y
V1
ÉÉ
ÉÉ
ÉÉ
ÉÉ
-Z9
S1
4X
0.20 (0.008) AC T−U Z
F
S
8X
M
J
R
D
DETAIL AD
G
SECTION AE-AE
-AB-
C E
-AC-
H
W
K
X
DETAIL AD
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE −AB− IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS −T−, −U−, AND −Z− TO BE DETERMINED
AT DATUM PLANE −AB−.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE −AC−.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE −AB−.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
DIM
A
A1
B
B1
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
S1
V
V1
W
X
http://onsemi.com
18
MILLIMETERS
MIN
MAX
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
1.400
1.600
0.300
0.450
1.350
1.450
0.300
0.400
0.800 BSC
0.050
0.150
0.090
0.200
0.500
0.700
12 REF
0.090
0.160
0.400 BSC
1
5
0.150
0.250
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
INCHES
MIN
MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
0.055
0.063
0.012
0.018
0.053
0.057
0.012
0.016
0.031 BSC
0.002
0.006
0.004
0.008
0.020
0.028
12 REF
0.004
0.006
0.016 BSC
1
5
0.006
0.010
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
Q
0.250 (0.010)
0.10 (0.004) AC
GAUGE PLANE
SEATING
PLANE
M
N
9
0.20 (0.008)
DETAIL Y
AC T−U Z
AE
B1
NBC12430
Notes
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19
NBC12430
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