NIS5101 Advance Information SMART HotPlug IC/Inrush Limiter/Circuit Breaker The SMART HotPlug Integrated Circuit combines the control function and power FET into a single IC that saves design time and reduces the number of components required for a complete hot swap application. It is designed to allow safe insertion and removal of electronic equipment to −48 volt backplanes. This chip features simplicity of use combined with an integrated solution. The SMART HotPlug includes user selectable undervoltage and overvoltage lockout levels. It also has adjustable current limiting that can be reduced from the maximum level with a single resistor. Operation at the maximum current level requires no extra external components. An internal temperature shutdown circuit greatly increases the reliability of this device. http://onsemi.com MARKING DIAGRAMS 8 S−PAK EX SUFFIX CASE 553AA 1 5101EX AYWW 7 Features • • • • • • • Integrated Power Device 100 Volt Operation Thermal Limit Protection Adjustable Current Limit No External Current Shunt Required Undervoltage & Overvoltage Lockouts 6.5 Amp Continuous Operation 8 1 X = 1 for Thermal Latch or 2 for Thermal Auto−retry A = Assembly Location Y = Year WW = Work Week VoIP (Voice over Internet Protocol) Servers −48 V Telecom Systems +24 V Wireless Base Station Power Central Office Switching Electronic Circuit Breaker 7 Input + ORDERING INFORMATION Voltage Regulator Thermal Shutdown 6 UVLO/ ENABLE 5 OVLO 4, 8 Drain Undervoltage Lockout Overvoltage Shutdown 5101BX AYWW 7 Typical Applications • • • • • D2PAK BX SUFFIX CASE 936AB 3 Current Limit Current Limit Device Package Shipping† NIS5101B1T4 D2PAK Latch Off 800 Units/Reel NIS5101B2T4 D2PAK Auto−Retry 800 Units/Reel NIS5101E1T1 S−PAK Latch Off 2000 Units/Reel NIS5101E2T1 S−PAK Auto−Retry 2000 Units/Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Input − 1, 2 Figure 1. Block Diagram This document contains information on a new product. Specifications and information herein are subject to change without notice. Semiconductor Components Industries, LLC, 2004 February, 2004 − Rev. 6 1 Publication Order Number: NIS5101/D NIS5101 PIN FUNCTION DESCRIPTIONS Pin Symbol Description 1, 2 Input − 3 Current Limit 4, 8 Drain Drain of power FET, which is also the switching node for the load. 5 OVLO The overvoltage shutdown point is programmed by a resistor from this pin to the Input + supply. 6 UVLO/ENABLE 7 Input + Negative input voltage to the device. This is used as the internal reference for the IC. This pin is shorted to the Input − pin for maximum current limit setting. If a reduced current limit level is desired, a series resistor is added between this pin and the Input − pin. A resistor from Input + to the UVLO pin adjusts the voltage at which the device will turn on. An open drain device can be connected to this pin, which will inhibit operation, when in its low impedance state. Positive input voltage to the device. MAXIMUM RATINGS (Maximum ratings are those, that, if exceeded, may cause damage to the device. Electrical Characteristics are not guaranteed over this range.) Rating Symbol Value Unit Input Voltage, Operating (Input + to Input −) Transient (1 second) Steady−State Vin V Drain Voltage, Operating (Drain to Input −) Transient (1 second) Steady−State VDD Drain Current, Continuous (TA = 25°C, 2.0 in2 Cu, double sided board, 1 oz.) IDavg 6.5 A Operating Temperature Range Tj −40 to 145 °C Non−Operating Temperature Range Tj −55 to 175 °C Lead Temperature, Soldering (10 Seconds) TL 260 °C Drain Current, Peak (Internally Limited) Ipk 20 A −0.3 to 110 −0.3 to 100 V −0.3 to 110 −0.3 to 100 Thermal Resistance, Junction−to−Air 0.5 in2 copper − SPAK 1.0 in2 copper − SPAK 0.5 in2 copper − D2PAK 1.0 in2 copper − D2PAK RJA Power Dissipation @ TA = 25°C 0.5 in2 copper − SPAK 1.0 in2 copper − SPAK 0.5 in2 copper − D2PAK 1.0 in2 copper − D2PAK Pmax °C/W 75 43 70 40 W 1.4 2.4 1.5 2.6 ESD Immunity for Device Handling (All Pins) HBM JESD22−A114−B 2.0 kV ESD Immunity Board Level (Note 1) IEC 61000−4−2 (Level 3) 6.0 kV Lightning, Surge (8 x 20 sec) (Note 1) IEC 61000−4−5 (Le el 3) (Level 2.0 kV 48 A 1. Applied between Input + and Input − pins only, and using an external 68 V bi−directional TVS device (P6SMB68AT3) connected across these pins. http://onsemi.com 2 NIS5101 ELECTRICAL CHARACTERISTICS (Tj = 25°C unless otherwise noted.) Characteristic Symbol Min Typ Max Unit POWER FET Charging Time (Turn−On to Rated Max Current) tchg − 5.0 − ms RDSon − 42 45 m IDSS − 10 − A − − 326 − pF Shutdown Temperature (Note 4) TSD 125 135 145 °C Hysteresis (Note 4) Thyst 35 40 45 °C Von 43 46 49 V Vhyst 7.0 8.0 9.0 V Von 30 33 35 V Vhyst 4.0 5.0 6.0 V VZ 15.2 16 16.8 V OVLO Threshold (Input + Increasing, RextOVLO = ) VOV 100 − − V OVLO Threshold (Input + Increasing, RextOVLO = 300 k) VOV 67 74 81 V VOVhyst 3.3 4.3 5.3 V Short Circuit Current Limit (RextILIMIT = 20 ) (D2PAK) (Note 5) ILIM1 3.8 4.5 5.2 A Short Circuit Current Limit (RextILIMIT = 20 ) (SPAK) (Note 5) ILIM1 3.4 4.0 4.6 A Overload Current Limit (RextILIMIT = 20 ) (D2PAK) (Notes 4 and 5) ILIM2 5.5 6.0 6.5 A Overload Current Limit (RextILIMIT = 20 ) (SPAK) (Notes 4 and 5) ILIM2 5.5 6.0 6.5 A Bias Current (Operational) IBias − 1.4 − mA Bias Current (Non−Operational) (Vinput = 30 V, RUVLO = ) IBias − 800 − A Vinmin − 18 − V ON Resistance Zero Gate Voltage Drain Current (VDS = 100 Vdc, VGS = 0 Vdc) Output Capacitance (VDS = 48 Vdc, VGS = 0 Vdc, f = 10 kHz) THERMAL LIMIT OVER/UNDERVOLTAGE Turn−On Voltage (RextUVLO = ) Hysteresis (RextUVLO = ) Turn−On Voltage (RextUVLO = 270 k) Hysteresis (RextUVLO = 270 k) Zener Voltage (UVLO Pin Voltage at Turn−On) OVLO Hysteresis (Input + Decreasing, RextOVLO = 300 k) CURRENT LIMIT TOTAL DEVICE Minimum Operating Voltage (RUVLO = 30 k) 2. 3. 4. 5. Pulse Test: Pulse width 300 s, duty cycle 2%. Switching characteristics are independent of operating junction temperatures. Verified by design. Please refer to explanation about the device’s current limit operation in short circuit and overload conditions. http://onsemi.com 3 NIS5101 TYPICAL PERFORMANCE CURVES (TA = 25°C unless otherwise noted) 10 10 ILimit (A) 100 ILimit (A) 100 Overload Short Circuit Overload Short Circuit 1 1 0.1 1 10 100 0.1 1 1000 10 100 1000 Rext_ILimit () Rext_ILimit () Figure 2. Current Limit Adjustment (D2PAK package) Figure 3. Current Limit Adjustment (SPAK package) 100 45 90 OVLO TRIP POINT (V) UVLO TRIP POINT (V) 40 35 30 25 80 70 60 50 40 30 20 20 15 10 10 10 1000 100 100 UVLO_Rext (k) OVLO_Rext (k) Figure 4. UVLO Adjustment 115 Figure 5. OVLO Adjustment 115 D2PAK Package SPAK Package 105 CASE TEMPERATURE (°C) 105 CASE TEMPERATURE (°C) 1000 0.5 in2 Cu area 95 1 in2 Cu area 85 2 in2 Cu area 75 65 55 45 Device Reaching Thermal Shutdown 35 0.5 in2 Cu area 95 1 in2 Cu area 85 2 in2 Cu area 75 65 55 45 Device Reaching Thermal Shutdown 35 25 25 1 2 3 4 5 6 7 1 CONTINUOUS CURRENT (A) 2 3 4 5 6 CONTINUOUS CURRENT (A) Figure 6. Continuous Current vs. Case Temperature (D2PAK Package) (Test performed on a double sided copper board, 1 oz) Figure 7. Continuous Current vs. Case Temperature (SPAK Package) (Test performed on a double sided copper board, 1 oz) http://onsemi.com 4 7 NIS5101 TYPICAL APPLICATION CIRCUIT & OPERATION WAVEFORMS (TA = 25°C unless otherwise noted) RUVLO Input + + + + UVLO NIS5101 ROVLO DC−DC Converter Drain OVLO/EN Current Limit Input − Rlimit Figure 8. Typical Application Load Capacitor 470 F Gnd Bounce Bus Voltage Load Voltage Load Current 1 A/div −48 V Figure 9. Turn On Waveforms for 470 F Load Capacitor http://onsemi.com 5 NIS5101 Load Capacitor 4200 F Gnd Bus Voltage Load Voltage Load Current 1 A/div −48 V Device Reaching Thermal Shutdown Figure 10. Typical Operation Waveforms of the Auto−Retry Device Load Capacitor 4200 F Load Voltage Gnd Bus Voltage Load Current 1 A/div −48 V Device Reaching Thermal Shutdown Figure 11. Typical Operation Waveforms of the Latch Off Device http://onsemi.com 6 NIS5101 ADDITIONAL APPLICATION CIRCUITS FOR DIFFERENT FUNCTIONS Input + + RL UVLO NIS5101 Pwr Good CL Pwr Good NUD3048 Drain NUD3048 OVLO Current Limit Input − + Figure 12. Power Good Signal Circuit 100 k Pwr Gd Input + + UVLO NIS5101 + Drain OVLO Current Limit Input − NUD3048 MM3Z5V1 Figure 13. Power Good Signal Referenced to Drain ROVLO 422 k + Input + OVLO/EN NIS5101 RUVLO + 100 F Drain UVLO Current Limit Input − + Cdelay Rlimit 20 50 RUVLO = Open 40 DELAY TIME (mS) + 30 RUVLO = 470k 20 10 0 RUVLO = 200k 0 40 80 120 160 Cdelay_UVLO pin (nF) Figure 14. Increased Delay Time Circuit http://onsemi.com 7 200 RL DC−DC Converter NIS5101 OPERATION Turn−on The SMART HotPlug monitors the input voltage by sensing the voltage across the Input + to Input − pins. When the UVLO voltage has been reached, the internal circuitry slowly charges the gate of the internal SENSEFET. There will be a slight delay of several milliseconds before the SENSEFET begins conduction. This may be increased by adding a capacitor to the UVLO pin. For a discussion of this, see application note AND8115/D. The SENSEFET will increase the load current with a controlled di/dt until the current limit level has been reached. At this point the SENSEFET will enter a constant current mode of operation until the load capacitor has been fully charged. If the thermal limit threshold is reached before the capacitor reaches its final charge level, the device will shut down until the die temperature reaches 735°C and then restart, if it is the auto−retry device. The thermal latching version must not be allowed to reach the thermal shutdown level at turn−on as this will cause it to latch in an off state. During the capacitor charging period, the dv/dt of the capacitor is: Faults Once the load capacitance is charged, the SENSEFET will become fully enhanced as long as the current does not reach the current limit threshold, or is shut−down due to an overvoltage, undervoltage or thermal fault. Both the UVLO and OVLO circuits incorporate hysteresis to assure clean turn−on and turn−offs with no chatter. The thermal latching circuit will require the input power to be recycled to resume operation after a fault. The current limit is always active, so any transient or overload will always be limited. Circuit Description Undervoltage Lockout: The UVLO circuit holds the chip off when the input voltage is less than the turn−on limit. It includes internal hysteresis to assure clean on/off switching. An internal divider sets the turn−on voltage level at 44 volts. This voltage can be reduced by adding an external resistor from the UVLO pin to the Input + pin. The equivalent circuit is shown in Figure 15. I dvdt LIMIT CLOAD Drain Input + Vreg RUVLO 200 k UVLO/ ENABLE 12.5 V 100 k Vz ZD1 50 k Input − Figure 15. Undervoltage Lockout Circuit http://onsemi.com 8 NIS5101 The equation for the UVLO turn−on voltage is: RUVLO This circuit contains an internal zener diode/resistor combination in series with the gate of a FET. When the input + to input − voltage reaches a level sufficient to apply the required gate voltage to the FET, operation of the SMART HotPlug will be inhibited. There is a hysteresis circuit built in that will eliminate on/off bursts due to noise on the input. The equation for the OVLO trip point is: 215 Vin 2970 46.8 Vin where RUVLO is in k. Input + + RL 290 Vin 3200 ROVLO 113.7 Vin CL UVLO/EN Drain OVLO + Where ROVLO is the overvoltage programming resistor from the OVLO pin to Input +, and Vin is the desired trip point for the overvoltage shutdown to occur. Similar to the undervoltage lockout circuit, the noise sensitivity of this circuit can be reduced by adding a capacitor from the OVLO pin to Input −. The capacitor required for the desired pole frequency is: Current Limit Input − Figure 16. COVLO Where Vin is the desired turn−on voltage, and RUVLO is the programming resistance from the UVLO pin to the Input + pin. To reduce nuisance tripping due to transients and noise spikes, a capacitor may be added from the UVLO pin to the Input – pin. This will create a low pass filter with a cutoff frequency of f. The required capacitance on this pin is: C Temperature Limit: The temperature limit circuit senses the temperature of the Power FET and removes the gate drive if the maximum level is exceeded. There is a nominal hysteresis of 40°C for this circuit. After a thermal shutdown, the device will automatically restart when the temperature drops to a safe level as determined by the hysteresis. Current Limit: The SMART HotPlug uses a SENSEFET to measure the Drain Current. The behavior of the SENSEFET in a short circuit condition varies from that in an overload because there is sufficient voltage across the drain to source terminals for the sense current to follow the ratio of the sense cells to main FET cells. This is not the case when the device is fully enhanced, since there are only a few millivolts from drain to source. In this condition, the sense voltage follows a different set of equations. An overload condition is one in which the FET is fully enhanced and operating at it’s minimum RDSon. A short circuit condition occurs when either the load has shorted or upon turn on, as the load capacitor to the hot swap device initially looks like a short circuit. Figure 2 shows both curves. A single resistor will determine both the short circuit and overload current. For example, a 110 resistor would result in a 1 amp current limit when charging the capacitance at turn on, but once the FET is fully enhanced, it would allow the load to operate at a current up to 2.5 amps. Once the 2.5 amp limit is reached, any further reduction in load impedance will result in a short circuit condition and the current will be reduced to 1 amp. As with all SMART HotPlug devices, the current limit will never shut down the limiter. Only the thermal limit will stop the flow of current to the load. Once the current is stopped due to the thermal limit, it will remain off until 1 2 · f 150 k R UVLO200 k R (1 31.3 · 10−6 · ROVLO) 2f · ROVLO · 200 k UVLO Overvoltage Lockout: The overvoltage shutdown circuit is an optional protection feature that can be disabled by simply grounding the OVLO pin. Drain Vreg Input + 280 k OVLO 400 k 11 V 40 k 400 k Input − Figure 17. http://onsemi.com 9 NIS5101 input power is recycled for the latching version, or it will continuously retry to start again if it is the auto−retry version. Turn−on Surge: During the turn−on event, there is a large amount of energy dissipated due to the linear operation of the power device. The energy rating is the amount of energy that the device can absorb before the thermal limit circuit will shut the unit down. This is very important specially for the latch off device as it determines the maximum load capacitance that the device can charge before the thermal limit shuts the device down. The calculation of this is not very simple as it depends on several factors such as the input voltage (Vin), load capacitance (CL), current limit settings (ILimit) and device’s thermal transient response. Figure 18 shows the device’s thermal transient response for minimum pad. THETA J(t) (°C/W) 100 10 1 0.1 0.01 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 TIME (seconds) Figure 18. Thermal Transient Response The device junction temperature (Tj) for turn−on surge conditions can be calculated by knowing the thermal transient resistance of a given pulse duration. To better illustrate this theoretical methodology, an example is explained: For the following conditions, TA = 25°C Vin = 48 V Tj = TA + [PD x RJ(t)], and RJ(t) = (Tj – TA)/PD where: Tj is the device junction temperature ILimit = 2.0 A What is the maximum load capacitance that the NIS5101 device can charge before the thermal limit circuit shuts the unit down? TA is the ambient temperature PD is the power dissipation of the device RJ(t) is the value from Figure 18 In order to obtain the thermal transient resistance value RJ(t), it is necessary to calculate the charging time of a given load capacitance (CL), the following equation is used for these purposes: i = C dV/dt; then, t = (CL/ILimit) x Vin If: RJ(t) = (Tj – TA)/PD RJ(t) = (135°C–25°C)/(48 V x 2.0 A) RJ(t) = 1.1 From Figure 18: RJ(t) = 1.1 corresponds to 80 msec Then: where: CL is the total load capacitance ILimit is the current limit value Vin is the input voltage t = (CL/ILimit) x Vin CL = (t x ILimit)/Vin CL = (0.080 x 2)/48 CL = 3,330 f By calculating the charging time, the thermal transient resistance is then given by Figure 18. And finally the device junction temperature (Tj) for turn−on surge conditions is calculated. If the calculated Tj does not exceed 135°C, then the thermal limit circuit is most likely to not shut the unit down. It is important to notice that this theoretical methodology is intended to be used only for first approximation purposes. http://onsemi.com 10 NIS5101 Enable: The UVLO pin serves a double function. In addition to the UVLO function, it can also be used to disable the chip when it is pulled to the input− rail, with an open drain type of device. The open drain device must be able to sink the current from the internal 100 k resistor in parallel with the external adjustment resistor, at the highest input voltage required. The turn on voltage at the UVLO pin is approximately 15 V, so any device that can sink the required amount of current should have a saturation voltage well below this requirement. The maximum sinking current can be calculated by the following equation: 100 k RUVLO Ienable(max) Vin(max) 100 k RUVLO http://onsemi.com 11 NIS5101 PACKAGE DIMENSIONS S−PAK 7 LEAD EX SUFFIX CASE 553AA−01 ISSUE O A A1 U K E M V B NOTES: 1. DIMENSIONS AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. PACKAGE OUTLINE EXCLUSIVE OF MOLD FLASH AND METAL BURR. 4. PACKAGE OUTLINE INCLUSIVE OF PLATING THICKNESS. 5. FOOT LENGTH MEASURED AT INTERCEPT POINT BETWEEN DATUM A AND LEAD SURFACE. H D 7 PL G DETAIL A L C N CL P W R −A− DETAIL A http://onsemi.com 12 DIM A A1 B C D E G H K L M N P R U V W INCHES MIN MAX 0.365 0.375 0.350 0.360 0.310 0.320 0.070 0.080 0.025 0.031 0.010 BSC 0.050 BSC 0.410 0.420 0.030 0.050 0.001 0.005 0.035 0.045 0.010 BSC 0.031 0.041 0 6 0.256 BCS 0.316 BSC 0.010 BSC MILLIMETERS MIN MAX 9.27 9.52 8.89 9.14 7.87 8.13 1.78 2.03 0.63 0.79 0.25 BSC 1.27 BSC 10.41 10.67 0.76 1.27 0.03 0.13 0.89 1.14 0.25 BSC 0.79 1.04 0 6 6.50 BSC 8.03 BSC 0.25 BSC NIS5101 PACKAGE DIMENSIONS D2PAK−7 BX SUFFIX CASE 936AB−01 ISSUE O For D2PAK Outline and Dimensions − Contact Factory http://onsemi.com 13 NIS5101 The product described herein (NIS5101), may be covered by U.S. patents. Other patents may be pending, including ON Semiconductor disclosures ONS00448 and ONS00458. SENSEFET and SMART HotPlug are trademarks of Semiconductor Components Industries, LLC. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. 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Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Phone: 81−3−5773−3850 Email: [email protected] http://onsemi.com 14 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. NIS5101/D