INTEGRATED CIRCUITS
P3C18V8Z40/P3C18V8ZIA
3 Volt zero standby power
universal PAL devices
Product specification
IC13 Data Handbook
1996 Oct 09
Philips Semiconductors
Product specification
3 volt zero standby power
universal PAL devices
P3C18V8Z40/P3C18V8ZIA
DESCRIPTION
APPLICATIONS
• Laptop, notebook and palm top computers
• Portable communications equipment
• Battery powered instruments
• Industrial automation/control
The P3C18V8Z is a universal PAL-type device designed to operate
specifically in a low voltage environment (3.3V). The PAL device is
available in the commercial temperature range, P3C18V8Z40, and
the industrial temperature range, P3C18V8ZIA.
These devices offer virtually zero standby power (15µA typical) as
well as very low power consumption during operation. The
P3C18V8Z automatically powers down when the inputs or the clock
are idle for greater than one full clock cycle. The device will
automatically power up from a standby mode once any input or the
clock is activated. This input transition detection circuitry makes
these devices ideal for power sensitive applications –– especially
those which are battery operated or backed up.
PIN CONFIGURATIONS
D, DB, DH, N, and FA Packages
I0/CLK
1
20 VCC
I1
2
19 F7
I2
3
18 F6
I3
4
17 F5
I4
5
16 F4
I5
6
15 F3
I6
7
14 F2
I7
8
13 F1
I8
9
12 F0
All the P3C18V8Z devices are available in plastic DIP, PLCC, Plastic
Small Outline (SOL), Plastic Shrink Small Outline (SSOP), and
Plastic Thin Shrink Small Outline (TSSOP) packages. A ceramic
DIP with a window for erasure is available for prototyping.
The P3C18V8Z is a two level logic element comprised of 10 inputs,
74 AND gates (logic and control product terms) and 8 Output Macro
Cells (OMCs). Each OMC can be configured as a dedicated input, a
combinatorial I/O or a registered output with internal feedback.
Each OMC has individual direction control (from the AND array) and
programmable output polarity. The dedicated clock and OE pins can
be configured as inputs for strictly combinatorial applications. Two
product terms control the asynchronous Reset and the synchronous
Preset functions.
GND 10
11 I9/OE
D = Plasitc Small Outline Large Package (300mil-wide)
DB = Plastic Shrink Small Outline Package (5.3mm wide)
DH = Plastic Thin Shrink Small Outline Package (4.4mm wide)
N = Plastic Dual In-Line Package (DIP) (300mil-wide)
FA = Ceramic DIP with Quartz Window (300mil-wide)
Power up Reset and Register Preload functions have also been
incorporated into the P3C18V8Z to facilitate state machine design
and testing.
A Package
The Output Macro Cell feature of the P3C18V8Z devices provides
the flexibility to emulate all 20 pin common PAL and GAL functions,
thus providing reduced documentation, inventory and manufacturing
costs. The P3C18V8Z is also pin and fuse map compatible with all
the Philips 5 Volt PLC18V8Z devices.
I2
3
FEATURES
• 20-pin Universal Programmable Array Logic (PAL), operational
over low voltage range and industrial temperature range
• Virtually zero-standby-power and very low dynamic power
I0/
I1 CLK VCC F7
2
1 20 19
I3
4
18 F6
I4
5
17 F5
I5
6
16 F4
I6
7
15 F3
I7
8
14 F2
9
– 15µA standby (typ.)
10
11
12
13
I8 GND I9/ F0 F1
OE
– 0.9 mA/MHz (worst case)
A = Plastic Leaded Chip Carrier
• Functional replacement for Series 16 PALs and GALs
SP00026A
– Highly flexible Output Macro Cell
• Available in DIP, PLCC, SOL (Small Outline), SSOP (Shrink Small
PIN DESCRIPTIONS
Outline), and TSSOP (Thin Shrink Small Outline) packages
• High performance EPROM CMOS cell technology
– 100% testable prior to programming
– Low cost OTP plastic packages
– Erasable/reconfigurable (ceramic package)
• Design support provided by most popular third party
programmable Logic CAD tools
1996 Oct 09
2
I
Dedicated Input
F
Output/Input Macrocell
CLK
Clock Input
OE
Output Enable
VCC
Supply Voltage
GND
Ground
853–1847 17376
Philips Semiconductors
Product specification
3 volt zero standby power
universal PAL devices
P3C18V8Z40/P3C18V8ZIA
ORDERING INFORMATION
TEMPERATURE
RANGE
ORDER CODE
DRAWING
NUMBER
20-Pin (300mil-wide) Plastic Dual In-Line Package
P3C18V8Z40N
SOT146-1
20-Pin (300mil-wide) Ceramic Dual In-Line Package with Quartz Window
P3C18V8Z40FA
0584B
DESCRIPTION
20-Pin (350mil square) Plastic Leaded Chip Carrier Package
P3C18V8Z40A
SOT380-1
P3C18V8Z40D
SOT163-1
20-Pin (5.3mm-wide) Plastic Shrink Small Outline Package
P3C18V8Z40DB
SOT339-1
20-Pin (4.4mm-wide) Plastic Thin Shrink Small Outline Package
Commercial
20-Pin (300mil-wide) Plastic Small Outline Large Package
P3C18V8Z40DH
SOT360-1
20-Pin (300mil-wide) Plastic Dual In-Line Package
P3C18V8ZIAN
SOT146-1
20-Pin (300mil-wide) Ceramic Dual In-Line Package with quartz window
P3C18V8ZIAFA
0584B
20-Pin (350mil square) Plastic Leaded Chip Carrier Package
P3C18V8ZIAA
SOT380-1
P3C18V8ZIAD
SOT163-1
20-Pin (5.3mm-wide) Plastic Shrink Small Outline Package
P3C18V8ZIADB
SOT339-1
20-Pin (4.4mm-wide) Plastic Thin Shrink Small Outline Package
P3C18V8ZIADH
SOT360-1
Industrial
20-Pin (300mil-wide) Plastic Small Outline Large Package
1996 Oct 09
3
Philips Semiconductors
Product specification
3 volt zero standby power
universal PAL devices
P3C18V8Z40/P3C18V8ZIA
PAL DEVICE TO P3C18V8Z OUTPUT PIN CONFIGURATION CROSS REFERENCE
PIN
NO.
P3C
18V8Z
16L8
16H8
16P8
16P8
16R4
16RP4
16R6
16RP6
16R8
16RP8
16L2
16H2
16P2
14L4
14H4
14P4
12L6
12H6
12P6
10L8
10H8
10P8
1
I0/CLK
I
CLK
CLK
CLK
I
I
I
I
19
F7
B
B
B
D
I
I
I
O
18
F6
B
B
D
D
I
I
O
O
17
F5
B
D
D
D
I
O
O
O
16
F4
B
D
D
D
O
O
O
O
15
F3
B
D
D
D
O
O
O
O
14
F2
B
D
D
D
I
O
O
O
13
F1
B
B
D
D
I
I
O
O
12
F0
B
B
B
D
I
I
I
O
11
I9/OE
I
OE
OE
OE
I
I
I
I
The Philips Semiconductors’ state-of-the-art Floating-Gate CMOS
EPROM process yields bipolar equivalent performance at less than
one-quarter the power consumption. The erasable nature of the
EPROM process enables Philips Semiconductors to functionally test
the devices prior to shipment to the customer. Additionally, this
allows Philips Semiconductors to extensively stress test, as well as
ensure the threshold voltage of each individual EPROM cell. 100%
programming yield is subsequently guaranteed.
FUNCTIONAL DIAGRAM
I0/
CLK
I0
CONFIG.
CELL
9
I1
I7
PROGRAMMABLE AND ARRAY
36 ROWS X 72 COLUMNS
I2
OMC
F7
CLK
9
OMC
F6
OMC
F1
OMC
F0
9
9
I8
SP
AR
OE
CONFIG.
CELL
I9/OE
I9
SP00013
1996 Oct 09
4
Philips Semiconductors
Product specification
3 volt zero standby power
universal PAL devices
P3C18V8Z40/P3C18V8ZIA
LOGIC DIAGRAM
0
4
8
12
16
20
24
28
32
35
I0/CLK 1
CLK
DIR
SP
19 F7
AC1
AC2
AR
I1 2
DIR
CLK
OE
SP
I2
18 F6
AC1
AC2
AR
3
DIR
CLK
OE
SP
I3
4
DIR
AC1
AC2
AR
CLK
OE
17 F5
SP
I4
5
DIR
AC1
AC2
AR
CLK
OE
16 F4
SP
I5
6
DIR
AC1
AC2
AR
CLK
OE
15 F3
SP
I6
7
DIR
AC1
AC2
AR
CLK
OE
14 F2
SP
I7
8
DIR
AC1
AC2
AR
CLK
OE
13 F1
SP
I8
AC1
AC2
AR
CLK
OE
9
SP
AR
12 F0
I1
I1
F7
F7
I2
I2
F6
F6
I3
I3
F5
F5
I4
I4
F4
F4
I5
I5
F3
F3
I6
I6
F2
F2
I7
I7
F1
F1
I8
I8
F0
F0
I0
I0
I9
I9
11 I9/OE
NOTES:
In the unprogrammed or virgin state:
All cells are in a conductive state.
All AND gate locations are pulled to a logic “0” (Low).
Output polarity is inverting.
1996 Oct 09
CONFIG.
CELL
Pins 1 and 11 are configured as Inputs 0 and 9, respectively, via the configuration cell. The clock and OE
functions are disabled.
All output macro cells (OMC) are configured as bidirectional I/O, with the outputs disabled via the direction term.
Denotes a programmable cell location.
SP00012
5
Philips Semiconductors
Product specification
3 volt zero standby power
universal PAL devices
P3C18V8Z40/P3C18V8ZIA
OUTPUT MACRO CELL (OMC)
FROM AND
ARRAY
1
DIRECTION CONTROL TERM
11
VCC 01 OE
00 MUX
SP
AR
{
FROM
AND
ARRAY
.
TO ALL OMCs
10
D
01
10 OUT
11 MUX
00
S
X(n)
OUTPUT
POLARITY
CONTROL
Q
F
CLK
AC1n
AC2n
00
F 10
MUX 11
01
TO ALL OMCs
11
OE
NOTE:
Denotes a programmable cell location.
SP00014
THE OUTPUT MACRO CELL (OMC)
DESIGN SECURITY
The P3C18V8Z series devices have 8 individually programmable
Output Macro Cells. The 72 AND inputs (or product terms) from the
programmable AND array are connected to the 8 OMCs in groups of
9. Eight of the AND terms are dedicated to logic functions; the ninth
is for asynchronous direction control, which enables/disables the
respective bidirectional I/O pin. Two product terms are dedicated for
the Synchronous Preset and Asynchronous Reset functions.
The P3C18V8Z series devices have a programmable security fuse
that controls the access to the data programmed in the device. By
using this programmable feature, proprietary designs implemented
in the device cannot be copied or retrieved.
Each OMC can be independently programmed via 16 architecture
control bits, AC1n and AC2n (one pair per macro cell). Similarly,
each OMC has a programmable output polarity control bit (Xn). By
configuring the pair of architecture control bits according to the
configuration cell table, 4 different configurations may be
implemented. Note that the configuration cell is automatically
programmed based on the OMC configuration.
1996 Oct 09
6
Philips Semiconductors
Product specification
3 volt zero standby power
universal PAL devices
P3C18V8Z40/P3C18V8ZIA
If any one OMC is configured as registered, the configuration cell
will be automatically configured (via the design software) to ensure
that the clock and output enable functions are enabled on Pins 1
and 11, respectively. If none of the OMCs are registered, the
configuration cell will be programmed such that Pins 1 and 11 are
dedicated inputs. The programming codes are as follows:
CONFIGURATION CELL
A single configuration cell controls the functions of Pins 1 and 11.
Refer to Functional Diagram. When the configuration cell is
programmed, Pin 1 is a dedicated clock and Pin 11 is dedicated for
output enable. When the configuration cell is unprogrammed, Pins 1
and 11 are both dedicated inputs. Note that the output enable for all
registered OMCs is common—from Pin 11 only. Output enable
control of the bidirectional I/O OMCs is provided from the AND array
via the direction product term.
Pin 1 = CLK, Pin 11 = OE
L
Pin 1 and Pin 11 = Input
H
CONTROL CELL CONFIGURATIONS
FUNCTION
AC11
AC2N
CONFIG. CELL
COMMENTS
Programmed
Programmed
Programmed
Dedicated clock from Pin 1. OE Control
for all registerd OMCs from Pin 11 only.
Bidirectional I/O mode
Unprogrammed
Unprogrammed
Unprogrammed
Pins 1 and 11 are dedicated inputs.
3-State control from AND array only.
Fixed input mode
Unprogrammed
Programmed
Unprogrammed
Pins 1 and 11 are dedicated inputs.
Programmed
Unprogrammed
Unprogrammed
Pins 1 and 11 are dedicated inputs. The
feedback path (via FMUX) is disabled.
Registered mode
Fixed output mode
NOTE:
1. This is the virgin state as shipped from the factory.
ARCHITECTURE CONTROL—AC1 and AC2
11
OE
DIR
SP
Q
F(D), F (D)
AR
S
S
S
F(B), F (B)
1
F(O), F (O)
CLK
OMC CONFIGURATION
REGISTERED (D–TYPE)
CODE
OMC CONFIGURATION
CODE
OMC CONFIGURATION
CODE
D
BIDIRECTIONAL I/O1
(COMBINATORIAL)
B
FIXED OUTPUT
O
1
1
SP
F (I)
CLK Q
F(D), F (D)
AR
NC
SP
CLK
Q
AR
OE
NC
OE
11
11
OMC CONFIGURATION
FIXED INPUT
CODE
CONFIGURATION CELL
I
PIN 1 = CLK
PIN 11 = OE
CODE
CONFIGURATION CELL
CODE
L
PIN 1 = INPUT
PIN 11 = INPUT
H6
SP00015
NOTES:
A factory shipped unprogrammed device is configured such that:
1. This configuration cannot be used if any OMCs are configured as registered (Code = D). The configuration cell will be automatically
configured to ensure that the clock and output enable functions are enabled on Pins 1 and 11, respectively, if any one OMC is programmed
as registered.
* All AND gates are pulled to a logic ”0” (Low).
* Output polarity is inverting.
* Pins 1 and 11 are configured as inputs 0 and 9. The clock and OE functions are disabled.
* All Output Macro Cells (OMCs) are configured as bidirectional I/O, with the outputs disabled via the direction term.
1996 Oct 09
7
Philips Semiconductors
Product specification
3 volt zero standby power
universal PAL devices
P3C18V8Z40/P3C18V8ZIA
ABSOLUTE MAXIMUM RATINGS1
RATINGS
UNIT
VCC
Supply voltage
PARAMETER
–0.5 to +6
VDC
VCC
Operating supply voltage
3.0 to 3.6
VDC
VIN
Input voltage
–0.5 to VCC +0.5
VDC
VOUT
Output voltage
–0.5 to VCC +0.5
VDC
200
ns/V maximum
–10 to +10
mA
+24
mA
–40 to +85 (Industrial)
0 to +75 (Commercial)
°C
–65 to +150
°C
SYMBOL
∆t/∆V
Input/clock transition rise or
IIN
Input currents
IOUT
Output currents
Tamb
Operating temperature range
Tstg
Storage temperature range
fall2
NOTES:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at
these or any other condition above those indicated in the operational and programming specification of the device is not implied.
2. All digital circuits can oscillate or trigger prematurely when input rise and fall times are very long. When the input signal to a device is at or
near the switching threshold, noise on the line will be amplified and can cause oscillation which, if the frequency is low enough, can cause
subsequent stages to switch and give erroneous results. For this reason, external Schmitt-triggers are recommended if rise/fall times are
likely to exceed 200ns at VCC = 3.6V.
THERMAL RATINGS
VOLTAGE WAVEFORMS
TEMPERATURE
+3.0V
Maximum junction
150°C
Maximum ambient
75°C
90%
10%
0V
Allowable thermal rise ambient to junction
75°C
tR
5ns
AC TEST CONDITIONS
tF
5ns
+3.0V
VCC
90%
+3.3V
S1
10%
0V
C1
C2
R1
I9
BW
BX
R2
DUT
GND
BZ
CL
Input Pulses
SP00017
SWITCHING WAVEFORM
OUTPUTS
INPUT
NOTES:
C1 and C2 are to bypass VCC to GND.
R1 = 200Ω R2 = 390Ω
5ns
MEASUREMENTS:
All circuit delays are measured at the +1.5V level of inputs and outputs,
unless otherwise specified.
BY
I0
INPUTS
5ns
VT
tER
SP00353
OUTPUT
tEA
VOH – 0.3V
VOL + 0.3V
VT
Input to Output Disable/Enable
SP00354
1996 Oct 09
8
Philips Semiconductors
Product specification
3 volt zero standby power
universal PAL devices
P3C18V8Z40/P3C18V8ZIA
DC ELECTRICAL CHARACTERISTICS
3.0V ≤ VCC ≤ 3.6 ranges
Commercial = 0°C ≤ Tamb ≤ +75°C
Industrial = –40°C ≤ Tamb ≤ +85°C
LIMITS
SYMBOL
PARAMETER
TEST CONDITION
MIN
TYP1
MAX
UNIT
Input voltage
VIL
Low
VCC = MIN
–0.3
0.8
V
VIH
High
VCC = MAX
2.0
VCC + 0.3
V
0.100
0.500
V
V
Output voltage2
VOL
Low
VCC = MIN, IOL = 20µA
VCC = MIN, IOL = 24mA
VOH
High
VCC = 3.0, IOH = –3.2mA
VCC = 3.0, IOH = –20µA
VCC = 3.0, IOH = –1.6µA
VCC – 0.6
VCC – 0.3
VCC – 0.3
V
V
Input current
IIL
Low5
VIN = GND
–5
µA
IIH
High
VIN = VCC
5
µA
10
–10
µA
µA
–130
mA
Output current
IO(OFF)
Hi–Z state
VOUT = VCC
VOUT = GND
IOS
Short-circuit3
VOUT = GND
ICC
VCC supply current (Standby)
VCC = MAX, VIN = 0 or VCC
15
40
µA
ICC/f
VCC supply current (Active)4
VCC = MAX
.75
0.9
mA/MHz
VCC = 5V, VIN = 2.0V
12
pF
VB = 2.0V
15
pF
6
Capacitance
CI
Input
CB
I/O
NOTES:
1. All typical values are at VCC = 3.3V, Tamb = +25°C.
2. All voltage values are with respect to network ground terminal.
3. Duration of short–circuit should not exceed one second. Test one at a time.
4. Measured with all outputs switching.
5. IIL for Pin 1 (I0/CLK) is ± 10µA with VIN = 0.4V.
6. VIN includes CLK and OE if applicable.
1996 Oct 09
9
Philips Semiconductors
Product specification
3 volt zero standby power
universal PAL devices
P3C18V8Z40/P3C18V8ZIA
AC ELECTRICAL CHARACTERISTICS
3.0V ≤ VCC ≤ 3.6V range; R2 = 390Ω
Commercial = 0°C ≤ Tamb ≤ +75°C
Industrial = –40°C ≤ Tamb ≤ +85°C
TEST CONDITION1
SYMBOL
PARAMETER
P3C18V8Z40
(Commercial)
P3C18V8ZIA
(Industrial)
MIN
FROM
TO
CL (pF)
MIN
MAX
MAX
UNIT
Pulse width
tCKP
Clock period (Minimum tIS + tCKO)
CLK +
CLK +
50
47
57
ns
tCKH
Clock width High
CLK +
CLK –
50
20
25
ns
tCKL
Clock width Low
CLK –
CLK +
50
20
25
ns
tARW
Async reset pulse width
I ±, F±
I +, F +
35
40
ns
Input or feedback data hold time
CLK +
Input ±
50
0
0
ns
I ±, F±
CLK +
50
30
35
ns
Hold time
tIH
Setup time
tIS
Input or feedback data setup time
Propagation delay
tPD
Delay from input to active output
I ±, F±
F±
50
40
45
ns
tCKO
Clock High to output valid access
Time
CLK +
F±
50
15
20
ns
tOE1
Product term enable to outputs off
I ±, F±
F±
50
40
45
ns
tOD1
Product term disable to outputs off
I ±, F±
F±
5
40
45
ns
tOD2
Pin 11 output disable High to outputs
off
OE –
F±
5
25
30
ns
tOE2
Pin 11 output enable to active output
OE +
F±
50
30
35
ns
tARD
Async reset delay
I ±, F±
F+
40
45
ns
tARR
Async reset recovery time
I ±, F±
CLK +
30
35
ns
tSPR
Sync preset recovery time
I ±, F±
CLK +
30
35
ns
tPPR
Power-up reset
VCC +
F+
35
40
ns
22
18
MHz
Frequency of operation
fMAX
Maximum frequency
I/(tIS + tCKO)
NOTES:
1. Refer also to AC Test Conditions. (Test Load Circuit)
1996 Oct 09
10
50
Philips Semiconductors
Product specification
3 volt zero standby power
universal PAL devices
P3C18V8Z40/P3C18V8ZIA
POWER-UP RESET
In order to facilitate state machine design and testing, a power-up
reset function has been incorporated in the P3C18V8Z. All internal
registers will reset to Active-Low (logical “0”) after a specified period
of time (tPPR). Therefore, any OMC that has been configured as a
registered output will always produce an Active-High on the
associated output pin because of the inverted output buffer. The
internal feedback (Q) of a registered OMC will also be set Low. The
programmed polarity of OMC will not affect the Active-High output
condition during a system power-up condition.
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
TIMING DIAGRAMS
INPUTS
I/O, REG.
FEEDBACK
VALID INPUT
tIS
VALID INPUT
tIH
tCKH
tCKL
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
CLK
tCKP
PIN 11 OE
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
tCKO
tOD2
tOE2
3–STATE
REGISTERED
OUTPUTS
ANY INPUT
PROGRAMMED FOR
DIRECTION CONTROL
tOD1
tPD
tOE1
3-STATE
COMBINATORIAL
OUTPUTS
Switching Waveforms
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
+3.3V
2.6V
VCC
0V
tPPR
F
(OUTPUTS)
I, B
(INPUTS)
VOH
1.5V
1.5V
VOL
tCKO
+3V
1.5V
1.5V
0V
tCKL
tIS
tIH
+3V
1.5V
CLK
1.5V
1.5V
0V
tIS
tCKH
tCKL
tCKP
NOTE:
Diagram presupposes that the outputs (F) are enabled. The reset occurs regardless of the output condition (enabled or disabled).
Power-Up Reset
1996 Oct 09
11
SP00356
Philips Semiconductors
Product specification
3 volt zero standby power
universal PAL devices
P3C18V8Z40/P3C18V8ZIA
TIMING DIAGRAMS (Continued)
tARW
ASYNCHRONOUS
RESET INPUT
tARD
REGISTERED
OUTPUT
tARR
CLOCK
Asynchronous Reset
tIS
tIH
tSPR
SYNCHRONOUS
PRESET INPUT
CLOCK
tCKO
REGISTERED
OUTPUT
Synchronous Preset
SP00021
1996 Oct 09
12
Philips Semiconductors
Product specification
3 volt zero standby power
universal PAL devices
P3C18V8Z40/P3C18V8ZIA
REGISTER PRELOAD FUNCTION
(DIAGNOSTIC MODE ONLY)
In order to facilitate the testing of state machine/controller designs, a
diagnostic mode register preload feature has been incorporated into
the P3C18V8Z series device. This feature enables the user to load
the registers with predetermined states while a super voltage is
applied to Pins 11 and 6 (I9/OE and I5). (See diagram for timing and
sequence.)
To read the data out, Pins 11 and 6 must be returned to normal TTL
levels. The outputs, F0 – 7, must be enabled in order to read data
out. The Q outputs of the registers will reflect data in as input via
F0 – 7 during preload. Subsequently, the register Q output via the
feedback path will reflect the data in as input via F0 – 7.
Refer to the voltage waveform for timing and voltage references.
tPL = 10µsec.
REGISTER PRELOAD (DIAGNOSTIC MODE)
12.0V
12.0V
I9/OE
(PIN 11)
5.0V
5.0V
tPL
tPL
tPL
tPL
tPL
tPL
OE(VOL)
12.0V
I5
(PIN 6)
5.0V
I0/CLK
I0/CLK
(PIN 1)
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
tOE
F0–7
I1–4, 6–8
1996 Oct 09
PRELOAD DATA IN
tCKL
tCKO
PRELOAD DATA OUT
13
tIS
DATA OUT
F0–7
tIH
I1–4, 6–8
SP00022
Philips Semiconductors
Product specification
3 volt zero standby power
universal PAL devices
P3C18V8Z40/P3C18V8ZIA
LOGIC PROGRAMMING
ERASURE CHARACTERISTICS
(For Quartz Window Packages Only)
The P3C18V8Z series is fully supported by industry standard
(JEDEC compatible) PLD CAD tools, including Philips
Semiconductors’ SNAP design software package. ABEL and
CUPL 90 design software packages also support the P3C18V8Z
architecture.
The erasure characteristics of the P3C18V8Z Series devices are
such that erasure begins to occur upon exposure to light with
wavelengths shorter than approximately 4000 Angstroms (Å). It
should be noted that sunlight and certain types of fluorescent
lighting could erase a typical P3C18V8Z in approximately three
years, while it would take approximately one week to cause erasure
when exposed to direct sunlight. If the P3C18V8Z is to be exposed
to these types of lighting conditions for extended periods of time,
opaque labels should be placed over the window to prevent
unintentional erasure.
All packages allow Boolean and state equation entry formats. SNAP,
ABEL and CUPL also accept, as input, schematic capture format.
P3C18V8Z logic designs can also be generated using the program
table entry format, which is detailed on the following pages. This
program table entry format is supported by SNAP only.
With Logic programming, the AND/OR/EX-OR gate input
connections necessary to implement the desired logic function are
coded directly from logic equations using the Program Table.
Similarly, various OMC configurations are implemented by
programming the Architecture Control bits AC1 and AC2. Note that
the configuration cell is automatically programmed based on the
OMC configuration.
The recommended erasure procedure for the P3C18V8Z is
exposure to shortwave ultraviolet light which has a wavelength of
2537 Angstroms (Å). The integrated dose (i.e., UV intensity ×
exposure time) for erasure should be a minimum of 15Wsec/cm2.
The erasure time with this dosage is approximately 30 to 35 minutes
using an ultraviolet lamp with a 12,000µW/cm2 power rating. The
device should be placed within one inch of the lamp tubes during
erasure. The maximum integrated dose a CMOS EPLD can be
exposed to without damage is 7258Wsec/cm2). Exposure of these
CMOS EPLDs to high intensity UV light for longer periods may
cause permanent damage.
In this table, the logic state of variables I, P and B associated with
each Sum Term S is assigned a symbol which results in the proper
fusing pattern of corresponding link pairs, defined as follows:
The maximum number of guaranteed erase/write cycles is 50. Data
retention exceeds 20 years.
OUTPUT POLARITY – (O, B)
S
S
O, B
O, B
X
X
ACTIVE LEVEL
CODE
ACTIVE LEVEL
CODE
INVERTING1
L
NON-INVERTING
H
SP00023
“AND” ARRAY – (I, B)
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
P
I, B
I, B
I, B
P
I, B
P
P
STATE
CODE
STATE
CODE
STATE
CODE
STATE
DON’T CARE
–
INACTIVE1
O
I, B
H
I, B
CODE
L
SP00024
NOTE:
1. A factory shipped unprogrammed device is configured such that all cells are in a conductive state.
ABEL is a trademark of Data I/O Corp.
CUPL is a trademark of Logical Devices, Inc.
1996 Oct 09
14
Philips Semiconductors
Product specification
3 volt zero standby power
universal PAL devices
P3C18V8Z40/P3C18V8ZIA
•
REV.
PROGRAM TABLE #
TOTAL NUMBER OF PARTS
CUSTOMER SYMBOLIZED PART #
PHILIPS DEVICE #
PURCHASE ORDER #
CUSTOMER NAME
CF(XXXX)
DATE
• • •
T
E
I
R
M
9 8 7 6 5 4 3 2 1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
SP
AR
11 9 8 7 6 5 4 3 2
PIN
CONFIGURATION CELL (CLK/OE CONTROL)
ARCH. CONTROL BITS
OUTPUT POLARITY
AND
OR (FIXED)
F (I)
F (B, O, D)
0 7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
D
A
A
A
A
A
A
A
A
D
A
A
A
A
A
A
A
A
D
A
A
A
A
A
A
A
A
D
A
A
A
A
A
A
A
A
D
A
A
A
A
A
A
A
A
D
A
A
A
A
A
A
A
A
D
A
A
A
A
A
A
A
A
D
A
A
A
A
A
A
A
A
1 19 18 17 16 15 14 13 12
19 18 17 16 15 14 13 12
VARIABLE
NAME
NOTES:
In the unprogrammed or virgin state:
All AND gate locations are pulled to a logic “0” (Low).
Output polarity is inverting.
Pins 1 and 11 are configured as inputs 0 and 9, respectively, via
the configuration cell. The clock and OE functions are disabled.
All output macro cells (OMC) are configured as combinatorial I/O,
with the outputs disabled via the direction control term.
PROGRAM TABLE
AND ARRAY
CONTROL
INACTIVE
O
I, F (I, B)
H
I, F (I, B)
L
**DON’T CARE –
OMC ARCH.
OUTPUT POLARITY
REGISTERED
(D-TYPE)
FIXED INPUT
D
FIXED OUTPUT
BIDIRECTIONAL I/O
O
B
I
NON-INVERTING
H
INVERTING
L
CONFIG. CELL*
PIN 1 = CLK; PIN 11 = OE L
PIN 1, PIN 11 = INPUT
H
OR ARRAY (FIXED)
DATA CANNOT BE ENTERED
INTO THE OR ARRAY FIELD
DUE TO THE FIXED NATURE
OF THE DEVICE ARCHITECTURE.
DIRECTION CONTROL D
ACTIVE OUTPUT
NOT USED
A
* THE CONFIGURATION CELL IS AUTOMATICALLY PROGRAMMED BASED ON THE OMC ARCHITECTURE.
** FOR SP, AR: “–” IS NOT ALLOWED.
1996 Oct 09
15
SP00029
Philips Semiconductors
Product specification
3 volt zero standby power
universal PAL devices
P3C18V8Z40/P3C18V8ZIA
SNAP RESOURCE SUMMARY DESIGNATIONS
I0/CLK
DINV8
I0
CONFIG.
CELL
NINV8
9
CKEV8
NOUTV8
I1
OMC
AND
CLK
9
PROGRAMMABLE AND ARRAY
36 ROWS X 72 COLUMNS
I2
I7
F7
NOUTV8
F6
OMC
9
NOUTV8
OMC
F1
9
NOUTV8
I8
OMC
F0
SP
AR
OE
CONFIG.
CELL
I9/OE
I9
1
FROM AND
ARRAY
TO ALL OMCs
DIRECTION CONTROL TERM
11
VCC
01
00
OE
MUX
XORREG
SP
AR
10
OR
FROM
AND
ARRAY
XORDIR
DFFV8
S
NOUTV8
F
D
X(n)
OUTPUT
POLARITY
CONTROL
Q
CLK
AC1n
XORINV
AC2n
F
MUX
00
10
11
01
FDMUX
NOTE:
Denotes a programmable cell location.
OE11V8
TO ALL OMCs
11
OE
SP00025
1996 Oct 09
16
Philips Semiconductors
Product specification
3 volt zero standby power
universal PAL devices
P3C18V8Z40/P3C18V8ZIA
DIP20: plastic dual in-line package; 20 leads (300 mil)
1996 Oct 09
17
SOT146-1
1996 Oct 09
853–0584B 06688
18
SEATING
PLANE
–T–
–D–
0.023 (0.58)
0.015 (0.38)
0.058 (1.47)
0.030 (0.76)
T
E D
0.010 (0.254)
0.975 (24.73)
0.940 (23.88)
0.100 (2.54) BSC
SEE NOTE 6
0.070 (1.78)
0.050 (1.27)
0.165 (4.19)
0.125 (3.18)
0.200 (5.08)
0.165 (4.19)
0.306 (7.77)
0.285 (7.24)
0.078 (1.98)
0.012 (0.30)
0.395 (10.03)
0.300 (7.62)
BSC
0.300 (7.62)
(NOTE 4)
3 volt zero standby power
universal PAL devices
0.015 (0.38)
0.010 (0.25)
0.035 (0.89)
0.020 (0.51)
0.175 (4.45)
0.145 (3.68)
0.320 (8.13)
0.290 (7.37)
(NOTE 4)
6. Denotes window location for EPROM products.
5. Pin numbers start with Pin #1 and continue
counterclockwise to Pin #20 when viewed
from the top.
2. Dimension and tolerancing per ANSI Y14. 5M-1982.
3. “T”, “D”, and “E” are reference datums on the body
and include allowance for glass overrun and meniscus
on the seal line, and lid to base mismatch.
4. These dimensions measured with the leads
constrained to be perpendicular to plane T.
NOTES:
1. Controlling dimension: Inches. Millimeters are
shown in parentheses.
0584B
PIN # 1
–E–
0.078 (1.98)
0.012 (0.30)
Philips Semiconductors
Product specification
P3C18V8Z40/P3C18V8ZIA
20-PIN (300 mils wide) CERAMIC DUAL IN-LINE (F) PACKAGE (WITH WINDOW (FA) PACKAGE)
Philips Semiconductors
Product specification
3 volt zero standby power
universal PAL devices
P3C18V8Z40/P3C18V8ZIA
PLCC20: plastic leaded chip carrier; 20 leads
1996 Oct 09
SOT380-1
19
Philips Semiconductors
Product specification
3 volt zero standby power
universal PAL devices
P3C18V8Z40/P3C18V8ZIA
SO20: plastic small outline package; 20 leads; body width 7.5 mm
1996 Oct 09
20
SOT163-1
Philips Semiconductors
Product specification
3 volt zero standby power
universal PAL devices
P3C18V8Z40/P3C18V8ZIA
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
1996 Oct 09
21
SOT339-1
Philips Semiconductors
Product specification
3 volt zero standby power
universal PAL devices
P3C18V8Z40/P3C18V8ZIA
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
1996 Oct 09
22
SOT360-1
Philips Semiconductors
Product specification
3 volt zero standby power
universal PAL devices
P3C18V8Z40/P3C18V8ZIA
NOTES
1996 Oct 09
23
Philips Semiconductors
Product specification
3 Volt zero standby power
universal PAL devices
P3C18V8Z40/P3C18V8ZIA
DEFINITIONS
Data Sheet Identification
Product Status
Definition
Objective Specification
Formative or in Design
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Preliminary Specification
Preproduction Product
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Product Specification
Full Production
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Philips Semiconductors and Philips Electronics North America Corporation
register eligible circuits under the Semiconductor Chip Protection Act.
Copyright Philips Electronics North America Corporation 1996
All rights reserved. Printed in U.S.A.