PI6C2308A 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 3.3V Zero-Delay Buffer Product Features Functional Description • 10 MHz to 140 MHz operating range • Zero input-output propagation delay, adjustable by capacitive load on FBK input • Multiple configurations, see Available PI6C2308A Configurations table • Input to output delay, less than 150ps • Multiple low skew outputs - Output-output skew less than 200ps - Device-device skew less than 500ps - Two banks of four outputs, Hi-Z by two select inputs • Low Jitter, less than 200ps • 3.3V operation • Available in industrial &commercial temperatures • Packages: - Space-saving 16-pin, 150-mil SOIC (W) - 16-pin TSSOP (L) Providing two banks of four outputs, the PI6C2308A is a 3.3V zerodelay buffer designed to distribute clock signals in applications including PC, workstation, datacom, telecom, and high-performance systems. Each bank of four outputs can be controlled by the select inputs as shown in the Select Input Decoding Table. The PI6C2308A provides 8 copies of a clock signal that has 150ps phase error compared to a reference clock. The skew between the output clock signals for PI6C2308A is less than 200ps. When there are no rising edges on the REF input, the PI6C2308A enters a power down state. In this mode, the PLL is off and all outputs are Hi-Z. This results in less than 12µA of current draw. The Select Input Decoding table shows additional examples when the PLL shuts down. The PI6C2308A configuration table shows all available devices. The base part, PI6C2308A-1, provides output clocks in sync with a reference clock. With faster rise and fall times, the PI6C2308A-1H is the high-drive version of the PI6C2308A-1. Depending on which output drives the feedback pin, PI6C2308A-2 provides 2X and 1X clock signals on each output bank. The PI6C2308A-3 allows the user to obtain 4X and 2X frequencies on the outputs. The PI6C2308A-4 provides 2X clock signals on all outputs. PI6C2308A (-1, -2, -3, -4) allows bank B to be Hi-Z when all output clocks are not required.The PI6C2308A-6 allows bank B to switch from Reference clock to half of the frequency of Reference clock using the control inputs S1 and S2 if Bank A is connected to feedback FBK. In addition, using the control inputs S1 and S2, the PI6C2308A-6 allows bank A to switch from Reference clock to 2X the frequency of Reference clock if Bank B is connected to feedback FBK. For testing purposes, the select inputs connect the input clock directly to outputs. Block Diagrams ÷2 REF PLL FBK CLKA1 MUX CLKA2 Extra Divider (-3, -4) S2 S1 CLKA3 Select Input Decoding CLKA4 ÷2 CLKB1 Extra Divider (-2,-3) CLKB2 CLKB3 PI6C2308A (-1, -1H, -2, -3, -4) REF PLL MUX Pin Configuration PI6C2308A (-1, -1H, -2, -3, -4, -6) CLKB4 FBK CLKA1 CLKA2 CLKA3 S2 S1 CLKA4 Select Input Decoding ÷2 MUX 1 16 FBK CLKA1 2 15 CLKA4 CLKA2 3 14 CLKA3 VDD 4 16-Pin 13 W, L GND 5 12 VDD GND CLKB1 6 11 CLKB4 7 10 CLKB3 8 9 CLKB2 CLKB1 PI6C2308A-6 REF S2 CLKB2 S1 CLKB3 CLKB4 1 PS8385C 08/03/00 PI6C2308A 3.3V Zero Delay Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Select Input Decoding for PI6C2308A (-1, -1H, -2, -3, -4) S2 S1 CLKA [1-4] CLKB [1-4] Output Source PLL Shutdown 0 0 Hi- Z Hi- Z PLL Y 0 1 Driven Hi- Z PLL N 1 0 Driven Driven Reference Y 1 1 Driven Driven PLL N Select Input Decoding for PI6C2308A-6 S2 S1 CLKA [1-4] CLKB [1-4] Output Source PLL Shutdown 0 0 Hi- Z Hi- Z PLL Y 0 1 Driven = Reference Driven = Reference/2 Reference Y 1 0 Driven = PLL Driven = PLL PLL N 1 1 Driven = PLL Driven = PLL/2 PLL N Available PI6C2308A Configurations De vice Fe e dback From Bank A Fre que ncy Bank B Fre que ncy PI6C2308A- 1 Bank A or Bank B Reference Reference PI6C2308A- 1H Bank A or Bank B Reference Reference PI6C2308A- 2 Bank A Reference Reference/2 PI6C2308A- 2 Bank B 2X Reference Reference PI6C2308A- 3 Bank A 2X Reference Reference PI6C2308A- 3 Bank B 4X Reference 2X Reference PI6C2308A- 4 Bank A or Bank B 2X Reference 2X Reference PI6C2308A- 6 Bank A Reference Reference or Reference/2 PI6C2308A- 6 Bank B Reference or 2X Reference Reference 2 PS8385C 08/03/00 PI6C2308A 3.3V Zero Delay Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Zero Delay and Skew Control REF. Input to CLKA/CLKB Delay vs. Difference in Loading between FBK pin and CLKA/CLKB pins 800 600 REF - Input to CLKA/CLKB Delay (ps) 400 200 0 -25 -20 -15 -10 0 -5 5 10 15 20 25 -200 -400 PI6C2308A-1H -600 -800 PI6C2308A-1,2,3,4,6 -900 -1000 Output Load Difference: FBK Load - CLKA/CLKB Load (pF) For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. If input-output delay adjustments are required, use the above graph to calculate loading differences between the feedback output and remaining outputs. To close the feedback loop of the PI6C2308A, the FBK pin can be driven from any of the 8 available output pins. The output driving the FBK pin will be driving a total load of 7pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust the input-output delay. This is shown in the graph above. Maximum Ratings Supply Voltage to Ground Potential ...................................................0.5V to +7.0V DC Input Voltage (Except REF) .................................................. 0.5V to VDD +0.5V DC Input Voltage REF ................................................................................ 0.5 to 7V Storage Temperature ........................................................................ 65ºC to +150ºC Maximum Soldering Temperature (10 seconds) ................................................ 260ºC Junction Temperature ....................................................................................... 150ºC Static Discharge Voltage (per MIL-STD-883, Method 3015) .................................................................. >2000V Operating Conditions (over the operating range, TA = 0ºC to +70°C, VCC = 3.3V ±0.3V) Parame te r VDD De s cription Supply Voltage M in. M ax. Units 3.0 3.6 V 0 70 ºC TA Operating Temperature (Ambient) Cl Load Capacitance 30 Cin Input Capacitance 7 3 pF PS8385C 08/03/00 PI6C2308A 3.3V Zero Delay Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Pin Description Pin Signal D e s cription 1 REF(1) Input reference frequency, 5VTolerant input, allows spread spectrum clock input 2 C LK A1(2) C lock output, Bank A 3 C LK A2(2) C lock output, Bank A 4 VDD 3.3V supply 5 GN D Ground 6 C LK B1(2) C lock output, Bank B 7 C LK B2(2) C lock output, Bank B 8 S2(3) Select input, bit 2 9 S1(3) Select input, bit 1 10 C LK B3(2) C lock output, Bank B 11 C LK B4(2) C lock output, Bank B 12 GN D Ground 13 VDD 3.3V, supply 14 C LK A3(2) C lock output, Bank A 15 C LK A4(2) C lock output, Bank A 16 FBK PLL feedback input Electrical Characteristics for Commercial Temperature Device Parame te r De s cription Te s t Conditions M in. M ax. VIL (4) Input LOW Voltage 0.8 VIH Input HIGH Voltage(4) 2.0 IIL Input LOW Current VIN = 0V 50.0 IIH Input HIGH Current VIN = VDD 200.0 VOL Output LOW Voltage(5) IOL = 8mA (1,2,3,4,6) IOL = 12mA (- 1H) 0.4 VOH (5) Output HIGH Voltage IOH = 8mA (1,2,3,4,6) IOH = 12mA (- 1H) 2.4 IDD (PD mode) Power Down Supply Current REF = 0 MHz 12.0 IDD Supply Current Unloaded outputs, 66.66 MHz, Select inputs at VDD or GND 39 IDD Supply Current Unloaded outputs, 100 MHz, Select inputs at VDD or GND 54 4 Units V µA V µA mA PS8385C 08/03/00 PI6C2308A 3.3V Zero Delay Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Switching Characteristics(5) for Commercial Temperature Device Parame te rs t1 t2 N ame Typ. Units 140 MHz 15pF to 30pF load 10 Duty = t2 ÷ t1 Measured at VDD/2 45 50 55 Duty C ycle(4) = t2 ÷ t1 (- 1H) Measured at 1.4V, FO UT ≤45 MHz 45 50 55 Measured at 1.4V 40 50 60 Rise Time(4) @30pF 2. 2 Time(4) @15pF 1. 5 Rise (1H) Fall Time(4) @30pF Rise 2. 2 1. 5 (1H) 1. 2 5 O utput to O utput Skew(4) same bank on (1,1H,2,3,4,6) O utput Bank A to O utput Bank B Skew(4) (1,1H,4) 200 All outputs equally loaded, VDD/2 200 O utput Bank A to O utput Bank B Skew(4) (2,3,6) 400 t6 Delay, REF Rising Edge to FBK Rising Edge(4) Measured at VDD/2 0 ± 15 0 t7 Device to Device Skew(4) Measured at VDD/2 on the FBK pins of devices 0 500 t8 O utput Slew Rate(4) Measured between 0.8V and 2.0V on - 1H device using Test C ircuit #2 1 200 Measured at 133 MHz, loaded outputs, 15pF load 10 0 C ycle to C ycle Jitter(4) (2,3,6) Measured at 66.67 MHz, loaded outputs, 30pF load 400 PLL Lock Time(4) Stable power supply, valid clocks presented on REF and FBK pins 1. 0 tJ ps V/ns Measured at 66.67 MHz, loaded outputs, 30pF load C ycle to C ycle Jitter(4) (1,1H,4) tLO CK % 1. 5 Measured between 0.8V and 2.0V Time(4) @15pF Fall Time(4) @30pF t5 M ax. C ycle(4) Fall Time(4) @30pF t4 M in. O utput Frequency Duty C ycle(4) = t2 ÷ t1 (- 1,- 2,- 3,- 4,- 6) t3 Te s t Conditions ps ms Notes: 1. Weak pull-down. 2. Weak pull-down on all outputs. 3. Weak pull-ups on these inputs. 4. REF and FBK inputs have a threshhold voltage of VDD/2. 5. For definition of t1-8, see Switching Waveforms on page 8. 5 PS8385C 08/03/00 PI6C2308A 3.3V Zero Delay Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Operating Conditions for Industrial Temperature Devices Parame te r VDD TA CL CIN D e s cription M in. M ax. Units Supply Voltage 3.0 3.6 V O perating Temperature (Ambient Temperature) 40 85 ºC Load Capacitance, below 100 MHz 30 Load Capacitance, from 100 MHz to 133 MHz 15 Input Capacitance 7 pF Electrical Characteristics for Industrial Temperature Devices Parame te r D e s cription Te s t Conditions M in. M ax. VIL Input LO W Voltage VIH Input HIGH Voltage IIL Input LO W Current VIN = 0V 50.0 IIH Input HIGH Current VIN = VDD 100.0 VOL O utput LO W Voltage(4) IOL = 8mA (1,2,3,4,6) IOL = 12mA (1H) VOH Voltage(4) IDD (PD mode) IDD O utput HIGH Power Down Supply Current Supply Current 0.8 2.0 IOH = 8mA (1,2,3,4,6) IOH = 12mA (1H) V µA 0.4 V 2.4 REF = 0 MHz 25.0 Unloaded outputs, 100 MHz, Select inputs at VDD or GND 45.0 µA 70.0 (1H) Unloaded outputs, 66 MHz, REF, except 1H 35.0 Unloaded outputs, 33 MHz, REF, except 1H 20.0 6 Units PS8385C mA 08/03/00 PI6C2308A 3.3V Zero Delay Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Switching Characteristics for Industrial Temperature Devices(5) Parame te r Name Te s t Conditions M in. Typ. 30pF load, All devices t1 O utput Frequency 20pF load, 1H device 100 10 140 15pF load, 1,2,3,4,6 devices Duty Cycle(4) = t2 ÷ t1 (1,2,3,4,6) t2 Duty Cycle(4) = t2 ÷ t1 (1H,) t3 Rise Time(4) (1,2,3,4,6) Rise Time(4) (1H) t4 Fall Time(4) (1,2,3,4) Fall Time(4) (1H) Measured at 1.4V, FOUT <66.66 MHz 30pF load Measured at 1.4V, FOUT <133 MHz 30pF load O utput Bank A to O utput Bank B Skew (1, 1H,4) 40.0 60.0 Measured at 1.4V, FOUT <45 MHz 30pF load 45.0 Measured at 1.4V, FOUT < 66.6 MHz 30pF load 45.0 Measured at 1.4V, FOUT <133 MHz 15pF load 40.0 60.0 Measured at 1.4V, FOUT <45 MHz 30pF load 45.0 55.0 50.0 Measured between 0.8V and 2.0V, 30pF load 55.0 Measured between 0.8V and 2.0V, 30pF load 2.50 Measured between 0.8V and 2.0V, 15pF load 1.50 Measured between 0.8V and 2.0V, 30pF load 1.25 400 Measured at VDD/2 t7 Device to Device Skew(4) Measured at VDD/2 MHz, on the FBK pins of devices t8 O utput Slew Rate(4) Measured between 0.8V & 2.0V on 1H,5 device using Test Circuit #2. 0 ±150 1 V/ns 200 Measured at 133 MHz, loaded outputs, 15pF Load 100 Cycle to Cycle Jitter(4), (2,3,6) Measured at 66.67 MHz, loaded outputs, 30pF load 400 PLL Lock Time(4) Stable power supply, valid clocks presented on REF and FBK pins 1.0 tJ ps 500 Measured at 66.67 MHz, loaded outputs, 30pF Load Cycle to Cycle Jitter(4), (1, 1H, 4) ns 200 All outputs equally loaded Delay, REF Rising Edge to FBK Rising Edge(4) % 1.50 Measured between 0.8V and 2.0V, 30pF load O utput Bank A to O utput Bank B Skew (2, 3,6) tLOCK 55.0 2.2 Measured between 0.8V and 2.0V, 15pF load t6 MHz 140 O utput to O utput Skew on same Bank (1,2,3,4,6)(4) t5 M ax. Units ps ms Notes: 1. Weak pull-down. 2. Weak pull-down on all outputs. 3. Weak pull-ups on these inputs. 4. REF and FBK inputs have a threshhold voltage of VDD/2. 5. For definition of t1-8, see Switching Waveforms on page 8. 7 PS8385C 08/03/00 PI6C2308A 3.3V Zero Delay Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Switching Waveforms Duty Cycle Timing t1 t2 1.4V 1.4V 1.4V All Outputs Rise/Fall Time 2.0V 0.8V OUTPUT 2.0V 0.8V t3 3.3V 0V t4 Output-Output Skew 1.4V OUTPUT 1.4V OUTPUT t5 Input-Output Propagation Delay VDD/2 INPUT VDD/2 FBK t6 Device-Device Skew FBK Device 1 VDD/2 VDD/2 FBK Device 2 t7 Test Circuit #1 0.1mF 0.1mF VDD OUTPUTS 0.1mF Test Circuit #2 CLK out 1k CLK out OUTPUTS CLOAD 0.1mF VDD GND W VDD GND GND W 1k VDD 10pF GND Test Circuit for t 8 ,Output slew rate on -1H device Test Circuit for all parameters except t 8 8 PS8385C 08/03/00 PI6C2308A 3.3V Zero Delay Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Package Diagrams 16-Pin SOIC (W) 16 .149 .157 3.78 3.99 .0099 .0196 0.25 x 45˚ 0.50 1 .0075 .0098 0-8˚ .386 .393 9.80 10.00 0.41 1.27 .053 .068 .0155 .0260 0.393 0.660 REF 1.35 1.75 .016 .050 .2284 .2440 5.80 6.20 SEATING PLANE .050 BSC 1.27 0.19 0.25 .0040 0.10 .0098 0.25 .013 .020 0.330 0.508 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS 16-Pin TSSOP (L) 16 .169 .177 4.3 4.5 1 .193 .201 4.9 5.1 .004 .008 .047 max. 1.20 0.45 .018 0.75 .030 SEATING PLANE .0256 BSC 0.65 .007 .012 .002 .006 0.09 0.20 .252 BSC 6.4 0.05 0.15 X.XX DENOTES CONTROLLING X.XX DIMENSIONS IN MILLIMETERS 0.19 0.30 Note: Controlling dimensions in millimeters. Ref: JEDEC MS - 012 AC 9 PS8385C 08/03/00 PI6C2308A 3.3V Zero Delay Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Ordering Information (Commercial Temperature Device) Orde ring Code Package Name Package Type W16 16- pin 150- mil SOIC Ope rating Range PI6C2308A- 1W PI6C2308A- 1HW PI6C2308A- 2W PI6C2308A- 3W PI6C2308A- 4W PI6C2308A- 6W Commercial PI6C2308A- 1L PI6C2308A- 1HL PI6C2308A- 2L PI6C2308A3L L16 16- pin TSSO P PI6C2308A4L PI6C2308A- 6L Ordering Information (Industria l Temperature Device) Orde ring Code Package Name Package Type W16 16- pin 150- mil SO IC Ope rating Range PI6C2308A- 1WI PI6C2308A- 1HWI PI6C2308A- 2WI PI6C2308A- 3WI PI6C2308A- 4WI PI6C2308A- 6WI Industrial PI6C2308A- 1LI PI6C2308A- 1HLI PI6C2308A- 2LI PI6C2308A- 3LI L16 16- pin TSSO P PI6C2308A- 4LI PI6C2308A- 6LII Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 10 PS8385C 08/03/00