ETC PI74ALVTC16652

PI74ALVTC16652
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2.5V 16-Bit Bus Transceiver and
Register with 3-State Outputs
Product Features
Product Description
• PI74ALVTC16652 is designed for low voltage operation,
VDD = 1.65V to 3.6V
• Supports Live Insertion
• 3.6V I/O Tolerant Inputs and Outputs
• Bus Hold
• High Drive, –32/64mA @ 3.3V
• Uses patented noise reduction circuitry
• Power-off high impedance inputs and outputs
• Industrial operation at –40°C to +85°C
• Packages available:
– 56-pin 240-mil wide plastic TSSOP (A56)
– 56-pin 173-mil wide plastic TVSOP (K56)
Pericom Semiconductor’s PI74ALVTC series of logic circuits are
produced using the Company’s advanced 0.35 micron CMOS
technology, achieving industry leading speed.
The PI74ALVTC16652 is a 16-bit bus transceiver and register designed
for low 1.65V to 3.6V Vcc operation. It consists of D-type flip-flops
and control circuitry arranged for multiplexed transmission of data
directly from the data bus or from the internal storage registers. The
device can be used as two 8-bit transceivers or one 16-bit transceiver.
Complementary Output Enable (OEAB and OEBA) inputs are
provided to control the transceiver functions. Select Control (SAB
and SBA) inputs are provided to select whether real-time or stored
data is transferred. A low input level selects real-time data, and a high
input level selects stored data. Circuitry used for Select Control
eliminates the typical decoding glitch that occurs in a multiplexer
during the transition between stored and real-time data.
Data on the A or B bus, or both, can be stored in the internal D flipflops by low-to-high transitions at the appropriate clock (CLKAB or
CLKBA) inputs regardless of the levels on the Select Control or
Output Enable inputs. When SAB and SBA are in the real-time
transfer mode, it also is possible to store data without using the
internal D-type flip-lops by simultaneously enabling OEAB and
OEBA. In this configuration, each output reinforces its input. Thus,
when all other data sources to the two sets of bus lines are in the highimpedance state, each set of bus lines remains at its last level
configuration.
To ensure the high-impedance state during power up or power down,
OEBA should be tied to Vcc through a pull-up resistor and OEAB
should be tied to GND through a pull-down resistor; the minimum
value of the resistor is determined by the current-sinking current
sourcing capability of the driver.
The family offers both I/O Tolerant, which allows it to operate in
mixed 1.65/3.6V systems, and “Bus Hold,” which retains the data
input’s last state preventing “floating” inputs and eliminating the
need for pullup/down resistors.
Logic Block Diagram
1OEBA 56
1OEAB
1CLKBA
1
55
1SBA 54
1CLKAB
2
1SAB
3
One of Eight Channels
1D
C1
1A1
5
52
1B1
1D
C1
TO SEVEN OTHER CHANNELS
2OEBA 29
2OEAB
2CLKBA
28
30
2SBA 31
2CLKAB 27
2SAB 26
One of Eight Channels
1D
C1
2A1
15
42
2B1
1D
C1
TO SEVEN OTHER CHANNELS
1
PS8597
01/22/02
PI74ALVTC16652
2.5V 16-Bit Bus Transceiver and
Register with 3-State Outputs
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Product Pin Description
Pin Name
D e s cription
O EAB
O utput Enable Inputs (Active HIGH)
O EBA
O utput Enable Inputs (Active LO W)
xCLK AB, xCLK BA
Clock Pulse Inputs
xSAB, xSBA
Select Control Inputs
xAx
Data Register A Inputs, Data Register B O utputs
xBx
Data Register B Inputs, Data Register A O utputs
GND
Ground
VCC
Power
Pin Configuration
1OEAB
1
56
1OEBA
1CLKAB
2
55
1CLKBA
1SAB
3
54
1SBA
GND
4
53
GND
1A1
5
52
1B1
1A2
6
51
1B2
VCC
7
50
VCC
1A3
8
49
1B3
1A4
9
48
1B4
1A5
10
47
1B5
GND
11
46
GND
1A6
12
45
1B6
1A7
13
1B7
1A8
14
56-Pin 44
A, K
43
2A1
15
42
2B1
2A2
16
41
2B2
2A3
17
40
2B3
GND
18
39
GND
2A4
19
38
2B4
2A5
20
37
2B5
1B8
2A6
21
36
2B6
VCC
22
35
VCC
2A7
23
34
2B7
2A8
24
33
2B8
GND
25
32
GND
2SAB
26
31
2SBA
2CLKAB
27
30
2CLKBA
2OEAB
28
29
2OEBA
2
PS8597
01/22/02
PI74ALVTC16652
2.5V 16-Bit Bus Transceiver and
Register with 3-State Outputs
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Truth Table(1)
Inputs
Data I/O*
Ope ration or Function
OEAB
OEBA
CLKAB
CLKBA
SAB
SB A
A1 - A8
B1 - B8
L
H
H or L
H or L
X
X
Input
Input
Isolation
L
H
↑
↑
X
X
Input
Input
Store A and B data
X
H
↑
H or L
X
X
Input
Unspecified* *
H
H
↑
↑
X* *
X
Input
Output
L
X
H or L
↑
X
X
Unspecified* *
Input
Hold A, store B
L
L
↑
↑
X
X* *
Output
Input
Store B in both registers
L
L
X
X
X
L
Output
Input
Real- time B data to A bus
L
L
X
H or L
X
H
Output
Input
Stored B data to A bus
H
H
X
X
L
X
Input
Output
Real- time A data to B bus
H
H
H or L
X
H
X
Input
Output
Stored A data to B bus
H
L
H or L
H or L
H
H
Output
Output
Stored A data to B bus and
stored B data to A bus
Store A, hold B
Store A in both registers
* The data output functions may be enabled or disabled by a varietyof level combinations at the OEAB or OEBA inputs. Data
input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
** Select control = L; clocks can occur simultaneously. Select control = H; to load both registers,
clocks must be staggered.
Note:
1. H = High Voltage Level, X = Don’t Care,
L = Low Voltage Level, ↑ = LOW-to-HIGH Transition
3
PS8597
01/22/02
PI74ALVTC16652
2.5V 16-Bit Bus Transceiver and
Register with 3-State Outputs
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REAL-TIME TRANSFER
BUS A to B
REAL-TIME TRANSFER
BUS B to A
BUS
BUS
BUS
BUS
A
B
A
B
OEAB OEBA
L
L
xCLKAB
X
xCLKBA
X
xSAB
X
xSBA
L
OEAB OEBA xCLKAB
H
H
X
xCLKBA
X
xSAB
L
TRANSFER STORED
DATA to A and/or B
STORAGE FROM
A,B, or A and B
BUS
BUS
BUS
BUS
A
B
A
B
OEAB OEBA xCLKAB
↑
X
H
L
X
X
↑
L
H
xCLKBA
X
↑
↑
xSBA
X
xSAB
X
X
X
OEAB OEBA xCLKAB
H
L
H or L
xSBA
X
X
X
xCLKBA
H or L
xSAB
H
xSBA
H
Note:
1. Cannot transfer data to A bus and B bus simultaneously.
4
PS8597
01/22/02
PI74ALVTC16652
2.5V 16-Bit Bus Transceiver and
Register with 3-State Outputs
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Supply Voltage Range, VDD ........................................................ –0.5V to 4.6V
Input Voltage Range, VI ................................................................ –0.5V to 4.6V
Output Voltage Range, VO (3-Stated) .............................. –0.5V to 4.6V
Output Voltage Range, VO(1) (Active) .................. –0.5V to VDD +0.5V
DC Input Diode Current (IIK) VI < 0V ........................................ –50mA
DC Output Diode Current (IOK)
VO < 0V ................................................................................... –50mA
VO > VDD .................................................................................................... ±50mA
DC Output Source/Sink Current (IOH/IOL) ......................... –64/128mA
DC VDD or GND Current per Supply Pin (ICC or GND) ............ ±100mA
Storage Temperature Range, Tstg .................................. –65°C to150°C
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Recommended Operating Conditions(2)
M in.
M ax.
Operating
1.65
3.6
Data Retention Only
1.2
3.6
2.0
VDD
Supply voltage
VIH
High- level input voltage
VDD = 2.7V to 3.6V
VIL
Low- level input voltage
VDD = 2.7V to 3.6V
VI
Input voltage
VO
Output voltage
Output current in IOH/IOL
∆t/∆v
TA
0.8
–0.3
3.6
Active State
0
VDD
Off State
0
3.6
VDD =
VDD =
VDD =
VDD =
3.0V to 3.6V
3.0V to 3.6V
2.3V to 2.7V
1.65V to 1.95V
Input transistion rise or fall rate(3)
Operating free- air temperature
Units
V
–32/64
±24
±18
±6
mA
0
10
ns/V
−40
85
C
Notes:
1. Absolute maximum of IO must be observed.
2. Unused control inputs must be held HIGH or LOW to prevent them from floating.
3 As measured between 0.8V and 2.0V, VDD = 3.0V.
5
PS8597
01/22/02
PI74ALVTC16652
2.5V 16-Bit Bus Transceiver and
Register with 3-State Outputs
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Electrical Characteristics over Recommended Operating Free-Air Temperature Range
(unless otherwise noted)
DC Characteristics (2.7V<VDD ≤ 3.6V)
Parame te r
VIK
VO H
Input Clamp Diode
HIGH Level O utput Voltage
Conditions
VD D
IIK = −18mA
3.0
2.7 - 3.6
VD D – 0.2
IO H = −12mA
2.7
2.2
IO H = −18mA
M ax.
3.0
2.2
2.0
IO L = 100µA
2.7 - 3.6
0.2
IO L = 12mA
2.7
0.4
IO L = 18mA
IO L = 24mA
0.45
3.0
0.5
IO L = 64mA
0.75
II
Input Leakage Current
VI = VD D , or GND
3.6
±5.0
IO Z
3- State O utput Leakage
VO = 3.6V
2.7
±10
IO F F
Power- O FF Leakage Current
VI or VO ≤ 3.6V
0
10
Bus Hold Current
A or B O utputs
VI = 0.8V
3.0
VI = 2.0V
VI = 0 to 3.6V
ID D
∆ID D
Q uiescent Supply Current
Increase in ID D per input
V
0.4
IO L = 32mA
IH O LD
Units
2.4
IO H = −32mA
LO W Level O utput Voltage
Typ.
–1.2
IO H = −100µA
IO H = −24mA
VO L
M in.
3.6
VI = VD D or GND
75
–75
µA
±500
50
VD D ≤ (VI,VO ) ≤ 3.6V
2.7 - 3.6
VIH = VD D –0.6V, O ther
inputs at VD D or GND
6
±50
400
PS8597
01/22/02
PI74ALVTC16652
2.5V 16-Bit Bus Transceiver and
Register with 3-State Outputs
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Electrical Characteristics over Recommended Operating Free-Air Temperature Range
(unless otherwise noted; continued from previous page)
DC Characteristics (2.3V ≤VDD ≤ 2.7V)
De s cription
VIK
Parame te rs
Input Clamp Diode
Conditions
IIK = –18mA
HIGH Level Output Voltage
2.3 - 2.7
IOH = –12mA
2.3
IOH = –18mA
IOL = 100µA
VOL
LOW Level Output Voltage
M in.
Typ.
2.3
IOH = –100µA
VOH
VDD
M ax.
–1.2
VDD– 0.2
1.8
1.7
2.3 - 2.7
0.2
IOL = 12mA
IOL = 18mA
0.5
2.3
0.55
II
Input Leakage Current
VI = VDD or GND
2.7
±5.0
IOZ
3- State Output Leakage
VO = 3.6V
2.3
±10
IOFF
Power- OFF Leakage Current
VI or VO ≤ 3.6V
0
10
Bus Hold Current
A or B Outputs
VI = 0.7V
IDD
∆ΙDD
Quiescent Supply Current
Increase in IDD per input
V
0.4
IOL = 24mA
IHOLD(1)
Units
2.5
VI = 1.7V
90
–90
VI = VDD or GND
40
VDD ≤ (VI,VO) ≤ 3.6V
±40
VIH = VDD –0.6V,
Inputs at VDD or Gnd
2.3 - 2.7
µA
µA
400
Note:
1. Not Guaranteed
7
PS8597
01/22/02
PI74ALVTC16652
2.5V 16-Bit Bus Transceiver and
Register with 3-State Outputs
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Electrical Characteristics over Recommended Operating Free-Air Temperature Range
(unless otherwise noted; continued from previous page)
DC Characteristics (1.65V ≤VDD ≤ 1.95V)
De s cription
Parame te rs
VIK
Input Clamp Diode
VOH
HIGH Level Output Voltage
VOL
LOW Level Output Voltage
Conditions
IIK = –18mA
VDD
M in.
Typ.
1.65
IOH = –100µA
1.65- 1.95
IOH = –6mA
M ax.
–1.2
VDD –0.2
V
1.4
IOL = 100µA
0.2
1.65
IOL = 6mA
0.3
II
Input Leakage Current
VI = VDD or GND
1.95
±5.0
IOZ
3- State Output Leakage
VO = 3.6V
1.65
±10
IOFF
Power- OFF Leakage Current
VI = VO ≤ 3.6V
0
10
Bus Hold Current
A or B Outputs
VI = 0.4
IHOLD(1)
IDD
∆ΙDD
Quiescent Supply Current
Increase in IDD per input
Units
1.65
VI = 1.3
VI = VDD or GND
50
µA
–50
20
VDD ≤ (VI,VO) ≤ 3.6V
VI = VDD –06V,
Other inputs at VDD or Gnd
1.65- 1.95
±20
400
Note:
1. Not Guaranteed
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PS8597
01/22/02
PI74ALVTC16652
2.5V 16-Bit Bus Transceiver and
Register with 3-State Outputs
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Timing Requirements (Over recommended operating free-air temperature range,
unless otherwise noted, see Figures 1 thru 4)
VCC = 1.8V ±0.15V
M in
M ax
fclock Clock Frequency
VCC = 2.5V ±0.2V
M in
150
tw Pulse duration, CLK high or low
M ax
VCC = 3.3V ±0.3V
M in
180
M ax
180
3.0
3.0
tsu Setup time,
A before CLKAB↑, or
B before CLKBA↑
2.5
2.0
1.6
th Hold time,
A after CLKAB↑, or
B after CLKBA↑
0.0
0.0
0.5
Units
MHz
ns
Switching Characteristics over recommended operating free-air temperature range
(unless otherwise noted, see Figures 1 thru 4)
Parame te rs
From
(Input)
To
(Output)
ten
tdis
M in.
M ax.
150
fmax
tpd
VCC = 1.8V ±0.15V
VCC = 2.5V ±0.2V
M in.
M ax.
180
VCC = 3.3V ±0.3V
M in.
M ax.
180
MHz
A or B
B or A
1.2
4.5
1.0
4.0
1.0
3.8
CLK AB
or
CLK BA
A or B
1.5
5.5
1.2
5.0
1.0
4.0
SAB or
SBA
B or A
1.4
5.0
1.1
4.5
1.0
4.0
O E or
OE
A or B
1.4
5.0
1.6
5.0
1.6
4.0
1.5
5.5
2.0
5.0
2.0
4.0
9
Units
ns
PS8597
01/22/02
PI74ALVTC16652
2.5V 16-Bit Bus Transceiver and
Register with 3-State Outputs
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Test Circuits and Switching Waveforms
Switch Position
Parameter Measurement Information (VDD = 1.65V - 3.6V)
3.3V/2.5V VDD
2 x VDD
R1
500Ω
From Output
Under Test
Open
RL
500Ω
50pF
CL
Te s t
S1
tPD
Open
tPLZ/tPZL
2 x VDD
tPHZ/tPZH
GND
GND
Pulse Width
(See Note A)
VDD
Low-High-Low
Pulse
VDD/2
0V
tW
1.8V VDD
VDD
2 x VDD
High-Low-High
Pulse
R1
1kΩ
From Output
Under Test
VDD/2
0V
Open
RL
1kΩ
30pF
CL
GND
Propagation Delay
(See Note A)
VDD
VDD/2
0V
Input
tPLH
Setup, Hold, and Release Timing
Data
Input
tSU
Timing
Input
tH
tPHL
VDD
VDD/2
VOL
Output
tPHL
VDD
VDD/2
0V
tPLH
VDD
VDD/2
0V
Opposite Phase
Input Transition
VDD
VDD/2
0V
Enable Disable Timing
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions
such that the output is LOW except when disabled by
the output control.
Waveform 2 is for an output with internal conditions
such that the output is HIGH except when disabled by
the output control.
C. All input pulses are supplied by generators having the
following characteristics: PRR ≤ 10 MHz, ZO = 50Ω,
tr ≤ 2ns, tf ≤ 2ns, measured from 10% to 90%, unless
otherwise specified.
D. The outputs are measured one at a time with one
transition per measurement.
VDD
Output
Control
(Active LOW)
VDD/2
0V
tPLZ
tPZL
VDD
Output
Waveform 1
S1 at 2xVDD
(see Note B)
Output
Waveform 2
S1 at GND
VDD
VDD/2
+0.15V
tPZH
-0.15V
VOH
VDD/2
0V
(see Note B)
10
VOL
tPHZ
PS8597
01/22/02
PI74ALVTC16652
2.5V 16-Bit Bus Transceiver and
Register with 3-State Outputs
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Packaging Mechanical: 56-pin TSSOP (A)
56
.236
.244
1
.547
.555
6.0
6.2
13.9
14.1
1.20
SEATING PLANE
.047
Max.
.004 0.09
.008 0.20
.0197
BSC
0.50
.007
.011
0.17
0.27
X.XX DENOTES DIMENSIONS
X.XX IN MILLIMETERS
0.45 .018
0.75 .030
.002
.006
0.05
0.15
.319 BSC
8.1
Packaging Mechanical: 56-pin TVSOP (K)
56
.169
.177
4.30
4.50
1
.441
.449
0.45 .018
0.75 .030
.031
.041
0.80
1.05
11.20
11.40
0.09
0.20
.0035
.008
.252
BSC
6.4
SEATING
PLANE
.016
BSC
0.40
X.XX
X.XX
.002
.006
0.05
0.15
.005
.009
0.13
0.23
.047
1.20
Max.
DENOTES DIMENSIONS
IN MILLIMETERS
Orde ring Information
Package - Pins
PI74ALVTC16652A
TSSOP - 56
PI74ALVTC16652K
TVSOP - 56
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
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