ETC PLUS20R8D/-7

Philips Semiconductors Programmable Logic Devices
Product specification
PAL devices
20L8, 20R8, 20R6, 20R4
PLUS20R8D/-7 SERIES
FEATURES
DESCRIPTION
• Ultra high-speed
The Philips Semiconductors PLUS20XX
family consists of ultra high-speed 7.5ns and
10ns versions of Series 24 PAL devices.
– tPD = 7.5ns and fMAX = 74MHz for the
PLUS20R8-7 Series
The PLUS20XX family is 100% functional
and pin-compatible with the 20L8, 20R8,
20R6, and 20R4 Series devices.
– tPD = 10ns and fMAX = 60 MHz for the
PLUS20R8D Series
• 100% functionally and pin-for-pin
The sum of products (AND-OR) architecture
is comprised of 64 AND gates and 8 fixed OR
gates. Multiple bidirectional pins provide
variable input/output pin ratios. Individual
3-State control of all outputs and registers
with feedback (R8, R6, R4) is also provided.
Proprietary designs can be protected by
programming the security fuse.
compatible with industry standard 24-pin
PAL ICs
• Power-up reset function to enhance state
machine design and testability
• Design support provided via SLICE and
other CAD tools for Series 24 PAL devices
• Field-programmable on industry standard
The PLUS20R8, R6, and R4 have D-type
flip-flops which are loaded on the
Low-to-High transition of the clock input.
programmers
• Security fuse
• Individual 3-State control of all outputs
In order to facilitate state machine design and
testing, a power-up reset function has been
incorporated into these devices to reset all
internal registers to active-Low after a
specific period of time.
The Philips Semiconductors State-of-the-Art
oxide isolation Bipolar fabrication process is
employed to achieve high-performance
operation.
The PLUS20XX family of devices are field
programmable, enabling the user to quickly
generate custom patterns using standard
programming equipment. See the
programmer chart for qualified programmers.
The SNAP software package from Philips
Semiconductors supports easy design entry
for the PLUS20XX series as well as other
PLD devices from Philips Semiconductors.
The PLUS20XX series are also supported by
other standard CAD tools for PAL-type
devices.
Order codes are listed in the Ordering
Information table.
DEDICATED
INPUTS
COMBINATORIAL
OUTPUTS
REGISTERED
OUTPUTS
PLUS20L8
14
8 (6 I/O)
0
PLUS20R8
12
0
8
PLUS20R6
12
2 I/O
6
PLUS20R4
12
4 I/O
4
DEVICE NUMBER
ORDERING INFORMATION
DESCRIPTION
ORDER CODE
DRAWING
NUMBER
24-Pin (300mils-wide) Plastic Dual-In-Line Package (DIP)
PLUS20R8DN
PLUS20R6DN
PLUS20R4DN
PLUS20L8DN
PLUS20R8–7N
PLUS20R6–7N
PLUS20R4–7N
PLUS20L8–7N
0410D
28-Pin (300mils-wide) Plastic Leaded Chip Carrier (PLCC)
PLUS20R8DA
PLUS20R6DA
PLUS20R4DA
PLUS20L8DA
PLUS20R8–7A
PLUS20R6–7A
PLUS20R4–7A
PLUS20L8–7A
0401F
PAL
is a registered trademark of Advanced Micro Devices, Inc.
September 10, 1993
52
853–1359 10778
Philips Semiconductors Programmable Logic Devices
Product specification
PAL devices
20L8, 20R8, 20R6, 20R4
PLUS20R8D/-7 SERIES
PIN CONFIGURATIONS
PLUS20L8
PLUS20R8
24
VCC
CLK
1
24
VCC
I1
2
23
I13
I0
2
23
I11
I2
3
22
O7
I1
3
DQ
Q
22
Q7
I3
4
21
B6
I2
4
DQ
Q
21
Q6
I4
5
20
B5
I3
5
DQ
Q
20
Q5
I5
6
19
B4
I4
6
DQ
Q
19
Q4
I6
7
18
B3
I5
7
DQ
Q
18
Q3
I7
8
17
B2
I6
8
DQ
Q
17
Q2
I8
9
16
B1
I7
9
DQ
Q
16
Q1
I9
10
15
B0
I8
10
DQ
Q
15
Q0
I10
11
14
I12
I9
11
14
I10
GND
12
13
I11
GND
12
13
OE
AND/OR ARRAY
1
AND/OR ARRAY
I0
PLUS20L8
PLUS20R8
I2
I1
I0 NC VCCI13 O7
I1
I0 CLK NC VCC I11 Q7
4
3
2
4
3
1
28 27 26
2
1
28 27 26
I3
5
I2
5
24 B5
I3
6
REG
REG
REG
25 Q6
6
O
I/O
I/O
25 B6
I4
I5
7
I/O
23 B4
I4
7
REG
23 Q4
I/O
22 NC
I/O
21 B3
I5
I7 10
I/O
20 B2
I8 11
O
19 B1
NC 8
I6
AND/OR
ARRAY
OUTPUTS
9
AND/OR
ARRAY
NC 8
24 Q5
22 NC
OUTPUTS
REG
21 Q3
I6 10
REG
20 Q2
I7 11
REG
19 Q1
9
12 13 14 15 16 17 18
12 13 14 15 16 17 18
I9 I10 GND NC I11 I12 O0
I8
I9 GND NC OE I10 Q0
SYMBOL
I
O
Q
B
CLK
OE
DESCRIPTION
Dedicated Input
Dedicated combinatorial Output
Registered output
Bidirectional (input/output)
Clock input
Output Enable
SYMBOL
I
O
Q
B
CLK
OE
DESCRIPTION
Dedicated Input
Dedicated combinatorial Output
Registered output
Bidirectional (input/output)
Clock input
Output Enable
VCC
GND
NC
Supply Voltage
Ground
No Connection
VCC
GND
NC
Supply Voltage
Ground
No Connection
September 10, 1993
53
Philips Semiconductors Programmable Logic Devices
Product specification
PAL devices
20L8, 20R8, 20R6, 20R4
PLUS20R8D/-7 SERIES
PIN CONFIGURATIONS
PLUS20R6
PLUS20R4
CLK
1
24
VCC
I0
2
23
I1
3
I2
4
I3
5
I4
6
I5
7
I6
24
VCC
I11
I0
2
23
I11
22
B7
I1
3
22
B7
DQ
Q
21
Q6
I2
4
21
B6
DQ
Q
20
Q5
I3
5
DQ
Q
20
Q5
DQ
Q
19
Q4
I4
6
DQ
Q
19
Q4
DQ
Q
18
Q3
I5
7
DQ
Q
18
Q3
8
DQ
Q
17
Q2
I6
8
DQ
Q
17
Q2
I7
9
DQ
Q
16
Q1
I7
9
16
B1
I8
10
15
B0
I8
10
15
B0
I9
11
14
I10
I9
11
14
I10
GND
12
13
OE
GND
12
13
OE
AND/OR ARRAY
1
AND/OR ARRAY
CLK
PLUS20R6
PLUS20R4
I1
I0 CLK NC VCC I11 B7
I1
I0 CLK NC VCC I11 B7
4
3
4
3
2
1
28 27 26
2
1
28 27 26
I2
5
I2
5
24 Q5
I3
6
I/O
I/O
REG
25 B6
6
I/O
REG
REG
25 Q6
I3
I4
7
REG
23 Q4
I4
7
REG
23 Q4
AND/OR
ARRAY
NC 8
I5
22 NC
OUTPUTS
9
I6 10
I7 11
REG
21 Q3
I5
REG
REG
I/O
20 Q2
I6 10
19 Q1
I7 11
22 NC
OUTPUTS
9
12 13 14 15 16 17 18
I8
AND/OR
ARRAY
NC 8
24 Q5
REG
REG
I/O
21 Q3
20 Q2
19 B1
12 13 14 15 16 17 18
I9 GND NC OE I10 B0
I8
I9 GND NC OE I10 B7
SYMBOL
I
O
Q
B
CLK
OE
DESCRIPTION
Dedicated Input
Dedicated combinatorial Output
Registered output
Bidirectional (input/output)
Clock input
Output Enable
SYMBOL
I
O
Q
B
CLK
OE
DESCRIPTION
Dedicated Input
Dedicated combinatorial Output
Registered output
Bidirectional (input/output)
Clock input
Output Enable
VCC
GND
NC
Supply Voltage
Ground
No Connection
VCC
GND
NC
Supply Voltage
Ground
No Connection
September 10, 1993
54
Philips Semiconductors Programmable Logic Devices
Product specification
PAL devices
20L8, 20R8, 20R6, 20R4
PLUS20R8D/-7 SERIES
LOGIC DIAGRAM
I0
1
I1
2
PLUS20L8
0
3
4
7
8
11 12
15 16
19 20
23 24
27 28
31 32
35 36
39
23
I13
22
O7
21
B6
20
B5
19
B4
18
B3
17
B2
16
B1
15
O0
8
15
I2
3
16
23
I3
4
24
31
I4
5
PRODUCT TERMS (0–63)
32
39
I5
6
40
47
I6
7
48
55
I7
8
56
63
I8
9
64
71
I9
10
14
I12
I10
11
13
I11
0
3
4
7
8
11 12
15 16
19 20
23 24
27 28
INPUTS (0–39)
NOTES:
1. All unprogrammed or virgin “AND” gate locations are pulled to logic “0”.
2.
Programmable connections.
September 10, 1993
55
31 32
35 36
39
Philips Semiconductors Programmable Logic Devices
Product specification
PAL devices
20L8, 20R8, 20R6, 20R4
PLUS20R8D/-7 SERIES
LOGIC DIAGRAM
CLK
1
I0
2
PLUS20R8
0
3
4
7
8
11 12
15 16
19 20
23 24
27 28
31 32
35 36
39
23
I11
22
Q7
21
Q6
20
Q5
19
Q4
18
Q3
17
Q2
16
Q1
15
Q0
14
I10
13
OE
8
D
I1
Q
Q
15
3
16
D
Q
23
I2
Q
4
24
D
Q
31
I3
Q
5
PRODUCT TERMS (0–63)
32
D
Q
39
I4
Q
6
40
D
Q
47
I5
Q
7
48
D
Q
55
I6
Q
8
56
D
I7
Q
Q
63
9
64
D
Q
71
I8
10
I9
11
0
3
4
7
8
11 12
15 16
19 20
23 24
27 28
INPUTS (0–39)
NOTES:
1. All unprogrammed or virgin “AND” gate locations are pulled to logic “0”.
2.
Programmable connections.
September 10, 1993
Q
56
31 32
35 36
39
Philips Semiconductors Programmable Logic Devices
Product specification
PAL devices
20L8, 20R8, 20R6, 20R4
PLUS20R8D/-7 SERIES
LOGIC DIAGRAM
CLK
1
I0
2
PLUS20R6
0
3
4
7
8
11 12
15 16
19 20
23 24
27 28
31 32
35 36
39
23
I11
22
B7
21
Q6
20
Q5
19
Q4
18
Q3
17
Q2
16
Q1
15
B0
14
I10
13
OE
8
15
I1
3
16
D
Q
23
I2
Q
4
24
D
Q
31
I3
Q
5
PRODUCT TERMS (0–63)
32
D
Q
39
I4
Q
6
40
D
Q
47
I5
Q
7
48
D
Q
55
I6
Q
8
56
D
I7
Q
Q
63
9
64
71
I8
10
I9
11
0
3
4
7
8
11 12
15 16
19 20
23 24
27 28
INPUTS (0–39)
NOTES:
1. All unprogrammed or virgin “AND” gate locations are pulled to logic “0”.
2.
Programmable connections.
September 10, 1993
57
31 32
35 36
39
Philips Semiconductors Programmable Logic Devices
Product specification
PAL devices
20L8, 20R8, 20R6, 20R4
PLUS20R8D/-7 SERIES
LOGIC DIAGRAM
CLK
1
I0
2
PLUS20R4
0
3
4
7
8
11 12
15 16
19 20
23 24
27 28
31 32
35 36
39
23
I11
22
B7
21
B6
20
Q5
19
Q4
18
Q3
17
Q2
16
B1
15
B0
14
I10
13
OE
8
15
I1
3
16
23
I2
4
24
D
Q
31
I3
Q
5
PRODUCT TERMS (0–63)
32
D
Q
39
I4
Q
6
40
D
Q
47
I5
Q
7
48
D
Q
55
I6
Q
8
56
63
I7
9
64
71
I8
10
I9
11
0
3
4
7
8
11 12
15 16
19 20
23 24
27 28
INPUTS (0–39)
NOTES:
1. All unprogrammed or virgin “AND” gate locations are pulled to logic “0”.
2.
Programmable connections.
September 10, 1993
58
31 32
35 36
39
Philips Semiconductors Programmable Logic Devices
Product specification
PAL devices
20L8, 20R8, 20R6, 20R4
PLUS20R8D/-7 SERIES
FUNCTIONAL DESCRIPTIONS
Programmable Bidirectional Pins
The PLUS20XX series utilizes the familiar
sum-of-products implementation consisting of
a programmable AND array and a fixed OR
array. These devices are capable of replacing
an equivalent of four or more SSI/MSI
integrated circuits to reduce package count
and board area occupancy, consequently
improving reliability and design cycle over
Standard Cell or gate array options. By
programming the security fuse, proprietary
designs can be protected from duplication.
The PLUS20XX products feature variable
Input/Output ratios. In addition to 12
dedicated inputs, each combinatorial output
pin of the registered devices can be
individually programmed as an input or
output. The PLUS20L8 provides 14 dedicated
inputs and 6 Bidirectional I/O lines that can
be individually configured as inputs or
outputs.
The PLUS20XX series consists of four
PAL-type devices. Depending on the
particular device type, there are a variable
number of combinatorial and registered
outputs available to the designer. The
PLUS20L8 is a combinatorial part with 8 user
configurable outputs (6 bidirectional), while
the other three devices, PLUS20R8,
PLUS20R6, PLUS20R4, have respectively 8,
6, and 4 output registers.
3-State Outputs
The PLUS20XX series devices also feature
3-State output buffers on each output pin
which can be programmed for individual
control of all outputs. The registered outputs
(Qn) are controlled by an external input
(/OE), and the combinatorial outputs (On, Bn)
use a product term to control the enable
function.
Output Registers
The PLUS20R8 has 8 output registers, the
20R6 has 6, and the 20R4 has 4. Each
output register is a D-type flip-flop which is
loaded on the Low-to-High transition of the
clock input. These output registers are
capable of feeding the outputs of the
registers back into the array to facilitate
design of synchronous state machines.
series are supported by SLICE, the
PC-based software development tool from
Philips Semiconductors. The PLUS20XX
family of devices are also supported by
standard CAD tools for PAL devices,
including ABEL and CUPL.
SLICE is available free of charge to qualified
users.
Logic Programming
The PLUS20XX series is fully supported by
industry standard (JEDEC compatible) PLD
CAD tools, including Philips Semiconductors
SNAP design software package. ABEL
CUPL and PALASM 90 design software
packages also support the PLUS20XX
architecture.
Power-up Reset
All packages allow Boolean and state
equation entry formats. SNAP, ABEL and
CUPL also accept, as input, schematic
capture format.
By resetting all flip-flops to a logic Low, as the
power is turned on, the PLUS20R8, R6, R4
enhance state machine design and
initialization capability.
PROGRAMMING/SOFTWARE
SUPPORT
Software Support
Like other Programmable Logic Devices from
Philips Semiconductors, the PLUS20XX
Refer to Section 9 (Development Software)
and Section 10 (Third-Party Programmer/
Software Support) of the PLD data handbook
for additional information.
AND ARRAY – (I, B)
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
P, D
STATE
INACTIVE1, 2
I, B
P, D
I, B
P, D
P, D
CODE
STATE
CODE
STATE
CODE
STATE
CODE
O
I, B
H
I, B
L
DON’T CARE
–
VIRGIN STATE
A factory shipped virgin device contains all
fusible links intact, such that:
1. All outputs are at “H” polarity.
2. All Pn terms are disabled.
3. All Pn terms are active on all outputs.
ABEL is a trademark of Data I/O Corp.
CUPL is a trademark of Logical Devices, Inc.
PALASM is a registered trademark of AMD Corp.
September 10, 1993
I, B
I, B
59
Philips Semiconductors Programmable Logic Devices
Product specification
PAL devices
20L8, 20R8, 20R6, 20R4
PLUS20R8D/-7 SERIES
ABSOLUTE MAXIMUM RATINGS1
THERMAL RATINGS
TEMPERATURE
RATINGS
SYMBOL
PARAMETER
MIN
MAX
UNIT
Maximum junction
150°C
VCC
Supply voltage
–0.5
+7
VDC
Maximum ambient
75°C
VIN
Input voltage
–1.2
+8.0
VDC
75°C
VOUT
Output voltage
–0.5
VCC + 0.5V
VDC
Allowable thermal
rise ambient to
junction
IIN
Input currents
–30
+30
mA
IOUT
Output currents
+100
mA
Tstg
Storage temperature range
+150
°C
–65
NOTE:
1. Stresses above those listed may cause malfunction or permanent damage to the device.
This is a stress rating only. Functional operation at these or any other condition above
those indicated in the operational and programming specification of the device is not
implied.
OPERATING RANGES
RATINGS
SYMBOL
PARAMETER
VCC
Supply voltage
Tamb
Operating free-air temperature
September 10, 1993
MIN
MAX
UNIT
+4.75
+5.25
VDC
0
+75
°C
60
Philips Semiconductors Programmable Logic Devices
Product specification
PAL devices
20L8, 20R8, 20R6, 20R4
PLUS20R8D/-7 SERIES
DC ELECTRICAL CHARACTERISTICS
0°C ≤ Tamb ≤ +75°C, 4.75 ≤ VCC ≤ 5.25V
LIMITS
SYMBOL
Input
PARAMETER
TEST CONDITIONS
MIN
TYP1
MAX
UNIT
0.8
V
voltage2
VIL
Low
VCC = MIN
VIH
High
VCC = MAX
VIC
Clamp
2.0
VCC = MIN, IIN = –18mA
V
–0.8
–1.5
V
0.5
V
Output voltage
VCC = MIN, VIN = VIH or VIL
VOL
Low
IOL = 24mA
VOH
High
IOH = –3.2mA
2.4
V
Input current
VCC = MAX
IIL
Low3
VIN = 0.40V
–250
µA
IIH
High3
VIN = 2.7V
25
µA
II
Maximum input current
VIN = VCC = VCCMAX
100
µA
Output current
VCC = MAX
IOZH
Output leakage
VOUT = 2.7V
100
µA
IOZL
Output leakage
VOUT = 0.4V
–100
µA
–90
mA
210
mA
4, 5
IOS
Short circuit
ICC
VCC supply current
VOUT = 0V
VCC = MAX
–30
150
Capacitance6
CIN
CB
Input
I/O (B)
VCC = 5V
VOUT = 2.0V
8
pF
VOUT = 2V, f = 1MHz
8
pF
NOTES:
1. All typical values are at VCC = 5V, Tamb = +25°C.
2. All voltage values are with respect to network ground terminal.
3. Leakage current for bidirectional pins is the worst case of IIL and IOZL or IIH and IOZH.
4. Test one at a time.
5. Duration of short circuit should not exceed 1 second.
6. These parameters are not 100% tested but periodically sampled.
September 10, 1993
61
Philips Semiconductors Programmable Logic Devices
Product specification
PAL devices
20L8, 20R8, 20R6, 20R4
PLUS20R8D/-7 SERIES
AC ELECTRICAL CHARACTERISTICS
R1 = 200Ω, R2 = 390Ω, 0°C ≤ Tamb ≤ +75°C, 4.75 ≤ VCC ≤ 5.25V
LIMITS
SYMBOL
PARAMETER
FROM
TO
–7
MIN1
TYP
D
MAX
MIN1
UNIT
MAX
Pulse Width
tCKH
Clock High
CK+
CK–
5
7
ns
tCKL
Clock Low
CK–
CK+
5
7
ns
tCKP
Period
CK+
CK+
10
14
ns
Setup & Hold time
tIS
Input
Input or
feedback
CK+
7
9
ns
tIH
Input
CK+
Input or
feedback
0
0
ns
3
Propagation delay
tCKO
Clock
CK±
Q±
tCKF
Clock3
CK±
Q
tPD
Output (20L8, R6, R4)2
I, B
Output
3
7.5
tOE1
Output
enable4
OE
Output enable
3
Output
enable4,5
I
Output enable
Output
disable4
OE
tOD2
Output
disable4,5
tSKW
Output
tPPR
Power-Up Reset
tOE2
tOD1
6.5
3
7.5
ns
6.5
ns
3
10
ns
8
3
10
ns
3
10
3
10
ns
Output disable
3
8
3
10
ns
I
Output disable
3
10
3
10
ns
Q
Q
1
1
ns
VCC+
Q+
10
10
ns
3
Frequency (20R8, R6, R4)
fMAX
No feedback 1/ (tCKL + tCKH)6
100
71.4
MHz
Internal feedback 1/ (tIS + tCKF)6
90
64.5
MHz
External feedback 1/ (tIS + tCKO)6
74
60.6
MHz
* For definitions of the terms, please refer to the Timing/Frequency Definitions tables.
NOTES:
1. CL = 0pF while measuring minimum output delays.
2. tPD test conditions: CL = 50pF (with jig and scope capacitance), VIH = 3V, VIL = 0V, VOH = VOL = 1.5V.
3. tCKF was calculated from measured Internal fMAX.
4. For 3-State output; output enable times are tested with CL = 50pF to the 1.5V level, and S1 is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output
voltage of VT = (VOH – 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed.
5. Same function as tOE1 and tOD1, with the difference of using product term control.
6. Not 100% tested, but calculated at initial characterization and at any time a modification in design takes place which may affect the
frequency.
September 10, 1993
62
Philips Semiconductors Programmable Logic Devices
Product specification
PAL devices
20L8, 20R8, 20R6, 20R4
PLUS20R8D/-7 SERIES
OUTPUT REGISTER PRELOAD
The output registers can be preloaded to any desired state during device testing. This permits any state to be tested without having to step
through the entire state-machine sequence. Each register is preloaded individually by following the steps given below.
Step 1.
Step 2.
Step 3.
Step 4.
With VCC at 5V and Pin 1 at VIL, raise Pin 13 to VIHH.
Apply either VIL or VIH to the output corresponding to the register to be preloaded.
Pulse Pin 1, clocking in preload data.
Remove output voltage, then lower Pin 13 to VIL. Preload can be verified by observing the voltage level at the output pin.
VIHH
PIN 13 OE
tsu
td
VIL
td
tw
ÉÉ
ÉÉ
ÇÇ
ÉÉ
ÇÇ
ÉÉ
ÇÇ
ÇÇ
PIN 1 CLOCK
VIH
VIL
td
VOH
VIH
REGISTERED I/O
INPUT
VIL
NOTE:
td = tsu = tw = 100ns to 1000ns.
VIHH = 10.25V to 10.75V.
Pin and number reference for DIP package
TEST LOAD CIRCUIT
VCC
C1
+5V
S1
C2
R1
B0/O0
I0
Bn/On
DUT
R2
Q0
INPUTS
Qn
In
CLK
OE
GND
NOTE:
C1 and C2 are to bypass VCC to GND.
September 10, 1993
63
CL
OUTPUT
VOL
Philips Semiconductors Programmable Logic Devices
Product specification
PAL devices
20L8, 20R8, 20R6, 20R4
PLUS20R8D/-7 SERIES
OUTPUT REGISTER SKEW
3V
CLK
0V
3V
Qn
(REGISTERED OUTPUT)
1.5V
0V
tSKW
3V
Qn + 1
(REGISTERED OUTPUT)
1.5V
0V
CLOCK TO FEEDBACK PATH
CLK
tIS
D
Q
tCKF
September 10, 1993
64
Philips Semiconductors Programmable Logic Devices
Product specification
PAL devices
20L8, 20R8, 20R6, 20R4
PLUS20R8D/-7 SERIES
TIMING DIAGRAMS1, 2
TIMING DEFINITIONS
SYMBOL
PARAMETER
+3V
I, B
(INPUTS)
1.5V
tCKH
Width of input clock pulse.
tCKL
Interval between clock pulses.
+3V
tCKP
Clock period.
0V
tIS
Required delay between
beginning of valid input and
positive transition of clock.
tIH
Required delay between
positive transition of clock and
end of valid input data.
tCKF
Delay between positive
transition of clock and when
internal Q output of flip-flop
becomes valid.
tCKO
Delay between positive
transition of clock and when
outputs become valid (with
OE Low).
tOE1
Delay between beginning of
Output Enable Low and when
outputs become valid.
tOD1
Delay between beginning of
Output Enable High and when
outputs are in the Off-State.
tOE2
Delay between predefined
Output Enable High, and
when combinational outputs
become valid.
tOD2
Delay between predefined
Output Enable Low and when
combinational outputs are in
the Off-State.
tPPR
Delay between VCC (after
power-on) and when flip-flop
outputs become preset at “1”
(internal Q outputs at “0”).
tPD
Propagation delay between
combinational inputs and
outputs.
1.5V
0V
tIH
tIS
ÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇ
1.5V
CLK
tIS
1.5V
tCKH
Q
(REGISTERED OUTPUTS)
tCKL
tCKP
VOH
VT
1.5V
VOL
tOD1
tCKO
OE
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
1.5V
+3V
1.5V
1.5V
0V
tOE1
Flip-Flop Outputs
I, B
(INPUTS)
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
1.5V
+3V
0V
tPD
O, B
(COMBINATORIAL
OUTPUTS)
VOH
1.5V
VT
VOL
tOE2
tOD2
+3V
I, B
(OUTPUT
ENABLE)
+1.5V
+1.5V
0V
Gate Outputs
VCC
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
4.5V
VCC
0V
tPPR
Q
(REGISTERED
OUTPUTS)
VOH
1.5V
1.5V
VOL
tCKO
+3V
I, B
(INPUTS)
1.5V
1.5V
0V
tIH
tIS
+3V
1.5V
CLK
1.5V
1.5V
0V
tIS
tCKH
tCKL
tIS+tCKF
Power-Up Reset
NOTES:
1. Input pulse amplitude is 0V to 3V.
2. Input rise and fall times are 2.5ns.
September 10, 1993
65
FREQUENCY DEFINITIONS
fMAX
No feedback: Determined by
the minimum clock period,
1/(tCKL + tCKH).
Internal feedback:
Determined by the internal
delay from flip-flop outputs
through the internal feedback
and array to the flip-flop
inputs, 1/(tIS + tCKF).
External feedback:
Determined by clock-to-output
delay and input setup time,
1/(tIS + tCKO).
Philips Semiconductors Programmable Logic Devices
Product specification
PAL devices
20L8, 20R8, 20R6, 20R4
PLUS20R8D/-7 SERIES
SNAP RESOURCE SUMMARY DESIGNATIONS
I0 – I13
14
DINPAL7
NINPAL7
PROGRAMMABLE AND ARRAY
AND
1
1
8
DINPAL7
8
NINPAL7
OR
OR
NOUTPAL7
NOUTPAL7
B1 – B6
O0, O7
PLUS20L8
CLK
I0 – I11
OE
12
CKPAL7
NOEPAL7
DINPAL7
NINPAL7
PROGRAMMABLE AND ARRAY
AND
NINPAL7
8
DINPAL7
8
OR
D
Q
OR
DFFPAL7
D
Q
Q
Q
NOUTPAL7
NOUTPAL7
Q7
Q0
PLUS20R8
September 10, 1993
DFFPAL7
66
Philips Semiconductors Programmable Logic Devices
Product specification
PAL devices
20L8, 20R8, 20R6, 20R4
PLUS20R8D/-7 SERIES
SNAP RESOURCE SUMMARY DESIGNATIONS (Continued)
I0 – I11
CLK
OE
CKPAL7
NOEPAL7
12
DINPAL7
NINPAL7
PROGRAMMABLE AND ARRAY
AND
NINPAL7
8
1
8
DINPAL7
OR
OR
DFFPAL7
D
Q
Q
NOUTPAL7
NOUTPAL7
Q1 – Q6
B0, B7
PLUS20R6
I0 – I11
CLK
OE
CKPAL7
NOEPAL7
12
DINPAL7
NINPAL7
PROGRAMMABLE AND ARRAY
AND
NINPAL7
8
1
8
DINPAL7
OR
OR
DFFPAL7
D
Q
NOUTPAL7
NOUTPAL7
Q2 – Q5
B0, B1, B6, B7
PLUS20R4
September 10, 1993
Q
67