ETC PM7322?

PM7322 RCMP-800
STANDARD PRODUCT
20
02
10
:21
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
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RCMP-800
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PM7322
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ATM LAYER
ROUTING CONTROL, MONITORING AND
POLICING 800 Mbps
Issue 6: August 1997
______________________________________________________________________________________________
PMC-Sierra, Inc.
105-8555 Baxter Place, Burnaby, BC Canada V5A 4V7 604 415-6000
PM7322 RCMP-800
STANDARD PRODUCT
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20
02
10
:21
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
______________________________________________________________________________________________
PMC-Sierra, Inc.
105-8555 Baxter Place, Burnaby, BC Canada V5A 4V7 604 415-6000
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
CONTENTS
10
FEATURES......................................................................................................................................................1
20
02
POLICING .....................................................................................................................................................2
CELL COUNTING..........................................................................................................................................2
OAM HANDLING AND PERFORMANCE MONITORING ..................................................................................2
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APPLICATIONS...............................................................................................................................................4
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REFERENCES ................................................................................................................................................4
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APPLICATION EXAMPLES.............................................................................................................................5
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BLOCK DIAGRAM...........................................................................................................................................8
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DESCRIPTION ................................................................................................................................................9
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PIN DIAGRAM ...............................................................................................................................................11
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PIN DESCRIPTION (TOTAL 240) .................................................................................................................12
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OUTPUT CELL INTERFACE SIGNALS (24) .................................................................................................12
INPUT CELL INTERFACE SIGNALS (30) .....................................................................................................15
SYNCHRONOUS SRAM INTERFACE SIGNALS (70) ...................................................................................19
MICROPROCESSOR INTERFACE SIGNALS (30).........................................................................................22
MISC. INTERFACE SIGNALS (66) ...............................................................................................................25
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FUNCTIONAL DESCRIPTION ......................................................................................................................30
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INPUT BUFFERING .....................................................................................................................................30
VC IDENTIFICATION...................................................................................................................................31
CELL PROCESSING ...................................................................................................................................39
MULTICASTING ..........................................................................................................................................58
OUTPUT BUFFERING .................................................................................................................................59
CONGESTION CONTROL ...........................................................................................................................59
JTAG TEST ACCESS PORT INTERFACE....................................................................................................59
MICROPROCESSOR INTERFACE ...............................................................................................................59
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NORMAL MODE REGISTER DESCRIPTIONS ............................................................................................67
MASTER REGISTERS .................................................................................................................................68
TEST FEATURES DESCRIPTION..............................................................................................................136
TEST MODE 0 DETAILS ...........................................................................................................................138
JTAG TEST PORT....................................................................................................................................139
OPERATION................................................................................................................................................141
SCI-PHY EXTENDED CELL FORMAT .......................................................................................................141
SYNCHRONOUS STATIC RAMS ...............................................................................................................144
OAM CELL FORMAT ................................................................................................................................145
VC IDENTIFICATION SEARCH ALGORITHM .............................................................................................149
JTAG SUPPORT ......................................................................................................................................159
______________________________________________________________________________________________
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PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
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FUNCTIONAL TIMING ................................................................................................................................165
10
:21
INPUT CELL INTERFACE ..........................................................................................................................165
OUTPUT CELL INTERFACE ......................................................................................................................169
02
ABSOLUTE MAXIMUM RATINGS ..............................................................................................................171
20
D.C. CHARACTERISTICS..........................................................................................................................172
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MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS............................................................174
RCMP-800 TIMING CHARACTERISTICS ..................................................................................................179
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ORDERING AND THERMAL INFORMATION ............................................................................................189
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MECHANICAL INFORMATION ...................................................................................................................190
______________________________________________________________________________________________
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STANDARD PRODUCT
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PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
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FEATURES
20
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• Monolithic single chip device which handles ATM switch Ingress VPI/VCI address
translation, cell appending, cell rate policing, counting, and OAM requirements for
65,536 VCs (virtual circuits)
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• Instantaneous transfer rate of 800 Mbit/s supports a cell transfer rate of 1.42x106
cells/s (one STS-12c or four STS-3c).
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• Concentrates the traffic from several PHY interfaces into one switch port.
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• 8 or 16 bit PHY interface using direct addressing for up to 4 PHYs (compatible with
Utopia Level 1 cell-level handshake) and Multi-PHY addressing for up to 32 PHYs
(Utopia Level 2 compatible).
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• 8 or 16 bit extended cell format SCI-PHY (52 - 64 byte extended ATM cell with
prepend/postpend) interface at output to switch fabric.
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• Compatible with wide range of switching fabrics and traffic management
architectures including per VC or per PHY queuing.
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• Provides identification/tagging of RM cells to support adjunct processing
applications such as Virtual Source/Virtual Destination ABR service.
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• Supports logical multicast.
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• Flexible CAM-type cell identification which can use arbitrary VPI/VCI values and/or
cell appended bytes for identification.
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• Discards on command all low priority (high CLP bit) cells to relieve switch
congestion.
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• Can discard or tag the remainder of an AAL5 packet if a single cell in that packet is
discarded or tagged due to policing.
• Includes a 16-bit FIFO buffered microprocessor bus interface for cell extraction and
insertion (including OAM), VC table access, control and status monitoring, and
configuration of the device.
• Supports DMA access for cell extraction and insertion.
• Uses common synchronous SRAMs for maintaining per-VC information.
______________________________________________________________________________________________
1
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
:53
• Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test
purposes.
02
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• Provides a generic 16-bit microprocessor bus interface for configuration, control
and status monitoring.
20
• Low power, 0.6 micron, +5 Volt CMOS technology.
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• 240 copper slugged plastic quad flat pack (PQFP) package.
Policing
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• Policing is performed for adherence to peak cell rate (PCR), cell delay variation
(CDV), sustained cell rate (SCR) and burst tolerance (BT). Violating cells can be
noted, dropped or have CLP bits set to 1.
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• Policing performed by an approximation to the Generic Cell Rate Algorithm
(GCRA).
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• Two policing instantiations available per VC. The policed cell streams can be any
combination of user cells, OAM cells, Resource Management, high priority cells or
low priority cells.
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Cell Counting
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• Counts maintained on a per VC basis include total low priority cells, total high
priority cells and cells violating the traffic contract.
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• Performance management counts are maintained for forward and reverse flows on
a per VC basis: lost cells, misinserted cells, BIP-16 errors and the number of
Severely Errored Cell Blocks (SECB).
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• Counts maintained for entire device include total cells input, total cells output, OAM
cells, cells discarded due to congestion, corrupted OAM cells, and cells with
unassigned/invalid VPI/VCIs.
OAM Handling and Performance Monitoring
• OAM performance monitoring for all VCs as described in ITU-T Recommendation
I.610, Bellcore TR-NWT-001248 and Bellcore GR-1113-CORE.
• Automatic OAM handling includes reception and generation of AIS, RDI, Forward
Monitoring and Backward Reporting cells.
______________________________________________________________________________________________
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PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
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• Backward generated OAM cell identification/tagging provided to enable direct
extraction by Egress device.
02
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• Incoming OAM cells can be terminated or passed to the Output Cell Interface
and/or microprocessor.
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• Outgoing OAM cells sourced from automatic OAM generating circuitry, Input Cell
Interface or microprocessor.
______________________________________________________________________________________________
3
PM7322 RCMP-800
STANDARD PRODUCT
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PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
APPLICATIONS
10
• ATM Hubs and Workgroup Switches
20
02
• ATM Enterprise and Edge Switches
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REFERENCES
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• ATM Forum - ATM User-Network Interface Specification, V3.0, October, 1993
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• ITU-T Recommendation I.361 - "B-ISDN ATM Layer Specification", March 1993
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• ITU-T Recommendation I.371 - "Traffic Control and Congestion Control in BISDN", March 1993
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• ITU-T Recommendation I.610 - "B-ISDN Operation and Maintenance Principles
and Functions", Helsinki, March 1993.
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• Bell Communications Research - Broadband Switching System (BSS) Generic
Requirements, GR-1110-CORE, Issue 1, September 1994.
liv
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• Bell Communications Research -Asynchronous Transfer Mode (ATM) and ATM
Adaptation Layer (AAL) Protocols, GR-1113-CORE, Issue 1, July 1994.
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• Bell Communications Research - Generic Requirements for Operations of
Broadband Switching Systems, TA-NWT-001248, Issue 2, October 1993.
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• IEEE 1149.1 - Standard Test Access Port and Boundary Scan Architecture, May
21, 1990.
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• PMC-940212, ATM_SCI_PHY, "SATURN Compliant Interface For ATM Devices",
July 1994, Issue 2.
• ATM Forum/95-0013R9, Draft Version 3.0 of ATM Forum Traffic Management
Specification Version 4.0, October, 1995
______________________________________________________________________________________________
4
PM7322 RCMP-800
STANDARD PRODUCT
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PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
APPLICATION EXAMPLES
20
02
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The RCMP-800 device is combined with up to 32 PHY devices to implement the
ingress direction an ATM switch port. Two ATM switch port applications are shown in
Figures 1 and 2.
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The RCMP-800 device accepts standard 53 byte cells through a SCI-PHY interface
and outputs cells with variable length pre-pends or post-pends through an extended
cell format SCI-PHY interface. The appendages added by the RCMP-800 are used
by the switch for routing. The HEC can optionally be omitted. The combined
pre-pend and post-pend length can vary from 0 to 10 bytes, with the cells
correspondingly being 52 to 63 octets or 26 to 32 words.
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Backward generated OAM cells and Resource Management cells are specially
labelled by overwriting an appended byte to allow these cells to be processed and
routed in the reverse direction.
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The RCMP-800 utilizes external synchronous RAMs to store VPI/VCI translation
tables and per VPI/VCI switch-specific routing appendages, as well as per VPI/VCI
policing and performance monitoring information. All of this information is stored in a
single structure called the VC table.
Ref.
Clock
19.44 MHz
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P ER VC
P A RAM ET ER
SRA M
PM7322 RCMP-800
ROUTING CONTROL MONITORING AND
POLICING
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TRCLK+/TXD+/-
UT OPIA
L ev e l 1 / 2
Int e rf ac e
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PM5347 S/UNI-PLUS
SONET/SDH
USER NETWORK INTERFACE
RRCLK+/RXD+/ALOS+/-
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O/E
Ext en de d
SCI-PH Y
Int e rf ac e
INGRESS
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Fig. 1 OC-3 Switch Port Application
1
4
OA M / RM
Ce lls
ATM
SWITCHING
FABRIC
PER V C OR PER PHY T RA FF IC
SHA PING A ND A BR RM CELL
PRO CESSIN G
OUT PUT
B UFFER
RA M
EGRESS
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PM7322 RCMP-800
STANDARD PRODUCT
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PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
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Fig. 2 DS-1 PHY Addressing Application
TSOC
TDAT[7:0]
TXPRTY
TCAMPH
TWA[1:0]
TWRMPHB
TFCLK
Single-PHY
or Multi-PHY
interface to
switch
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OSC
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EGRESS
DEVICE
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RSOC
RDAT[7:0]
RXPRTY
RCAMPH
RRA[1:0]
RRDMPHB
RFCLK
4:2
E
1:0
D
Q
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ICA[1]
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IAVALID
IADDR[4:0]
N-to-1
mux
TSOC
TDAT[7:0]
TXPRTY
TCAMPH
TWA[1:0]
TWRMPHB
TFCLK
RSOC
RDAT[7:0]
RXPRTY
RCAMPH
RRA[1:0]
RRDMPHB
RFCLK
S/UNI-MPH
#N
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IBUS8
S/UNI-MPH
#2
3-to-N
decoder
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ISOC
IFCLK
IPOLL
TSOC
TDAT[7:0]
TXPRTY
TCAMPH
TWA[1:0]
TWRMPHB
TFCLK
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IPRTY[0]
Single-PHY
interface to
switch
S/UNI-MPH
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IDAT[7:0]
PM7322
RCMP-800
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load
D
IWRENB[1]
RSOC
RDAT[7:0]
RXPRTY
RCAMPH
RRA[1:0]
RRDMPHB
RFCLK
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Figure 2 illustrates how up to 32 PHY Utopia Level 1 entities may be interfaced to an
RCMP-800. With a minimum amount of support circuitry (eg. a single PAL), the PHY
addressing mode of operation polls the PHY devices to determine the next cell for
transfer. In this example, a quad DS-1 ATM device, the S/UNI-MPH (PM7344),
provides the PHY transmission convergence function. Eight S/UNI-MPH devices
would be required to provide 32 DS-1 ports.
The S/UNI-MPH supports PHY address polling by sampling the two least significant
address bits (RRA[1:0] and TWA[1:0]) and generating the cell available status for the
selected PHY entity. It also holds the last state of RRA[1:0] and TWA[1:0] before the
assertion of RRDMPHB and TWRMPHB, respectively, thus latching the PHY address
resolved by the polling process. The only support logic is that required to select
between the S/UNI-MPH devices.
______________________________________________________________________________________________
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PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:53
The IAVALID output is not required for this application.
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In this application, the aggregate throughput is less than 6.144 Mbyte/s with 32 DS-1
ports; therefore, the clock oscillator frequency can be as low as 6.5 MHz.
______________________________________________________________________________________________
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PM7322 RCMP-800
STANDARD PRODUCT
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PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
BLOCK DIAGRAM
:21
10
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20
02
B U S YB
S D [39 :0 ],
S P [4 :0 ]
SADS
SO EB
S RW B
CONG
S A [1 9 :0 ]
TR S TB
TC K
TM S
TD I
TD O
T o E x tern a l R A M
M ic ro p r o c e s s or
R AM
A rb itra tio n
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E x te r n a l
R AM
Addres s
Lookup
C e ll
P ro c e s s o r
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JTAG Test
Access
Port
9S
S YS C L K
ID A T[1 5 :0 ]
IP R TY[1 :0 ]
IS O C
IFC L K
ORDENB
OBUS8
OTSEN
nT
IP O L L
IB U S 8
io
A ll B lo c k s
M ic ro
C e ll
B u ffe r
DREQ
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D [1 5 :0]
A [6:0 ]
A LE
CSB
W RB
RDB
R S TB
IN TB
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ONESEC
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M ic ro p ro c e s s or
In te rfa c e
S C I-P H Y + In te rfa c e
(a p p e n d e d A T M C e lls )
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IA D D R [2 :0 ]/IW R E N B [4 :2 ]
IW R E N B [1 ]
U to p ia L e ve l 1 o r 2
In te rfa c e
O u tp u t
F IF O
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IA V A LID /IC A [4 ]
IA D D R [4 :3 ]/IC A [3 :2 ]
IC A [1 ]
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In p u t
F IF O
O D A T[1 5 :0 ]
O P R TY[1 :0 ]
OSOC
O FC L K
OCA
______________________________________________________________________________________________
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PM7322 RCMP-800
STANDARD PRODUCT
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PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
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DESCRIPTION
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The PM7322 Routing Control, Monitoring and Policing 800 Mbps (RCMP-800) device
is a monolithic integrated circuit that implements ATM layer functions that include
fault and performance monitoring, header translation and cell rate policing. The
RCMP-800 is intended to be situated between a switch core and the physical layer
devices in the ingress direction. The RCMP-800 supports a sustained aggregate
throughput of 1.42x106 cells/s. The RCMP-800 uses external SRAM to store
per-VPI/VCI data structures. The device is capable of supporting up to 65536
connections.
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The Input Cell Interface can be connected to up to 32 physical layer devices through
a SCI-PHY compatible bus. The 53 byte ATM cell is encapsulated in a data structure
which can contain pre-pended or post-pended routing information. Received cells
are buffered in a four cell deep FIFO. All Physical Layer and unassigned cells are
discarded. For the remaining cells, a subset of ATM header and appended bits is
used as a search key to find the VC Table Record for the virtual connection. If a
connection is not provisioned and the search terminates unsuccessfully as a result,
the cell is discarded and a count of invalid cells is incremented. If the search is
successful, subsequent processing of the cell is dependent on contents of the cell
and configuration fields in the VC Table Record.
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The RCMP-800 performs header translation if so configured. The ATM header is
replaced by contents of fields in the VC Table Record for the connection. The VCI
contents are passed through transparently for VPCs. Appended bytes can be
replaced, added or removed.
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If the RCMP-800 is the end point for a F4 or F5 OAM stream, the OAM cells are
dropped and processed. If the RCMP-800 is not the end point, the OAM cells are
passed to the Output Cell Interface with an optional copy passed to the
Microprocessor Cell Buffer. The reception of an AIS or RDI cell results in the
appropriate alarm. Upon the arrival of a Forward Monitoring or Monitoring/Reporting
cell, error counts are updated and a Backward Reporting cell is optionally generated.
Activate/Deactivate cells are passed to the Microprocessor Cell Buffer for external
processing. Continuity Check cells can be generated if no user cells have been
received in the latest 1.5 +/- 0.5 or 2.5 +/- 0.5 (default) seconds.
Cell rate policing is supported through two instances of the Generic Cell Rate
Algorithm (GCRA) for each connection. Each cell that violates the traffic contract can
be tagged (CLP bit set high) or discarded. To allow full flexibility, each GCRA
instance can be programmed to police any combination of user cells, OAM cells,
Resource Management, high priority cells or low priority cells.
______________________________________________________________________________________________
9
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
:21
:53
The RCMP-800 supports multicasting. A single received cell can result in an arbitrary
number of cells presented on the Output Cell Interface, each with its own unique
VPI/VCI value and appended bytes. The ATM cell payload is duplicated without
modification.
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02
The Output Cell Interface can be connected to the switch core through an extended
cell format SCI-PHY compatible bus. Cells are stored in a four cell deep FIFO until
the downstream devices are ready to accept them. The details of how cells are
handled in this FIFO depends on the particular application of the RCMP-800 and are
presented in "Operational Modes" section.
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The Microprocessor Interface is provided for device configuration, control and
monitoring by an external microprocessor. This interface provides access to the
external SRAM to allow creation of the data structure, configuration of individual
connections and monitoring of the connections. The Microprocessor Cell Buffer gives
access to the cell stream, either directly or through intervention by a DMA controller.
Programmed cell types can be routed to a microprocessor readable sixteen cell
FIFO. The microprocessor can send cells over the Output Cell Interface.
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The RCMP-800 is implemented in low power, 0.6 micron, +5 Volt CMOS technology.
It has TTL compatible inputs and outputs and is packaged in a 240 pin copper
slugged plastic QFP package.
______________________________________________________________________________________________
10
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
PIN DIAGRAM
PIN 180
tem
be
PIN 1
NC
VSS_AC
VDD_AC
SA[9]
SA[8]
SA[7]
SA[6]
SA[5]
SA[4]
VSS_AC
VDD_AC
VSS_DC
VDD_DC
SA[3]
SA[2]
SA[1]
SA[0]
SD[15]
SD[14]
SD[13]
VDD_AC
VSS_AC
VSS_DC
VDD_DC
SD[12]
SD[11]
SD[10]
SD[9]
SD[8]
VSS_AC
VDD_AC
VSS_DC
VDD_DC
SYSCLK
NC
NC
NC
VSS_DC
VDD_DC
SP[1]
SD[7]
SD[6]
SD[5]
SD[4]
SD[3]
VSS_AC
VDD_AC
SD[2]
SD[1]
SD[0]
SP[0]
NC
VSS_DC
VDD_DC
OFCLK
VSS_DC
VDD_DC
CONG
OTSEN
NC
PM7322
RCMP-800
TOP VIEW
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Pin 1 Index
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PIN 61 n
loa
de
NC
IDAT[15]
IDAT[14]
IDAT[13]
IDAT[12]
IDAT[11]
IDAT[10]
IDAT[9]
IDAT[8]
IDAT[7]
VDD_DC
VSS_DC
IDAT[6]
IDAT[5]
IDAT[4]
IDAT[3]
IDAT[2]
IDAT[1]
IDAT[0]
IPRTY[1]
IPRTY[0]
ISOC
IAVALID/ICA[4]
IADDR[4]/ICA[3]
VDD_AC
VSS_AC
IADDR[3]/ICA[2]
ICA[1]
IADDR[2]/IWRENB[4]
IADDR[1]/IWRENB[3]
VDD_DC
VSS_DC
IADDR[0]/IWRENB[2]
IWRENB[1]
IPOLL
IBUS8
VDD_AC
VSS_AC
VDD_DC
VSS_DC
IFCLK
VDD_DC
VSS_DC
TCK
TMS
TDI
TDO
TRSTB
D[0]
D[1]
D[2]
D[3]
VDD_DC
VSS_DC
VDD_AC
VSS_AC
D[4]
D[5]
D[6]
D[7]
PIN 181
02
r,
20
VSS_DC
VDD_DC
SD[39]
SD[38]
SD[37]
VSS_AC
VDD_AC
SD[36]
SD[35]
VSS_DC
VDD_DC
SD[34]
SD[33]
SD[32]
SP[4]
SD[31]
SD[30]
VSS_AC
VDD_AC
SD[29]
SD[28]
SD[27]
SD[26]
SD[25]
VSS_DC
VDD_DC
SD[24]
SP[3]
VSS_AC
VDD_AC
SD[23]
SD[22]
SD[21]
SD[20]
SD[19]
SD[18]
SD[17]
VSS_AC
VDD_AC
VSS_DC
VDD_DC
SD[16]
SP[2]
SA[19]
SA[18]
SA[17]
SA[16]
SA[15]
VSS_AC
VDD_AC
SA[14]
SA[13]
SA[12]
SA[11]
VSS_DC
VDD_DC
SA[10]
SOEB
SRWB
SADSB
PIN 240
10
The RCMP-800 is packaged in a 240 pin slugged plastic QFP package having a body
size of 32 mm by 32 mm and a pin pitch of 0.5 mm.
PIN 120
PIN 121
D[8]
D[9]
D[10]
D[11]
VDD_AC
VSS_AC
VDD_DC
VSS_DC
D[12]
D[13]
D[14]
D[15]
INTB
BUSYB
DREQ
RDB
WRB
CSB
VDD_DC
VSS_DC
ONESEC
RSTB
ALE
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
ODAT[15]
ODAT[14]
ODAT[13]
VDD_DC
VSS_DC
ODAT[12]
ODAT[11]
VDD_AC
VSS_AC
ODAT[10]
ODAT[9]
ODAT[8]
ODAT[7]
ODAT[6]
ODAT[5]
ODAT[4]
ODAT[3]
VDD_DC
VSS_DC
VDD_AC
VSS_AC
ODAT[2]
ODAT[1]
ODAT[0]
OPRTY[1]
OPRTY[0]
OSOC
OCA
ORDENB
OBUS8
PIN 60
______________________________________________________________________________________________
11
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
PIN DESCRIPTION (TOTAL 240)
10
Output Cell Interface Signals (24)
Type
Pin
No.
OFCLK
Input
126
The output FIFO clock (OFCLK) is used to read words
from the Output Cell Interface. OFCLK must cycle at
a 52 MHz or lower instantaneous rate, but at a high
enough rate to avoid FIFO overflow. OSOC, OCA,
OPRTY[1:0] and ODAT[15:0] are updated on the
rising edge of OFCLK. ORDENB is sampled using the
rising edge of OFCLK.
OBUS8
Input
120
The 8-bit bus width select (OBUS8) input selects the
Output Cell Interface bus width. When OBUS8 is tied
high, a 10-bit interface consisting of a start of cell
indication, parity bit and an 8-bit octet bus is selected.
When OBUS8 is tied low, a 19-bit interface consisting
of a start of cell indication, two parity bits and a 16-bit
word bus is selected.
ORDENB
Input
119
The active low read enable (ORDENB) signal is used
to indicate transfers from the Output Cell Interface.
When ORDENB is sampled low using the rising edge
of OFCLK, a word is read from the internal
synchronous FIFO and output on bus ODAT[15:0].
When ORDENB is sampled high using the rising edge
of OFCLK, no read is performed and outputs
ODAT[15:0], OPRTY[1:0] and OSOC are tristated if
the OTSEN input is high. ORDENB must operate in
conjunction with OFCLK to access the FIFO at a high
enough instantaneous rate as to avoid FIFO
overflows.
02
Pin
Name
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
tem
be
r,
20
Feature
______________________________________________________________________________________________
12
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
Tristate 114
113
112
107
106
105
104
103
102
101
100
97
96
93
92
91
The output cell data (ODAT[15:0]) bus carries the
ATM cell octets that are read from the output FIFO. If
the IBUS8 input is high, only ODAT[7:0] carries cell
octets. The ODAT[15:0] bus is updated on the rising
edge of OFCLK.
OPRTY[0]
OPRTY[1]
Tristate 116
115
The output parity (OPRTY[1:0]) signals indicate the
parity of the ODAT[15:0] bus. OPRTY[1] is the parity
calculation over the ODAT[15:8] bus. OPRTY[0] is the
parity calculation over the ODAT[7:0] bus. Alternately
the device can be configured so that OPRTY[1] is the
parity calculation over the entire ODAT[15:0] bus.
Odd or even parity selection can be made using a
register bit. OPRTY[1:0] is updated on the rising edge
of OFCLK.
02
10
:21
:53
ODAT[0]
ODAT[1]
ODAT[2]
ODAT[3]
ODAT[4]
ODAT[5]
ODAT[6]
ODAT[7]
ODAT[8]
ODAT[9]
ODAT[10]
ODAT[11]
ODAT[12]
ODAT[13]
ODAT[14]
ODAT[15]
tem
be
r,
20
When the Output Cell Interface is configured for
tristate operation using the OTSEN input, tristating of
the ODAT[15:0] output bus is controlled by the
ORDENB input.
Tristate 117
Do
wn
loa
de
OSOC
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
When OTSEN is low, the ODAT[15:0] bus is low when
no cell is being transferred.
When the Output Cell Interface is configured for tristate
operation using the OTSEN input, tristating of the
OPRTY[1:0] output bus is controlled by the ORDENB
input.
The output start of cell (OSOC) signal marks the start
of cell on the ODAT[15:0] bus. When OSOC is high,
the first word of the cell structure is present on the
ODAT[15:0] stream. OSOC is updated on the rising
edge of OFCLK.
When the Output Cell Interface is configured for tristate
operation using the OTSEN input, tristating of the
OSOC output is controlled by the ORDENB input.
______________________________________________________________________________________________
13
PM7322 RCMP-800
STANDARD PRODUCT
118
The active polarity of this signal is programmable and
defaults to active high.
:53
Output
:21
OCA
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
122
The tristate enable (OTSEN) signal allows tristate
control over the ODAT[15:0], OPRTY[1:0] and OSOC
outputs. When OTSEN is high, the active low read
enable input, ORDENB, controls when the
ODAT[15:0], OPRTY[1:0] and OSOC outputs are
driven. When OTSEN is low, the ODAT[15:0],
OPRTY[1:0] and OSOC outputs are always driven.
ep
Input
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
OTSEN
tem
be
r,
20
02
10
OCA indicates when a cell is available in the output
FIFO. When asserted, the OCA signal indicates that
the output FIFO has at least one cell available to be
read. The OCA signal is deasserted when the output
FIFO contains four or zero words available for the
current cell. Selection is made using the OCALEVEL0
bit in the Output FIFO Configuration register. OCA is
updated on the rising edge of OFCLK.
______________________________________________________________________________________________
14
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
Input Cell Interface Signals (30)
Type
Pin
No.
IFCLK
Input
41
The input FIFO clock (IFCLK) is used to write words to
the synchronous FIFO interface. IFCLK must cycle at
a 52 MHz or lower instantaneous rate. ISOC,
ICA[4:1], IPRTY[1:0] and IDAT[15:0] are sampled on
the rising edge of IFCLK. IWRENB[4:1], IADDR[4:0]
and IAVALID are updated on the rising edge of IFCLK.
IPOLL
Input
35
The input polling select (IPOLL) pin determines the
method used to poll PHY devices.
10
Pin
Name
,1
9S
ep
tem
be
r,
20
02
Feature
hu
rsd
ay
If IPOLL is low, the IWRENB[4:1] and ICA[4:1] signals
are connected directly to up to four single-PHY
entities.
36
The bus width select (IBUS8) input selects the input
FIFO interface bus width. When IBUS8 is tied high, a
10-bit interface consisting of a start of cell indication,
an 8-bit octet bus, and a parity bit is selected. When
IBUS8 is low, a 19-bit interface consisting of a start of
cell indication, a 16-bit word bus, and two parity bits is
selected.
liv
Input
Do
wn
loa
de
db
yV
inv
ef
uo
fo
IBUS8
ett
io
nT
If IPOLL is high, polling using address lines is used.
The RCMP-800 uses the IADDR[4:0] and IAVALID
outputs to perform sequential polling of the PHY
devices to determine the next cell to transfer.
______________________________________________________________________________________________
15
PM7322 RCMP-800
STANDARD PRODUCT
:21
:53
The active low write enable (IWRENB[4:1]) inputs are
used to initiate writes to the input FIFO.
If the IPOLL input is low, the RCMP-800 asserts one
of the IWRENB[4:1] outputs to transfer a cell from one
of up to four PHY devices. A valid word is expected
on the IDAT[15:0] bus at the second rising edge of
IFCLK after one of the enables is asserted low. When
all of the enables are high, no valid data is expected.
The IWRENB[4:1] outputs are updated on the rising
edge of IFCLK. See Figure 7.
10
34
33
30
29
tem
be
r,
20
02
IWRENB[1] Output
IWRENB[2]
IWRENB[3]
IWRENB[4]
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
rsd
If the IPOLL input is high, the IADDR[4:0] pins are
used for PHY addressing. If the IPOLL input is low,
the IADDR[4:0] pins are redefined as ICA[3:2] and
IWRENB[4:2].
hu
24
27
29
30
33
nT
I/O
If the IPOLL input is high, the IADDR[4:0] signals are
outputs and are used to address up to 32 PHY
devices for the purposes of polling and selection for
cell transfer. When conducting polling, in order to
avoid bus contention, the RCMP-800 inserts gap
cycles during which IADDR[4:0] is set to 1F hex and
IAVALID to logic 0. When this occurs, no PHY device
should drive ICA[1] during the following clock cycle.
Polling is performed in a incrementing sequential
order. The PHY device selected for transfer is based
on the IADDR[4:0] value present when IWRENB[1]
falls. The IADDR[4:0] bus is updated on the rising
edge of IFCLK.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
IADDR[4]
IADDR[3]
IADDR[2]
IADDR[1]
IADDR[0]
ay
,1
9S
ep
If the IPOLL input is high, the IWRENB[4:2] pins are
redefined as IADDR[2:0]. The IWRENB[1] pin is used
to transfer all cells. The source PHY is selected by the
IADDR[4:0] signals.
______________________________________________________________________________________________
16
PM7322 RCMP-800
STANDARD PRODUCT
23
If the IPOLL input is high, the PHY Address Valid
(IAVALID) pin is active. If the IPOLL input is low, the
IAVALID pin is redefined as ICA[4].
:53
I/O
10
:21
IAVALID
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
r,
20
02
If the IPOLL input is high, the IAVALID pin indicates
that the IADDR[4:0] bus is outputting a valid PHY
address for polling purposes. When this signal is
deasserted, the IADDR[4:0] bus is set to 1F hex.
ep
9S
,1
ay
rsd
hu
nT
io
ett
Input
The input cell data (IDAT[15:0]) bus carries the ATM
cell octets that are written to the input FIFO. The
IDAT[15:0] bus is sampled on the rising edge of
IFCLK and is considered valid only when one of the
IWRENB[4:1] signals so indicates.
liv
IPRTY[0]
IPRTY[1]
19
18
17
16
15
14
13
10
9
8
7
6
5
4
3
2
fo
Input
ef
uo
IDAT[0]
IDAT[1]
IDAT[2]
IDAT[3]
IDAT[4]
IDAT[5]
IDAT[6]
IDAT[7]
IDAT[8]
IDAT[9]
IDAT[10]
IDAT[11]
IDAT[12]
IDAT[13]
IDAT[14]
IDAT[15]
tem
be
IAVALID is not necessary when less than 32 PHY
links are being polled.
inv
yV
db
Do
wn
loa
de
21
20
The input parity (IPRTY[1:0]) signals indicate the parity
of the IDAT[15:0] bus. IPRTY[1] is expected to be the
parity calculation over the IDAT[15:8] bus. IPRTY[0] is
expected to be the parity calculation over the IDAT[7:0]
bus. Alternately the device can be configured so that
IPRTY[1] is expected to be the parity calculation over
the entire IDAT[15:0] bus. Odd or even parity selection
can be made using a register. A maskable interrupt
status is generated upon a parity error; no other
actions are taken. IPRTY[1:0] is sampled on the rising
edge of IFCLK and is considered valid only when one
of the IWRENB[4:1] signals so indicates.
______________________________________________________________________________________________
17
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
Input
22
The input start of cell (ISOC) signal marks the start of
cell on the IDAT[15:0] bus. When ISOC is high, the
first word of the cell structure is present on the
IDAT[15:0] stream. It is not necessary for ISOC
asserted for each cell. An interrupt may be generated
if ISOC is high during any word other than the first
word of the cell structure. ISOC is sampled on the
rising edge of IFCLK and is considered valid only when
one of the IWRENB[4:1] signals so indicates.
ICA[1]
ICA[2]
ICA[3]
ICA[4]
I/O
28
27
24
23
The active polarity of these signals is programmable
and defaults to active high.
ep
tem
be
r,
20
02
10
:21
:53
ISOC
ett
io
nT
hu
rsd
ay
,1
9S
If the IPOLL input is low, the RCMP-800 asserts the
appropriate IWRENB[4:1] signal in response to a
round-robin polling of the ICA[4:1] signals. Once
committed, the RCMP-800 will transfer an entire cell
from a single physical link before servicing the next.
The RCMP-800 will complete the read of an entire cell
even if the associated ICA[4:1] input is deasserted
during the cell. Sampling of ICA[4:1] resumes the
cycle after the last octet of a cell has been transferred.
liv
Note that ICA[1] is an input only.
If the IPOLL input is high, the ICA[3:2] pins are
redefined as IADDR[4:3] and the ICA[4] pin is
redefined as IAVALID.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
ICA[4:1]
(cont.)
If the IPOLL input is high, the RCMP-800 polls up to 32
PHY devices using the PHY address signals
IADDR[4:0]. A PHY device being addressed by
IADDR[4:0] is expected to indicate whether or not it
has a complete cell available for transfer by driving
ICA[1] during the clock cycle following that in which it is
addressed. (When a cell transfer is in progress, the
RCMP-800 will not poll the PHY device which is
sending the cell and so PHY devices need not support
cell availability indication during cell transfer.) The
selection of a particular PHY device from which to
transfer a cell is indicated by the state of IADDR[4:0]
when IWRENB[1] falls.
Note that ICA[1] is an input only
______________________________________________________________________________________________
18
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
10
20
02
The SRAM Address (SA[19:0]) outputs identify the
SRAM location accessed.
9S
ep
tem
be
r,
The sixteen least significant bits (SA[15:0] locate one
of a possible 65536 VC Table entries. If 65536
connections are not required, the most significant bits
of SA[15:0] may be unconnected with no physical
memory associated with the unused memory space.
rsd
ay
,1
The four most significant bits (SA[19:16]) identify the
fields within a VC Table Record. In most applications,
SA[19:16] is decoded to SRAM chip selects. Physical
memory need not be allocated for unused fields.
nT
hu
The SA[15:0] outputs are also used to access the
Search Table.
io
The SA[19:0] bus is updated on the rising edge of
SYSCLK.
ett
197
196
195
194
193
190
189
188
187
184
177
176
175
174
173
172
167
166
165
164
liv
Output
Feature
Do
wn
loa
de
db
yV
inv
ef
uo
SA[19]
SA[18]
SA[17]
SA[16]
SA[15]
SA[14]
SA[13]
SA[12]
SA[11]
SA[10]
SA[9]
SA[8]
SA[7]
SA[6]
SA[5]
SA[4]
SA[3]
SA[2]
SA[1]
SA[0]
Pin
No.
Type
fo
Pin
Name
:53
Synchronous SRAM Interface Signals (70)
______________________________________________________________________________________________
19
PM7322 RCMP-800
STANDARD PRODUCT
:21
:53
The bi-directional SRAM Data (SD[39:0]) pins interface
directly with synchronous SRAM data ports.
tem
be
r,
20
02
10
A SRAM read is performed when the RCMP-800 drives
the address strobe (SADSB) low and the SRWB output
high. The RCMP-800 tristates the SD[39:0] pins and
samples the value driven by the SRAM on the second
rising edge of the SYSCLK input after SADSB is
asserted.
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
A SRAM write is performed when RCMP-800 drives
the address strobe (SADSB) low and the SRWB output
low. The RCMP-800 presents valid data on the
SD[39:0] pins upon the rising edge of SYSCLK which
is written into the SRAM on the next SYSCLK rising
edge. SD[39:0] is tri-stated on the rising edge of
SYSCLK. Contention is avoided by not performing a
read during the cycle after the write burst.
fo
238
237
236
233
232
229
228
227
225
224
221
220
219
218
217
214
210
209
208
207
206
205
204
199
163
162
161
156
155
154
153
152
140
139
138
137
136
133
132
131
db
yV
inv
ef
uo
I/O
Do
wn
loa
de
SD[39]
SD[38]
SD[37]
SD[36]
SD[35]
SD[34]
SD[33]
SD[32]
SD[31]
SD[30]
SD[29]
SD[28]
SD[27]
SD[26]
SD[25]
SD[24]
SD[23]
SD[22]
SD[21]
SD[20]
SD[19]
SD[18]
SD[17]
SD[16]
SD[15]
SD[14]
SD[13]
SD[12]
SD[11]
SD[10]
SD[9]
SD[8]
SD[7]
SD[6]
SD[5]
SD[4]
SD[3]
SD[2]
SD[1]
SD[0]
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
______________________________________________________________________________________________
20
PM7322 RCMP-800
STANDARD PRODUCT
:53
The SRAM Parity (SP[4:0]) pins provide parity
protection over the SD[39:0] bus.
:21
226
213
198
141
130
SP[4] completes odd parity for SD[39:32].
SP[3] completes odd parity for SD[31:24].
SP[2] completes odd parity for SD[23:16].
SP[1] completes odd parity for SD[15:8].
SP[0] completes odd parity for SD[7:0].
10
I/O
r,
20
02
SP[4]
SP[3]
SP[2]
SP[1]
SP[0]
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
Output
181
The SRAM Address Strobe (SADSB) qualifies the
address bus. If the SADSB output is asserted low, an
SRAM access is initiated.
nT
hu
SADSB
rsd
ay
,1
9S
ep
tem
be
SP[4:0] has the same timing as SD[39:0]. When data
is being written to the external SRAM, the RCMP-800
generates correct parity. When data is being read
from the external SRAM, the RCMP-800 checks the
parity and generates a maskable interrupt indication
upon an error. No other action is taken; therefore, the
SP[4:0] may be unconnected if parity protection is not
required.
183
The asynchronous SRAM Output Enable (SOEB)
controls the SRAM tri-state outputs. When SOEB is
low during a read cycle, the selected SRAM (as
determined by SA[19:0] decoding) is expected to drive
SD[39:0] and SP[4:0].
ett
Output
yV
Output
Do
wn
loa
de
db
SRWB
inv
ef
uo
fo
liv
SOEB
io
SADSB is updated on the rising edge of SYSCLK.
182
SOEB is updated on the rising edge of SYSCLK.
The SRAM read/write enable (SRWB) determines the
SRAM access type. SRWB is qualified by the SADSB
output. The RCMP-800 drives the SRWB output high
if the subsequent cycle is a SRAM read. The RCMP800 drives the SRWB output low if the current cycle is
a SRAM write.
SRWB is updated on the rising edge of SYSCLK.
______________________________________________________________________________________________
21
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
Input
78
10
CSB
Feature
02
Pin
No.
CSB is low during RCMP-800 Microprocessor Interface
Port register accesses.
20
Type
r,
Pin
Name
:21
Microprocessor Interface Signals (30)
ep
tem
be
If CSB is not required (i.e. register accesses controlled
using the RDB and WRB signals only), CSB should be
connected to an inverted version of the RSTB input.
Input
76
RDB is low during RCMP-800 Microprocessor Interface
Port register read accesses. The RCMP-800 drives
the D[15:0] bus with the contents of the addressed
register while RDB and CSB are low.
WRB
Input
77
WRB is low during a RCMP-800 Microprocessor
Interface Port register write accesses. The D[15:0] bus
contents are clocked into the addressed register on the
rising WRB edge while CSB is low.
DREQ
Output
75
The DMA request (DREQ) output is asserted when the
Microprocessor Cell Buffer contains a cell to be read
and the DMAEN bit in the Microprocessor Buffer
Configuration register is a logic 1. The first read of the
Microprocessor Cell Data register after DREQ is
asserted will return the first word of the cell. DREQ is
deasserted after the last word of the cell has been read
or an abort has been signaled.
The polarity of the DREQ output is programmable and
defaults to active high.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
RDB
______________________________________________________________________________________________
22
PM7322 RCMP-800
STANDARD PRODUCT
74
The BUSYB output is asserted while a µP access
request to the external SRAM is pending. The BUSYB
output is deasserted after the access has been
completed. A µP access request is typically completed
within 37 SYSCLK cycles. If the STANDBY bit in the
Master Configuration is a logic 1, the access time is
reduced to less than 5 SYSCLK cycles. The polarity of
the BUSYB output is programmable and defaults to
active low.
:53
Output
tem
be
r,
20
02
10
:21
BUSYB
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
liv
ett
io
nT
hu
rsd
ay
,1
9S
The bi-directional data bus D[15:0] is used during
RCMP-800 Microprocessor Interface Port register read
and write accesses. D[15:8] should contain the most
significant byte of a word while D[7:0] should contain
the least significant byte of a word.
fo
49
50
51
52
57
58
59
60
61
62
63
64
69
70
71
72
ef
uo
I/O
Input
ALE
Input
Do
wn
loa
de
db
yV
A[0]
A[1]
A[2]
A[3]
A[4]
A[5]
A[6]/TRS
inv
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
D[8]
D[9]
D[10]
D[11]
D[12]
D[13]
D[14]
D[15]
ep
The BUSYB should be treated as a glitch-free
asynchronous output.
90
89
88
87
86
85
84
A[6:0] selects specific Microprocessor Interface Port
registers during RCMP-800 register accesses. A[6] is
the Test Register Select (TRS) address pin. TRS
selects between normal and test mode register
accesses. TRS is high during test mode register
accesses, and is low during normal mode register
accesses.
83
ALE is active high and latches the address bus A[6:0]
when low. When ALE is high, the internal address
latches are transparent. It allows the RCMP-800 to
interface to a multiplexed address/data bus. ALE has
an integral pull up resistor.
______________________________________________________________________________________________
23
PM7322 RCMP-800
STANDARD PRODUCT
The interrupt request (INTB) output goes low when a
RCMP-800 interrupt source is active and that source is
unmasked. INTB returns high when the interrupt is
acknowledged via an appropriate register access.
INTB is an open drain output.
:53
73
:21
OD
Output
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
tem
be
r,
20
02
10
INTB
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
______________________________________________________________________________________________
24
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
Misc. Interface Signals (66)
Type
Pin
No.
SYSCLK
Input
147
The system clock (SYSCLK) provides timing for the
RCMP-800's internal circuitry. SYSCLK should be
nominally a 50% duty cycle 25 MHz to 52 MHz clock.
SYSCLK should be connected to the same clock
buffer as the external synchronous SRAM clock.
CONG
Input
123
The congestion indication (CONG) input signals that
cell congestion is occurring in an element downstream
of the RCMP-800 and that all low priority cells be
dropped. If CONG is high, the RCMP-800 drops all
cells with a one in the CLP bit position after policing
has occurred, except AAL5 end-of-message (EOM)
cells. (Dropping an EOM cell results in corrupting two
packets; this does help to relieve the congestion.)
10
Pin
Name
nT
hu
rsd
ay
,1
9S
ep
tem
be
r,
20
02
Feature
81
The one second clock (ONESEC) provides precise
timing for events such as the generation of RDI and
AIS cell and the clearing of AIS, RDI and Continuity
Check alarms.
ett
Input
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ONESEC
io
CONG may be treated as an asynchronous input.
RSTB
Scmitt
Trigger
Input
Internal
Pull-up
By default, the initiation of one second events is based
on the SYSCLK period; therefore, the ONESEC input
is ignored. If the SEL1SEC register bit is a logic 1, the
ONESEC input becomes the source of the one second
clock.
ONESEC must be glitch free and may be treated as an
asynchronous input.
82
The active low reset (RSTB) signal provides an
asynchronous RCMP-800 reset. RSTB is a Schmitt
triggered input with an integral pull up resistor. When
RSTB is forced low, all RCMP-800 registers are forced
to their default states.
______________________________________________________________________________________________
25
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
Input
44
The test clock (TCK) signal provides timing for test
operations that can be carried out using the IEEE
P1149.1 test access port.
TMS
Input
45
The test mode select (TMS) signal controls the test
operations that can be carried out using the IEEE
P1149.1 test access port. TMS is sampled on the
rising edge of TCK. TMS has an integral pull up
resistor.
46
The test data input (TDI) signal carries test data into
the RCMP-800 via the IEEE P1149.1 test access port.
TDI is sampled on the rising edge of TCK. TDI has an
integral pull up resistor.
Input
ep
Internal
Pull-up
9S
TDI
tem
be
r,
20
02
Internal
Pull-up
10
:21
:53
TCK
Tristate
47
The test data output (TDO) signal carries test data out
of the RCMP-800 via the IEEE P1149.1 test access
port. TDO is updated on the falling edge of TCK. TDO
is a tri-state output which is tri-stated except when
scanning of data is in progress.
TRSTB
Scmitt
Trigger
Input
48
The active low test reset (TRSTB) signal provides an
asynchronous RCMP-800 test access port reset via
the IEEE P1149.1 test access port. TRSTB is a
Schmitt triggered input with an integral pull up resistor.
ett
io
nT
hu
rsd
ay
,1
TDO
liv
Internal
Pull-up
Do
wn
loa
de
db
yV
inv
ef
uo
fo
The JTAG TAP controller must be initialized when the
RCMP-800 is powered up. If the JTAG port is not
used TRSTB must be connected to the RSTB input or
VSS.
______________________________________________________________________________________________
26
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
Power
11
31
39
42
53
67
79
94
108
124
127
142
148
157
168
185
200
215
230
239
The DC power (VDD_DC1 - VDD_DC20) pins should
be connected to a well-decoupled +5 V DC supply in
common with VDD_AC.
VSS_DC1
VSS_DC2
VSS_DC3
VSS_DC4
VSS_DC5
VSS_DC6
VSS_DC7
VSS_DC8
VSS_DC9
VSS_DC10
VSS_DC11
VSS_DC12
VSS_DC13
VSS_DC14
VSS_DC15
VSS_DC16
VSS_DC17
VSS_DC18
VSS_DC19
VSS_DC20
Ground
12
32
40
43
54
68
80
95
109
125
128
143
149
158
169
186
201
216
231
240
The DC ground (VSS_DC1 - VSS_DC20) pins should
be connected to GND in common with VSS_AC.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
tem
be
r,
20
02
10
:21
:53
VDD_DC1
VDD_DC2
VDD_DC3
VDD_DC4
VDD_DC5
VDD_DC6
VDD_DC7
VDD_DC8
VDD_DC9
VDD_DC10
VDD_DC11
VDD_DC12
VDD_DC13
VDD_DC14
VDD_DC15
VDD_DC16
VDD_DC17
VDD_DC18
VDD_DC19
VDD_DC20
______________________________________________________________________________________________
27
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
Power
25
37
55
65
98
110
134
150
160
170
178
191
202
211
222
234
The AC power (VDD_AC1 - VDD_AC16) pins should
be connected to a well-decoupled +5 V DC supply in
common with VDD_DC.
VSS_AC1
VSS_AC2
VSS_AC3
VSS_AC4
VSS_AC5
VSS_AC6
VSS_AC7
VSS_AC8
VSS_AC9
VSS_AC10
VSS_AC11
VSS_AC12
VSS_AC13
VSS_AC14
VSS_AC15
VSS_AC16
Ground
26
38
56
66
99
111
135
151
159
171
179
192
203
212
223
235
The AC ground (VSS_AC1 - VSS_AC16) pins should
be connected to GND in common with VSS_DC.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
tem
be
r,
20
02
10
:21
:53
VDD_AC1
VDD_AC2
VDD_AC3
VDD_AC4
VDD_AC5
VDD_AC6
VDD_AC7
VDD_AC8
VDD_AC9
VDD_AC10
VDD_AC11
VDD_AC12
VDD_AC13
VDD_AC14
VDD_AC15
VDD_AC16
______________________________________________________________________________________________
28
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
Notes on Pin Description:
02
10
1. All RCMP-800 inputs and bi-directionals present minimal capacitive loading and
operate at TTL logic levels.
20
2. All RCMP-800 digital outputs and bi-directionals have 2 mA D.C. drive capability.
tem
be
r,
3. Inputs RSTB, TRSTB, TMS, TDI and ALE have internal pull-up resistors.
9S
ep
4. The VSS_DC and VSS_AC ground pins are not internally connected together.
Failure to connect these pins externally may cause malfunction or damage the
RCMP-800.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
5. The VDD_DC and VDD_AC power pins are not internally connected together.
Failure to connect these pins externally may cause malfunction or damage the
RCMP-800.
______________________________________________________________________________________________
29
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
FUNCTIONAL DESCRIPTION
20
02
10
The RCMP-800 receives cells from up to 32 PHY devices, processes them, and
passes them to a single switch port or queue manager. The RCMP-800 device
operates as a multi-PHY master on its input side. Round-robin polling selects
between the PHY devices based on the availability of cells.
ep
tem
be
r,
The Output Cell Interface operates as a single-PHY slave. The RCMP-800 informs
the bus master if it has a cell available for transfer out by asserting OCA, and waits
for the bus master to assert the ORDENB signal to effect the transfer. If the output
buffer becomes full, the RCMP-800 will apply back-pressure to all its input PHYs.
ay
,1
9S
Logical multicasting is possible, although the system design must take into account
the fact that the input PHYs may be backed-up as a result - with possible cell loss
occurring.
hu
rsd
Input Buffering
ett
io
nT
Cells received on the extended cell format SCI-PHY compatible Input Cell Interface
are buffered in a 4 cell deep FIFO. The input buffer provides for the separation of
internal timing from asynchronous external devices.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
The SCI-PHY cell interface operates at clock rates up to 52 MHz and supports 16 bit
and 8 bit wide data structures with programmable lengths. The 16 bit data structure
contains 26 (HEC and User Defined Field excluded) or 27 words allocated to carrying
an ATM cell and up to 5 appended words. The 8 bit data structure contains a 52
(HEC excluded) or 53 byte ATM cell and up to 10 appended bytes. The start of the
data structure is indicated by the ISOC input. Refer to the "Operation" section for
more detail on these data structures. The data bus is protected by the IPRTY[1:0]
inputs. The parity can be configured to be odd or even. Each parity input can cover
a byte or IPRTY[1] can cover all sixteen data inputs.
The input FIFO filters all unassigned cells and cells reserved for the use of the
Physical Layer. Unassigned cells are identified by an all zero VPI/VCI value and
CLP=0. They are filtered without notification. Physical layer cells are identified by an
all zero VPI/VCI value and CLP=1. They are filtered with a resulting maskable
interrupt indication and a Physical Layer cell count increment. By default, the cell
coding is assumed to be for a Network-Network Interface (NNI); therefore the VPI is
taken to be twelve bits. If one of the PHY links is a User-Network Interface (UNI) and
the GFC field is non-zero, the cell will not be filtered by the Input Cell Interface, but
will be discarded by the VC Identification circuit. As an option, all cells can be
interpreted as UNI cells.
______________________________________________________________________________________________
30
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
ep
tem
be
r,
20
02
10
:21
:53
The RCMP-800 is a bus master and services the PHY devices in one of two ways:
direct status arbitration or address line polling. For direct status arbitration, the
RCMP-800 monitors cell available signals (ICA[4:1]) from to up four physical (PHY)
layer devices and generates write enables (WRENB[4:1]) in response. For address
line polling, ICA[1] and IWRENB[1] are shared between up to 32 PHY devices and
signals IADDR[4:0] and IAVALID are used to address the latter individually. The
RCMP-800 performs round-robin polling of the PHY devices to determine which have
available cells. The RCMP-800 will read an entire cell from one PHY device before
accessing the next PHY device. No fixed cell slots exist, but instead the RCMP-800
maximizes throughput by servicing a PHY device as soon as the bus is free and PHY
device's cell available signal is asserted.
ay
,1
9S
All input FIFO signals, ISOC, IWRENB[4:1], ICA[4:1], IADDR[4:0], IAVALID,
IPRTY[1:0] and IDAT[15:0] are either sampled or updated on the rising edge of the
IFCLK clock input.
rsd
VC Identification
ef
uo
fo
liv
ett
io
nT
hu
The RCMP-800 makes use of a flexible approach to identify incoming cells and to
determine which record in the VC Table they are associated with. The RCMP-800 is
able to identify each cell's VC by searching the VC Search Table (see Table 1) using
selected portions of the cell header, prepend, postpend along with the cell's PHY
address. To do this, the RCMP-800 creates an internal Routing Word which is the
concatenation of the cell header, cell prepend and cell postpend. The RCMP-800 is
programmed to select portions of the Routing Word plus the PHY address to create a
VC Search Key . The VC Search key, therefore, consists of portions of the cell's
header, prepend, postpend and SCI-PHY address. See Figure 3.
Do
wn
loa
de
db
yV
inv
Figure 3 is not intended to imply any restrictions on the positioning of Field A and
Field B. These fields may occur any where within the appended octets or the ATM
header. The Primary Key and Secondary Key may also intersect.
______________________________________________________________________________________________
31
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:53
Fig. 3 VC Search Key Composition
Cell Postpend
Cell Header
m
S
S A- L A
S -L
B B
B
47 (NNI) 20
43 (UNI)
HEC UDF
0
hu
rsd
ay
length <= 128 bits
,1
9S
SA
VPI/VCI
Field B
ep
Field A
tem
be
r,
20
Cell Prepend
02
10
:21
Routing Word
Field B VPI/VCI
ett
Field A
liv
PHY
ID
io
nT
VC Search Key
Secondary Key
uo
fo
Primary Key
Do
wn
loa
de
db
yV
inv
ef
The RCMP-800 divides the VC Search Key into two search keys - the Primary
Search Key and the Secondary Search Key. The Primary Key is 0 to 16 bits long. It
is constructed from two fields - the PHY ID and Field A. The PHY ID field and Field
A can be programmed to be 0-5 bits and 0-16 bits long, respectively. The PHY ID is
the SCI-PHY address and must, therefore, include sufficient bits to encode all the
PHYs at the PHY Layer interface of the RCMP-800. Field A starts at location S A of
the Routing Word and has length L A. The number of bits in Field A plus the number
in the PHY ID field must be less than or equal to 16.
The Secondary Search Key is 39 bits long and is composed of two fields. The first
field, Field B, is 0 to 11 bits long and may start anywhere in the routing word. Field B
parameters include starting position S B, and length LB. The second field is the 28 bit
VCI/VPI. This field is always taken from the cell's header.
Field B and the VPI/VCI field are positioned "right justified" within the routing word.
______________________________________________________________________________________________
32
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:53
Fig. 4 Parameters of Primary Key and Secondary Key
10
:21
Primary Key
02
Field A
LA
0-16 bits
tem
be
LP
0-5 bits
r,
20
PHY ID
9S
ep
L P + L A <= 16 bits
Field B
VPI / VCI
nT
hu
Unused
rsd
ay
,1
Secondary Key
io
LB
0-11 bits
28 bits
LB+
28 + Unused = 39 bits
uo
fo
liv
ett
0-11 bits
yV
inv
ef
The user can program the RCMP-800 with the length and position parameters of
fields A and B. Refer to the descriptions for registers 0x28 and 0x29. N.B. Lp =
binary length of the PHYID field, as given by the coding of the PHY[2:0] register bits.
Do
wn
loa
de
db
Figure 5 provides a representation of how the RCMP-800 creates the Primary and
Secondary search keys. Field location and length registers are used to select Field A
and Field B from the routing word. Field A and the PHYID are concatenated to form
the Primary Search Key. Field B and the VPI/VCI field are concatenated to form the
secondary search key.
______________________________________________________________________________________________
33
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:53
Fig. 5 Construction of Search Keys
10
:21
CONFIGURATION
REGISTERS
Field B
Location S B ,L B
Registers
20
tem
be
r,
Field A Size
& Location
Field A
Location S A ,L A
Registers
02
Field B Size & Location
nT
PHY ID
I
/VP
VCI
Field B
ROUTING
WORD
hu
rsdField A
ay
,1
9S
ep
VPI/VCI
SECONDARY
SEARCH KEY
liv
ett
io
PRIMARY
SEARCH KEY
Do
wn
loa
de
db
yV
inv
ef
uo
fo
Once the search keys are assembled, the Primary Search Key is first used to
address an external direct look-up table (Primary Table). This table occupies 2n
memory locations where n = LP + LA, i.e. the length of the Primary Search Key. The
result of this direct look up is the address of a root node of a search tree. From this
root node, the Secondary Search Key is used by a patented search algorithm to find
the cell's VC Table address (held in external SRAM.) The RCMP-800 requires this
table address for cell processing. Table 1 provides a description of the VC Table. If
the search process does not lead to the successful identification of the cell concerned
(contents of the VC table address returned do not match the Secondary Search Key
contents), the cell is discarded as invalid. Optionally, the cell is routed to the
microprocessor cell interface for header error logging.
The length of time required to perform the VC search is variable. Since the Primary
Search Key is used in a direct look up, only one cycle is required to process the
Primary Key. The Secondary Search Key processing time is highly dependent on the
key's contents, but the maximum number of processing cycles required is equal to
the number of bits in the Secondary Search Key which must the examined to make a
unique identification. Some VPI and VCI bits may always be zero; therefore, they
need not be used in the search. In some instances, the Primary Search Key may
______________________________________________________________________________________________
34
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
02
10
:21
:53
overlap the Secondary Search Key; therefore, the intersecting bits are only required
for the confirmation of a search and will not be used as decision points by the binary
search. If the number of bits used by the binary search is no greater than 18, a
sustained rate of 1.42x106 cell/s is guaranteed. The general expression for
guaranteed throughput is
tem
be
r,
20
1
Throughput = (17+ max.binary tree depth)(SYSCLK
period) cell / s
Note, however, if the binary tree depth is is less than 10, the throughput becomes:
9S
ep
1
Throughput = (cell word length)(SYSCLK
period) cell / s
,1
where the cell word length is the number of 16-bit words in the cell.
fo
liv
ett
io
nT
hu
rsd
ay
The first two words of each VC Table Record are reserved for the primary table and
the search table. The third word of the VC Table Record contains the Secondary
Search Key and an "NNI" bit in the most significant bit position. This word is used to
confirm whether the incoming cell belongs to a provisioned virtual connection. Any
unused bits within this word must be set to zero. The NNI bit identifies if the VC
belongs to a Network-Network Interface. If the NNI bit is set to zero, the connection
is part of a UNI which means that the four MSBs of the VPI are excluded from the
secondary key verification. If the VCI field in the VC Table is all zeros, this signifies
the connection is a VPC and that the VCI field is to be ignored.
ef
uo
Search Table Data Structure
Do
wn
loa
de
db
yV
inv
The Primary and Secondary Search Tables reside in external SRAM. The Primary
Search Table is located in the least significant 16 bits of RAM locations with
SA[19:16]=0001 and requires 2(LP + LA) words of memory. The Secondary Search
Table resides in RAM locations with SA[19:16]=0000 and its size is bounded by the
number of virtual connections supported.
Figure 6 illustrates the relationship between the Primary Search Table, Secondary
Search Table and the VC Table.
______________________________________________________________________________________________
35
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:53
Fig. 6 Data Structures
:21
Primary Key
...
P
+L
A
)
-1
VC
T ABL E
E nt r y
VC
T ABL E
E nt r y
VC
T ABL E
E nt r y
VC
T ABL E
E nt r y
VC
T ABL E
E nt r y
VC
T ABL E
E nt r y
VC
T ABL E
E nt r y
VC
T ABL E
E nt r y
9S
ep
VC
T ABL E
E nt r y
r,
VC
T ABL E
E nt r y
tem
be
VC
T ABL E
E nt r y
Secondary
Search Table
20
02
Primary
Search Table
(L
2
10
0
rsd
ay
,1
The following gives the immutable coding rules for the search data structures. The
coding supports numerous possible algorithms, but the Operations Section presents
an algorithm which is optimized for most applications.
hu
Primary Search Table
ett
io
nT
The Primary Search Table contains an array of pointers which point to the roots of
binary trees. The table is directly indexed by the contents of the Primary Search Key,
as defined above.
db
yV
inv
ef
uo
fo
liv
The entire Primary Search Table must be initialized to all zeros. A table value of zero
represents a null pointer; therefore, the initial state means no provisioned
connections are defined. If a connection is added which results in a new binary
search tree (i.e. It is the only connection associated with a particular Primary Search
Key.), the appropriate Primary Search Table location must point to the newly created
binary search tree root. If the last connection associated with a particular Primary
Search Key is taken down, the associated Primary Search Table location must be set
to all zeros.
Do
wn
loa
de
Secondary Search Table
The Secondary Search Table consists of a set of binary search trees. Each tree's
root is pointed to by an entry in the Primary Search Tree. Each node in the tree is
represented by a 40 bit record contained at SA[19:16]=0000, which is encoded as
follows:
MSB
SD[39:34]
Select
SD[33]
Left
Leaf
SD[32:17]
Left Branch
SD[16]
Right
Leaf
LSB
SD[15:0]
Right Branch
______________________________________________________________________________________________
36
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
The index of the Secondary Search Key bit upon which the
branching decision is based. An index of zero represents the
LSB. If the selected bit is a logic one, the "Left Leaf" and
"Left Branch" fields are subsequently used. Likewise, if the
selected bit is a logic zero, the "Right Leaf" and "Right
Branch" are subsequently used. Typically, the Select value
decreases monotonically with the depth of the tree, but other
search sequences are supported by the flexibility of this bit.
tem
be
r,
20
02
10
:21
:53
Select
io
nT
hu
rsd
ay
,1
9S
ep
If a VC belongs to a multicast, the select field is set to an all
ones pattern, except the last in the linked list. For a multicast
entry, the Left_Branch gives the VC table address of the
multicast VC (the Left Leaf is always '1'). The Right_Branch
points to the Search Table address of the next VC in the
multicast. The VC search table therefore forms a linked list
and may multicast an arbitrary number of cells. The linked list
is terminated by setting the Select field to value that is not all
ones. A non all ones value in the Select field instructs the
search engine that the Left_Branch field provides the final VC
Search Table Address of the multicast set.
This flag indicates if this node is a leaf. If "Left Leaf" is a logic
one, the left branch is a leaf and the binary search terminates
if the decision bit is a logic one. If "Left Leaf" is a logic zero,
"Left Branch" value points to another node in the binary tree.
uo
fo
liv
ett
Left Leaf
Do
wn
loa
de
Left Branch
db
yV
inv
ef
If the VC pointed to by the Left Branch is the first VC in a
multicast set, the Left_Leaf must be set to a logic 1. For the
remaining VCs in the multicast set, the Left Leaf value is
arbitrary, but it is recommended to be set to a logic 1 for
future compatibility.
The pointer to the node accessed if the decision bit is a logic
one. If "Left Leaf" is a logic one, "Left Branch" contains the
SA[15:0] address identifying the VC Table Record for the
candidate connection. If "Left Leaf" is a logic zero, "Left
Branch" contains the SA[15:0] value pointing to another
Secondary Search Table entry.
If the Search Table entry is part of a multicast linked list, the
Left Branch is the VC Table address of one VC in the
multicast.
______________________________________________________________________________________________
37
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
This flag indicates if this node is a leaf. If "Right Leaf" is a
logic one, the Right branch is a leaf and the binary search
terminates if the decision bit is a logic zero. If "Right Leaf" is
a logic zero, "Right Branch" value points to another node in
the binary tree.
02
10
:21
:53
Right Leaf
tem
be
r,
20
If the VC pointed to by the Left Branch belongs to a multicast
set, the Right_Leaf value is arbitrary, but it is recommended
to be set to a logic 0 for future compatibility.
The pointer to the node accessed if the decision bit is a logic
zero. If "Right Leaf" is a logic one, "Right Branch" contains
the SA[15:0] address identifying the VC Table Record for the
candidate connection. If "Right Leaf" is a logic zero, "Right
Branch" contains the SA[15:0] value pointing to another
Secondary Search Table entry.
rsd
ay
,1
9S
ep
Right Branch
ett
io
nT
hu
If the Search Table entry is part of a multicast linked list
(except the last element of the list), the Right Branch is the
Search Table address of the next element in the list. If the
Search Table entry is the last element in the linked list, this
field is arbitrary.
fo
liv
The above encoding defines the binary search tree recursively.
ef
A binary tree with only one connection must have both the Left and Right
Branches pointing to the solitary VC Table Record. Both Leaf flags must be a
logic one.
yV
inv
1.)
uo
The following special cases must be respected:
Do
wn
loa
de
db
2a.) If the Primary Search Table is not used (i.e. LP = LA = 0), the root of the single
resulting binary search tree must be located at the Secondary Search Table
entry at SA[15:0]=0x0000.
2b.) If the Primary Search Table is in use, no root node shall use location
SA[15:0]=0x0000, although this location may be used for nodes at least one
level down. A value of 0x0000 in the Primary Search Table represents a null
pointer.
______________________________________________________________________________________________
38
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:53
Cell Processing
02
10
:21
After a VPI/VCI search has been completed for a cell, the resulting actions are
dependent upon the cell contents and the VC Table Record. Particular features such
as policing and OAM cell processing can be disabled on a global basis.
9S
ep
tem
be
r,
20
The VPI/VCI search results in a SA[15:0] value which points to a VC Table Record.
Table 1 illustrates the fields for each VC Table Record. A description of each field is
given below. If fewer than 32768 connections are supported, the most significant bits
of SA[15:0] and the associated memory may not be required. The individual fields of
the VC Table Record are accessed by the SA[19:16] outputs. If particular features
are disabled, the associated fields are unused and no memory need be provided for
them.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
When a new VC is provisioned, the microprocessor must initialize the contents of the
VC Table Record. Refer to the External RAM Address (MSB) and Access Control
register description for details on access control. Once provisioned, the
microprocessor can retrieve the contents of the VC Table Record.
______________________________________________________________________________________________
39
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
(6)
:21
OAM Config
(9)
(8)
(8)
ReservedCOCUPReserved
(2)
BWD Routing Tag
(5)
TAT#1 (28)
TAT#2 (28)
I#1 (20)
Action#1
(2)
Action#2
(2)
non-compliant
cell count #2 (16)
non-compliant
cell count #1 (16)
,1
(1)
UDF
liv
ett
io
nT
hu
rsd
ay
Output Header (40)
Pre/Post pend (40)
Pre/Post pend (40)
Unused (8)
CLP=0 cell count (32)
Unused (8)
CLP=1 cell count (32)
PM Config(8)
current cell count (16)
BIP16 (16)
Backward Reporting Counts
SECB(8), Lost Cells (12), Misinserted Cells (8), BIPV (12)
Forward Monitoring Counts
SECB(8), Lost Cells (12), Misinserted Cells (8), BIPV (12)
Do
wn
loa
de
db
yV
inv
ef
uo
fo
1111
Extended Status
L#1 (12)
L#2 (12)
I#2 (20)
(1)
1000
1001
1010
1011
1100
1101
1110
Config
r,
Status
20
02
10
Reserved for Search Table
MSN (8)
TUC (16)
Reserved for Search Table (16)
Search
VPI (12)
VCI (16)
NNI (1)
FieldB (11)
tem
be
(4)
0100
0101
0110
0111
LSB(0)
ep
0011
MSB(39)
9S
SA[19:16]
0000
0001
0010
:53
Table 1 VC Table Record
______________________________________________________________________________________________
40
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:53
Configuration and Status
10
:21
Configuration and Status fields are available at locations SA[19:16]=0011 and 0111.
Definition
The connection type. If this bit is 1, the VC is an ABR
connection. Otherwise, the VC is a VBR/CBR
connection. This bit affects the choice of Cell Rate
Policing Configuration Registers. When CONTYP is 1
(an ABR connection), the ABR Cell Rate Policing
Configuration registers are used by the policing
processor, when CONTYP is 0, the VBR/CBR Cell
Rate Policing registers are used by the policing
processor.
Indicates that this VC should be output to the
Microprocessor Cell Interface only (not to the Output
Cell Interface). Otherwise, the VC is presented on
Output Cell Interface (provided it is not a cell which is
filtered by the Routing Configuration Register).
Identifies the VC as an AAL Type 5 Connection. This
enables AAL5 packet discard/tagging. Note, if AAL5
policing is used, then only one GCRA can be used
(either GCRA1 or GCRA2). The GCRA which is not
being used must have its increment field set to
0x00000.
Identifies the VC as an active connection. If this bit is
set to 1, the VC is an active connection. Otherwise the
VC is an inactive connection. The bit is checked
during one-second servicing to determine if the
connection is still active. It is the responsibility of the
microprocessor to set and clear this bit during
activation and deactivation, respectively, of a
connection.
If this bit is set, the CLP=0 and CLP=1 cell counts
include user information cells.
If this bit is set, the CLP=0 and CLP=1 cell counts
include OAM and RM cells.
20
Name
CONTYP
3
AAL5
2
Active
rsd
DROPUP
1
0
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
4
ay
,1
9S
ep
tem
be
r,
Bit
5
02
The Configuration field allows each connection to be independently provisioned:
Count User
Count OAM
______________________________________________________________________________________________
41
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
AIS
2
RDI
1
CC_alarm
0
POLICE
Definition
This bit becomes a logic 1 upon the receipt of a single
AIS cell. The alarm status is cleared upon the receipt
of a single user cell or continuity check cell or if no AIS
cell has been received within the last 3.5 +/- 0.5 sec
(default) or 2.5 +/- 0.5 sec. The threshold is set by the
AISRDIThresh bit of the Performance Monitoring
Configuration 1 register (0x19).
This bit becomes a logic 1 upon the receipt of a single
RDI cell. The bit is cleared if no RDI cell has been
received within the 3.5 +/- 0.5 sec (default) or 2.5 +/0.5 sec. . The threshold is set by the AISRDIThresh bit
of the Performance Monitoring Configuration 1 register
(0x19).
This bit is a logic 1 if no user, AIS or continuity check
cells have been received in the latest 5.5 +/- 0.5 sec
(default) or 3.5 +/- 0.5 sec seconds. The threshold is
set by the CCThresh bit of the Performance Monitoring
Configuration 1 register (0x19).
This bit is a logic 1 if at least one cell has violated the
traffic contract. This bit is not cleared upon a read; it
must be cleared explicitly by writing to its location.
10
Name
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
tem
be
r,
20
02
Bit
3
:21
:53
The Status field provides a single location for the fast determination of the connection
state:
db
yV
inv
ef
The Extended Status and Reserved fields of the VC Table word at SA[19:16]=0111
contain connection state information. The Reserved field should be initialized to all
zeros and the Extended Status field should be set to 0x050 during connection
provisioning.
Do
wn
loa
de
Header Translation
Any appended octets (used by non-standard PHY devices or in special applications)
in incoming cells are removed after they have been used for VC identification. Once
VC identification has been made, new octets contained in the VC table can be
appended to each cell.
The new appended octets are contained in locations identified by SA[19:16]=0011,
1001 and 1010. Substitution of appended octets can be disabled by clearing the
GPREPO bit of the Cell Processor Configuration register. If the 16 bit bus format is
configured on the Output Cell Interface, the eight bit UDF field in the SA[19:16]=0011
______________________________________________________________________________________________
42
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
20
02
10
:21
:53
word is placed in the user defined octet following the HEC octet location. If the 8 bit
bus format is configured on the Output Cell Interface, the eight bit UDF field in the
SA[19:16]=0011 word is not used. All other appended octets are sequenced in the
extended cell format SCI-PHY data structure starting with the most significant octet of
SA[19:16]=1001. Physical memory need not be provided for all octets if the SCI-PHY
cell is less than 63 octets.
ep
tem
be
r,
Note that if the RCMP is placed in 8-bit output mode, with the Output Cell Interface
configured for an even length output cell (i.e. an odd number of appended octets), the
RCMP will sequence the appended octets starting with the second most significant
byte.
liv
ett
io
nT
hu
rsd
ay
,1
9S
The header contents of each cell can be altered. The location accessed by
SA[19:16]=1000 contains the new header. The forty bit field contains the entire
header, although not all bits are required for all connections. The VPI portion, the
VCI portion, or both can be replaced with new values recovered from the VC table
once VC identification has been made. Substitution of VPI/VCI contents can be
disabled by clearing the GVPIVCI bit of the Cell Processor Configuration register.
The PTI field is not modified by the translation process. If the connection is a Virtual
Path (i.e. the VCI value in the search key is coded as all zeros), the VCI field is
passed through transparently. As a globally configurable option, the GFC field in UNI
cells can be left unmodified; otherwise, it is replaced by the four most significant bits
of the output header word.
uo
fo
Cell Routing
Do
wn
loa
de
db
yV
inv
ef
Each generated reverse flow cell which is presented by the Output Cell Interface may
have the Backward Routing tag of the VC table inserted in its header (i.e. overwrite a
byte of the header). The Backward Routing tag of the VC table is at SA[19:16] =
0011. The appended byte or header byte to be overwritten is programmable. As an
option, the VPI/VCI combination may equal the incoming VPI/VCI instead of the
translated value.
The destination of each OAM cell depends on the type of OAM cell and whether the
RCMP-800 is the end-point for that particular OAM flow. If the RCMP-800 is not an
end point, the OAM cell is routed to the same destination as the user cells. If the
RCMP-800 is an end point, the default configuration terminates and processes all
OAM cells except Activate/Deactivate and Loopback cells, which are routed to either
the Output Cell Interface or the Microprocessor Cell Interface.
______________________________________________________________________________________________
43
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:53
Cell Rate Policing
ep
tem
be
r,
20
02
10
:21
The RCMP-800 supports two instances of the Generic Cell Rate Algorithm (GCRA)
for each connection. The rate policing operation is performed according to the Virtual
Scheduling Algorithm presented in Annex 1 of ITU-T Recommendation I.371 and the
ATM Forum UNI 3.0. To allow full flexibility, the GCRA1 and GCRA2 bit vectors in
the ABR Cell Rate Policing Configuration (0x1A) and VBR/CBR Rate Policing
Configuration (0x1B) registers allow each instance to police many combination of
cells: user cells, OAM cells, Resource Management cells (for ABR connections only),
high priority cells or low priority cells. The connection type (ABR or VBR/CBR) is
determined on a per-VC basis as programmed in the VC table.
rsd
τ
∆t
hu
L=
∆t = time quantum (s)
nT
1
PCR(∆t)
where
io
I=
ay
,1
9S
The Limit (L#1 and L#2) and Increment (I#1 and I#2) fields in the VC Table must be
initialized before policing is enabled. These fields are related to the traffic contract
parameters as follows:
liv
ett
PCR = Peak Cell Rate (cell/s)
τ = Cell Delay Variation (s)
yV
ef
SCR = Substained Cell Rate (cell/s)
MBS = Max. Burst Size at the Peak Cell Rate (cells)
BT = Burst Tolerance (s)
inv
where
1
1
)
− PCR
BT ( MBS − 1)( SCR
=
∆t
∆t
Do
wn
loa
de
L=
1
SCR(∆t )
db
I=
uo
fo
For a Sustained Cell Rate (SCR) conformance definition, the parameters relate as
follows:
The time quantum (∆t) can be programmed to be an 1, 2, 4 or 8 multiple of the
SYSCLK period. With a 50 MHz clock, ∆t is 20, 40, 80 or 160 ns.
______________________________________________________________________________________________
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PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
MSB
4
LSB
0
r,
m
tem
be
e
20
0 6
02
10
:21
:53
In order to compensate for the potentially large CDV and Burst Tolerance limits
anticipated in ATM networks, the Limit fields, L#1 and L#2, are encoded as
floating-point values, while all other policing parameters are fixed-point values. The
Limit fields are encoded as follows:
ep
where e is the 5-bit exponent and m is the 7-bit mantissa. The value of the Limit
field is computed as:
,1
9S
L = m • 2e
hu
rsd
ay
It is important to note that since the Limit field is a floating-point number, its maximum
value exceeds the maximum TAT (268435455) value; therefore, L should not exceed
this value. If the encoded value of L is greater than TATmax, then L shall be taken to
be TATmax, i.e.
io
nT
L ≤ TATmax
liv
ett
To maximize resolution, the limit field should be encoded as a normalized
floating-point number (i.e. the mantissa is MSB justified).
yV
1
Imax∆t
db
PCRmin =
inv
ef
uo
fo
The value of ∆t and the range of I and L determine the lowest PCR that can be
policed, the PCR granularity supported at the highest expected PCR and the largest
CDV expected:
Do
wn
loa
de
granularity (as a fraction of PCR) = PCR∆t
τ max = L max ∆t
With a 20 bit increment field, Imax is 1048575; therefore, the smallest peak rate (or
sustainable rate) supported is
47.7 cells / s : ∆ t = 20ns
23.8 cells / s : ∆ t = 40ns
=
PCR min 
11.9 cells / s : ∆ t = 80ns

5.96 cells / s : ∆t = 160ns
______________________________________________________________________________________________
45
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
:21
As described previously, the limit field, L, is a 12-bit floating-point field, with
Lmax = 268435455 (which is equal to TATmax). Therefore
tem
be
r,
20
02
5.36s : ∆t = 20ns
10.7s : ∆t = 40ns
CDV max = 
21. 4s : ∆t = 80ns

42.8s : ∆t = 160ns
,1
9S
ep
With a maximum expected cell rate of 353,207 cell/s (which is the bandwidth of an
STS-3c/STM-1) and a time quantum of 20ns, the granularity of the policed rate is
0.71% of the peak rate.
rsd
ay
The action taken on a non-conforming cell is programmed on a per VC basis by the
"Action[1:0]" field:
Definition
Set the POLI status bit but take
no other action other than to
increment the appropriate noncompliant cell count..
Reduce the priority of high
priority cells.
Reduce the priority of high
priority cells and discard low
priority cells.
Discard all non-conforming cells.
ett
io
nT
hu
Action[1:0]
00
fo
liv
01
inv
ef
uo
10
yV
11
Do
wn
loa
de
db
Action1[1:0] represents the action to be taken by GCRA1 on non-conforming cells,
and Action2[1:0] represents the action to be taken by GCRA2 on non-conforming
cells.
Policing can be effectively disabled for a connection if the increment fields (I#1 and
I#2) are set to all zeros.
In general, if a GCRA fails, its TAT parameter is not updated. However, a coupling
can be introduced between the update actions of GCRA1 and GCRA2. To allow for
this contingency, the COCUP (COnditional Conformance UPdate) bit of the VC table
can be set appropriately. If COCUP = 0, the update of GCRA1 and GCRA2 TAT
______________________________________________________________________________________________
46
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
02
10
:21
:53
parameters are completely independent. That is, the conformance or nonconformance of one GCRA has no effect on the other. If COCUP = 1, however, the
GCRA1 TAT parameter update is dependent on the conformance to GCRA2. Thus,
if a cell is compliant to GCRA1, the TAT parameter for GCRA1 shall be updated if
and only if the cell is also compliant to GCRA2.
tem
be
r,
20
In addition, if COCUP=1, the GCRA2 TAT parameter update is dependent on the
conformance to GCRA1. That is, if a cell is to be discarded as a result of nonconformance to GCRA1, the GCRA2 TAT parameter will not be updated.
9S
ep
Two non-compliant cell counts are maintained based upon one of the following
programmable definitions, as determined by the state of the NCOMP[1:0] register bits
in the VBR/CBR Cell Rate Policing Configuration register:
Non-compliant CLP=0 cells and non-compliant CLP=1 cells.
2.)
Dropped CLP=0 cells and dropped CLP=1 cells.
3.)
Cells which are non-compliant with GCRA#1, and cells compliant with
GCRA#1 which are non-compliant with GCRA#2.
4.)
Cells which are non-compliant with GCRA#1, and cells which are noncompliant with GCRA#2
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
1.)
______________________________________________________________________________________________
47
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:53
AAL5 Packet Tagging and Dropping
20
02
10
:21
An AAL5 packet can be up to 1366 cells long. If a cell is dropped early in a packet
due to policing or congestion, then the remaining cells of the packet represent wasted
bandwidth. Optionally, all remaining cells of a packet can be dropped or tagged once
a single cell has been dropped or tagged.
rsd
ay
,1
9S
ep
tem
be
r,
On a per-VC basis, the RCMP-800 has a configuration bit indicating the AAL as Type
5 and two status bits that indicate a cell within the packet has violated either or both
of the GCRAs. For each cell received on an AAL5 connection, if either of the status
flags are set, the actions dictated by the appropriate ACTION field will be taken on
the remainder of the packet. The policing parameters for that GCRA will not be
updated. If an EOM (SDU_type=1) cell is received, the cell is passed on and the
status bits are cleared. Note, if AAL5 packet policing is to be used, only one
GCRA may police the cell stream. The other GCRA must have its increment
field set to 0x00000.
nT
hu
OAM and Resource Management (RM) cells are passed transparently by the packet
discard mechanism.
ett
io
The CLP=0, CLP=1 and non-compliant cell counts are updated for all cells of an
AAL5 packet.
fo
liv
Cell Counting
ef
uo
The RCMP-800 maintains counts on a per VC basis and over the aggregate cell
stream.
db
number of low priority cells
number of high priority cells
non-compliant cell counts (user programmable)
Do
wn
loa
de
•
•
•
yV
inv
The following parameters are stored on a per VC basis:
______________________________________________________________________________________________
48
PM7322 RCMP-800
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PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
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:21
:53
The number of cells discarded by the policing function and the number of cell
reduced from high to low priority can be derived from the above counts , the state of
the Action1[1:0] and Action2[1:0] fields, and the state of the NCOMP[1:0] register
bits.
tem
be
r,
20
02
In order to maintain accurate non-compliant cell counts in the VC table, the RCMP800 asserts a maskable interrupt whenever the most significant bit is set for either of
the non-compliant cell counts. This allows an external microprocessor to read the
counts to prevent saturation.
9S
ep
The low and high priority cell counts represent the state of the cells before policing.
The non-compliant cell counts can be used to derive the cell counts after policing.
rsd
ay
,1
To provide the ability to provision scheduled measurements and special studies, each
VC can be programmed to count either user information cells, OAM (including
Resource Management) cells or both.
liv
ett
io
number of lost cells
number of misinserted cells
number of BIP-16 errors
number of Severely Errored Cell Blocks (SECB)
fo
•
•
•
•
nT
hu
If performance monitoring is activated, the following forward monitoring and backward
reporting parameters are stored on a per-VC basis:
ef
uo
Each of the per VC values is cleared upon a microprocessor read access to its
location.
•
•
•
db
number of cells received at the Input Cell Interface
number of cells transferred through the Output Cell Interface
number of valid OAM cells received
number of OAM cells with an incorrect CRC-10, undefined OAM Type or
undefined Function Type
number of cells with errored headers. These include cells with
unassigned/invalid VPI/VCIs or invalid PTI values
number of CLP=1 cells dropped due to congestion
number of physical layer cells received
Do
wn
loa
de
•
•
•
•
yV
inv
The following parameters cover the aggregate cell stream:
Events are accumulated over consecutive intervals as defined by the period of the
microprocessor initiated data latching. The RCMP-800 maintains current counts and
holding registers. A latching event transfers the counter values into holding registers
______________________________________________________________________________________________
49
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
:21
:53
and resets the counters to begin accumulating events for the next interval. The
counters are reset in such a manner that events occurring during the reset are not
missed. The holding registers can be read via the microprocessor interface.
02
All counts saturate at all ones and will not roll over.
20
Operations, Administration and Maintenance (OAM) Cell Servicing
9S
ep
tem
be
r,
The RCMP-800 is capable of terminating and monitoring F4 and F5 OAM flows.
Complete processing of Fault Management, Performance Management (PM) and
Continuity Check cells is provided. Activate/Deactivate and Loopback cells are
passed to the Microprocessor Cell Buffer or the Output Cell Interface for external
processing.
ay
,1
For the case of OAM processing, the following applies:
nT
hu
rsd
1. If the RCMP-800 is configured as a sink of PM cells, then the BIP-16, current
cell count, MSN, TUC, forward statistics and backward statistics are updated
independent of the outcome of cell policing.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
2. If the RCMP-800 is configured as a source of PM cells, then the BIP-16,
current cell count, MSN and TUC are updated dependent of the outcome of
cell policing. That is, those fields are updated if and only if the cells are not
discarded by the RCMP-800.
______________________________________________________________________________________________
50
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
6
BACKRPT
5
Send_AIS
4
Send_RDI
3
End_pt
2
Seg_end_pt
1
PM_activate
0
CC_activate
Action if a logic 1
Setting this bit enables the sending of RDI cells at one
second intervals upon the declaration of a Continuity
Check alarm at a termination point (i.e. the CC_alarm
bit is set).
Enables the generation of backward report cells. A
backward report cell is output for each forward
monitoring cell received at an OAM flow end-point if
the SRCPM bit is a logic 0.
Sends an AIS cell once per second. The cells
genrated are encoded as End-to-End AIS cells.
Sends an RDI cell once per second. The cells
genrated are encoded as End-to-End RDI cells.
Defines the RCMP-800 as an End-to-End termination
point. For VPCs, all cells with VCI=4 are dropped and
processed. For VCCs, all cells with PT=101 are
dropped and processed.
Defines the RCMP-800 as a Segment termination
point. For VPCs, all cells with VCI=3 are dropped and
processed. For VCCs, all cells with PT=100 are
dropped and processed.
Enables performance management. PM cells are
either sourced or monitored.
Enables Continuity Checking. If no user or AIS cell is
received over a 1.5 +/- 0.5 or 2.5 +/- 0.5 (default,
controlled by the AISRDIThresh bit in register 0x19)
second window, a Continuity Check OAM cell is
generated. The CC cell generation interval set by the
CCThresh bit of the Performance Monitoring
Configuration 1 register (0x19).
10
Name
CC_RDI
Do
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loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
tem
be
r,
20
02
Bit
7
:21
:53
The contents of the OAM Configuration field at SA[19:16]=0011 determine the
RCMP-800's behavior with respect to a particular connection:
Upon receipt of an OAM cell, the CRC-10 is checked. If the check sum is incorrect,
the OAM cell is not processed and the global errored OAM cell count is incremented.
Otherwise, further processing is dependent upon the contents of the OAM Cell Type
field.
If a connection is not provisioned as an end point, all incoming OAM cells are passed
to the Output Cell Interface (subject to policing) regardless of whether the OAM Type
or the Function Type fields have defined values. As an option, OAM cells may be
______________________________________________________________________________________________
51
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
tem
be
r,
20
02
10
:21
:53
discarded at non flow end-points if the CRC-10 is incorrect. At flow end-points all
OAM cells are terminated, except Activate/Deactivate and Loopback cells whose
handling is specified by the Routing Configuration register. If the UNDEFtoUP bit of
the Routing Configuration register is a logic 1, all undefined OAM cells are routed to
the Microprocessor Cell Interface for further processing or error logging. If the
CNTUNDEF bit in the CRAM Configuration register is a logic 1, the Errored OAM Cell
Count register is incremented for each cell with an undefined OAM Type or Function
Type value.
The PM Configuration field (SA[19:16] = 1101) provides various PM related functions:
SECBMISINS
5
SECBBIPV
ep
6
Definition
This status bit indicates that a forward LOST cell count
exceeded the MLOST[7:0] threshold and resulted in
the declaration of a SECB. This bit is cleared upon a
microprocessor read of location SA[19:16] = 1101.
This status bit indicates that a forward MISINSERTED
cell count exceeded the MMISINS[7:0] threshold and
resulted in the declaration of a SECB. This bit is
cleared upon a microprocessor read of location
SA[19:16] = 1101.
This status bit indicates that a forward BIPV cell count
exceeded the MERROR[4:0] threshold and resulted in
the declaration of a SECB. This bit is cleared upon a
microprocessor read of location SA[19:16] = 1101.
If the RCMP-800 is configured as a source of PM cells
(SRCPM = 1, PM_activate = 1, and the RCMP-800 is
configured as a flow-end-point), the BLKSIZE[1:0] bits
select the nominal number of user cells per
performance monitoring block.
9S
Name
SECBLOST
BLKSIZE[1:0]
Do
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4:3
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
Bit
7
BLKSIZE[1:0]
00
01
10
11
User cells per block
1024
128
256
512
______________________________________________________________________________________________
52
PM7322 RCMP-800
STANDARD PRODUCT
1
SRCPM
0
PM0
The PM_TYP bit determines whether end-to-end PM
cells or segment PM cells are relevant to the
connection. If PM_TYP is a logic 1, end-to-end PM
cells will be generated (if SRCPM is a 1) or they will be
analyzed (if SRCPM is a 0). If PM_TYP is a logic 0,
segment PM cells will be sourced or analyzed.
This bit provisions the RCMP-800 as a source of
forward monitoring cells for the connection. Setting the
SRCPM bit and PM_activate bit to logic 1 results in
the presention of a forward monitoring cell on the
Output Cell Interface at an interval selected by the
BLKSIZE[1:0] bits. If the SRCPM bit is 0, no
monitoring cells are generated, which frees up
resources so that statistics can be collected for
incoming monitoring cells.
The PM0 bit of the VC table must be set to '1' initially.
This bit is cleared upon receiving the first PM cell. This
clears the current cell count and BIP16. The PM0 bit is
used to note the arrival of the first PM cell. The PM0
bit suppresses accumulation of error counts. If this bit
is not set, errors counts will be accumulated.
:53
PM_TYP
ett
io
nT
hu
rsd
ay
,1
9S
ep
tem
be
r,
20
02
10
:21
2
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
fo
liv
Fault Management Cells
ef
uo
Fault Management cells are identified with an OAM Cell Type of 0001. Four types
are currently supported: AIS, RDI, Continuity Check and Loopback.
Do
wn
loa
de
db
yV
inv
An AIS alarm status bit is set upon the receipt of a single AIS cell (function
type=0000). The alarm status is cleared upon the receipt of a single user cell or
continuity check cell or if no AIS cell has been received within the last 3.5 +/- 0.5 sec
(default) or 2.5 +/- 0.5 sec. If the AUTORDI bit in the Cell Processor Configuration
register is set, an RDI cell is generated immediately upon the reception of the first
AIS cell at a flow end-point and once a second thereafter until the AIS state is exited.
An RDI alarm status bit is set upon the receipt of a single RDI cell (function
type=0001). The alarm status is cleared if no RDI cell has been received within the
last 3.5 +/- 0.5 sec (default) or 2.5 +/- 0.5 sec.
If the "CC_activate" bit is a logic 1 and no user cells have been received within a one
or two (default) second window, a Continuity Check cell is generated and passed to
the Output Cell Interface. Regardless of the state of the "CC_activate" bit, if no user ,
AIS or Continuity Check cells are received within a 5.5 +/- 0.5 sec (default) or 3.5 +/______________________________________________________________________________________________
53
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
02
10
:21
:53
0.5 sec window, the "CC_alarm" status bit is set. The "CC_alarm" is cleared upon
reception of a single user, AIS or Continuity Check cell. If the AUTORDI bit in the
Cell Processor Configuration register is set and the "CC_RDI" bit of the OAM
Configuration field is set, an RDI cell is presented on the Output Cell Interface once a
second while the Continuity Check alarm is declared.
ep
tem
be
r,
20
The RCMP-800 provides support for processing of Loopback cells by a
microprocessor. The LB[1:0] bits of the Cell Processor Configuration register
determine which loopback cells are copied to the Microprocessor Cell Interface: all,
none or just at OAM flow end-points. If the RCMP-800 is not an OAM flow end-point,
all received loopback cells are routed to the Output Cell Interface.
rsd
ay
,1
9S
If the Loopback Indication is non-zero and the Loopback Location ID matches this
node (coded as all '1's for flow end-points), the microprocessor should insert into the
reverse direction a copy of the loopback cell with the Loopback Indication set to '0'.
Otherwise, the microprocessor should discard the cell.
hu
Performance Management Cells
nT
Performance Management (PM) cells are identified with a OAM Cell Type of 0010.
uo
fo
liv
ett
io
If the RCMP-800 is not the flow end point, the PM cells are passed to the Output Cell
Interface and can be monitored to generate alarms or statistics. If the RCMP-800 is
provisioned as a flow end point, a received PM cell is unconditionally dropped. If the
"PM_activate" bit is a logic 0 or the SRCPM register bit is logic 1, no further actions
are taken.
Do
wn
loa
de
db
yV
inv
ef
As a flow end point, the RCMP-800 can be provisioned as source or sink of PM cells
for a specific connection, but not both. If provisioned as a source (i.e. the SRCPM
and the PM_activate VC table bits are both logic 1), the RCMP-800 shall generate a
forward PM cell nominally every 128, 256, 512 or 1024 user cells. The contents of
the cell fields are as follows:
Monitoring Sequence Number (MSN) - This field is incremented with each
transmitted PM cell.
Total User Cell Number (TUC) - This field indicates the total number of
transmitted user cells modulo 65536 before the monitoring cell.
Block Error Detection Code - This field is the even parity BIP-16 error detection
code computed over the information field of the block of user cells transmitted
after the last monitoring cell.
______________________________________________________________________________________________
54
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:53
Time Stamp - The default of all ones is inserted.
02
10
:21
Block Error Result - The generated cell is a forward monitoring cell; therefore,
this field is coded as 6AH.Lost/Misinserted Cell Count - The generated cell is
a forward monitoring cell; therefore, each byte of this field is coded as 6AH.
tem
be
r,
20
A backward reporting cell is output for each forward monitoring cell received at an
OAM flow end-point if the BACKRPT bit is a logic 1 and the SRCPM bit is a logic 0.
ep
The PM0 bit of the VC table must be set to '1' initially to suppress the accumulation of
error counts upon the arrival of the first forward Performance Management cell. This
bit is cleared upon receiving the first PM cell.
nT
hu
rsd
ay
,1
9S
If the RCMP-800 is a sink of PM cells, all received user cells result in updating of the
current cell count and BIP16 fields of the VC table. If the RCMP-800 is a source of
PM cells, only user cells which are not discarded by the UPC function result in an
updating of the current cell count and BIP16 fields of the VC table. For the purposes
of Performance Management at the F4 (VPC) level , cells with VCI values of 1, 2, 5 or
•16 are considered user cells. For the purposes of Performance Management at the
F5 (VCC) level, cells with PTI values of 000 through 011 are considered user cells.
uo
fo
liv
ett
io
If the "PM_activate" bit is a logic 1 and the RCMP-800 is not the source of monitoring
cells (i.e. the SRCPM VC table bit is logic 0), the fields of received Forward
Monitoring and Monitoring/Reporting cells are compared with the accumulated data
for the block of user cells since the latest PM cell. Receipt of a monitoring cell results
in the updating of the statistics located at SA[19:16]=1111:
Do
wn
loa
de
db
yV
inv
ef
Lost Cell Count - The Lost Cell Count is incremented by the number of lost cells
if the number of received cells in the block is less than the number that are
expected based on the contents of the TUC field. If the number of lost cells
equals or exceeds the threshold set by the MLOST[7:0] register bits, the SECB
count is incremented and the lost cell accumulation is suppressed.
Misinserted Cell Count - The Misinserted Cell Count is incremented by the
number of misinserted cells if the number of received cells in the block is more
than the number that are expected based of the contents of the TUC field. If
the number of misinserted cells equals or exceeds the threshold set by the
MMISINSERT[7:0] register bits, the SECB count is incremented and the
misinserted cell accumulation is suppressed.
______________________________________________________________________________________________
55
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
20
02
10
:21
:53
BIP-16 Violation (BIPV) Count - The BIPV count is incremented by the number of
mismatches between the locally calculated BIP-16 code and the value
encoded in the BIP-16 field. If either of the MSN or the TUC values are
incorrect, the BIPV accumulation is suppressed. If the number of BIPV errors
equals or exceeds the threshold set by the MERRORED[4:0] register bits, the
SECB count is incremented and the BIPV accumulation is suppressed.
ep
tem
be
r,
Severely Errored Cell Block (SECB) Count - This parameter is incremented if the
number of BIPVs, lost cells or misinserted cells are equal to or greater than the
threshold set by the MERRORED[4:0], MLOST[7:0] and MMISINSERT[7:0]
register bits, respectively.
rsd
ay
,1
9S
The RCMP-800 also maintains the analogous counts for the reverse flow at
SA[19:16]=1110. These counts are updated upon the reception of either a Backward
Reporting cell or a Monitoring/Reporting cell. The MERRORED[4:0], MLOST[7:0]
and MMISINSERT[7:0] register bits also set the SECB thresholds for the reverse
flow.
nT
hu
The count values contained in the SA[19:16]=1110 and 1111 locations are cleared to
zero upon a microprocessor read access.
ett
io
Activation/Deactivation Cells
uo
fo
liv
Activation/Deactivation cells are identified with a OAM Cell Type of 1000. They are
used by the management entity to implement the handshaking required to initiate or
cease performance monitoring or continuity check processes.
Do
wn
loa
de
db
yV
inv
ef
The RCMP-800 does not process these cells. If the RCMP-800 is not an end point
for an OAM cell flow, all Activation/Deactivation cells are passed to the Output Cell
Interface. If the RCMP-800 is an end point for a OAM flow, the
Activation/Deactivation cells are optionally passed to the Microprocessor Cell
Interface or the Output Cell Interface. The flow of the Activation/Deactivation cells is
controlled by the ACTDEtoUP and ACTDEtoOCIF bits of the ALCP Routing
Configuration register. This enables the management entity to process the cell, and
respond by modifying the "PM_activate" or "CC_activate" bit and sending back an
acknowledgment.
______________________________________________________________________________________________
56
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:53
Resource Management Cells
02
10
:21
Resource Management (RM) cells are identified by PTI=110 for VC-RM cells and by
VCI=6 for VP-RM cells. As a programmable option, VP-RM cells can be further
qualified by PTI=110.
tem
be
r,
20
The RCMP-800 does not process the payload of these cells, but simply passes them
to the Output Cell Interface with a translated header. As an option, the RCMP-800
can copy the cells to the Microprocessor Cell Interface. RM cells are not included in
Performance Management blocks.
ep
Backward OAM and RM Cell Identification
hu
rsd
ay
,1
9S
All RCMP-800-generated backward flow OAM cells, and forward and backward
Resource Management cells may be marked for easy identification by an external
processing device. As a configurable option, the RCMP-800 can overwrite an
arbitrary byte in the cell's appended bytes or header with a Cell Status Information
byte. The contents of the Cell Status Information byte consist of the following:
io
nT
Cell Status Information byte
BWDROUTINGTAG[7:3]
CELLID[2:0]
Do
wn
loa
de
db
yV
CELLID[2:0]
000
inv
ef
uo
fo
liv
ett
The five-bit BWDROUTINGTAG[4:0] is stored in the VC table at SA[19:16] = 0011,
and is only used for generated backward OAM cells (i.e. generated RDI and
Backward Reporting). It overwrites the value normally presented for forward destined
cells, so as to provide a distinction. For example, the BWDROUTINGTAG may
contain the PHY identification for the egress device. The CELLID[2:0] field is
encoded in all cells as follows:
001
010
Definition
All other cells:
• cells received via the Input Cell Interface
• cells inserted via the Microprocess Cell Inferface if
• the UPHDRX register bit is a logic 1
• generated AIS cells if the TAGAIS register bit is a
logic 0
• generated Continuity Check cells
Forward RM cell.
Backward RM cell.
______________________________________________________________________________________________
57
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
Backward generated OAM cells:
• generated RDI
• generated Backward Reporting
• generated AIS if the TAGAIS register bit is a logic 1
Reserved
10
:21
:53
011
02
100-111
tem
be
r,
20
For all generated backward OAM cells (i.e. generated RDI and Backward Reporting),
the RCMP-800 can be programmed to enable or disable header translation. That is,
the RCMP-800 can insert either the ingress VPI/VCI or the translated VPI/VCI for a
backward generated OAM cell.
9S
ep
Multicasting
liv
ett
io
nT
hu
rsd
ay
,1
The RCMP-800 supports multicasting. A single received cell can result in an arbitrary
number of cells presented on the Output Cell Interface, each with its own unique
VPI/VCI value and appended bytes. The ATM cell payload is duplicated without
modification. Multicasting is implemented by having special code in the VC
identification search table which indicates that the VC Table Record identified by the
search process is one of a multicast set. That VC is processed and then the next VC
for the same received cell is identified by a linked list pointer in the search table. This
process can continue indefinitely. (Optionally, a 63 cell limit can be imposed as a
watch dog.)
Do
wn
loa
de
db
yV
inv
ef
uo
fo
Multicasting has limited utility in the ingress direction. Because the cells for
all VCs are queued at the Output Cell Interface, multicasting may result in
head-of-the-line blocking. Provided the multicasting cannot result in an
instantaneous rate greater than the bandwidth supported by the Output Cell
Interface (e.g. 800Mbit/s with a 50MHz 16-bit bus), no problems shall occur.
It is the Connection Admission Control entity's responsibilty to ensure the
traffic is within the rate supported.
______________________________________________________________________________________________
58
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
02
10
:21
:53
Cell counting, cell rate policing and OAM processing is performed on the received
cell, if so enabled. Therefore, the connection statistics for the multicast group are
available in the VC Table Record at the head of the linked list. If the received cell is
discarded due to policing, no multicasted cells are created. If the received cell is
tagged, all multicasted cells are also tagged.
tem
be
r,
20
For multicast connections not at the head of the linked list, policing and cell counting
are suppressed, in order to conserve bandwidth. The CLP=1, CLP=0 and noncompliant counts are not valid.
9S
ep
Each branch connection has its own VC Table Record. Therefore, header translation
and OAM is supported independently for each branch.
,1
Output Buffering
nT
hu
rsd
ay
The output buffer consists of a four cell FIFO which transfers the oldest cell to the
switch port whenever it signals that it will accept a cell. The FIFO output is a slave to
the switch port. If the output buffer becomes full, it provides back-pressure to the Cell
Processor which in turn back-pressures the Input Cell Interface.
io
Congestion Control
uo
fo
liv
ett
Congestion control is handled by a single signal, CONG, entering the device. When
this signal indicates that congestion is being experienced by the switch core, all low
priority cells (high CLP bit) are discarded. This includes cells which are made low
priority during the policing process.
inv
ef
JTAG Test Access Port Interface
Do
wn
loa
de
db
yV
The JTAG Test Access Port block provides JTAG support for boundary scan. The
standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST instructions
are supported. The RCMP-800 identification code is 273220CD hexadecimal.
Microprocessor Interface
The microprocessor interface is provided for device configuration, control and
monitoring by an external microprocessor. Normal mode registers, test mode
registers and the external SRAM can be accessed through this port. Test mode
registers are used to enhance the testability of the RCMP-800.
The interface has a 16 bit wide data bus. Multiplexed address and data operation is
supported.
______________________________________________________________________________________________
59
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:53
SRAM Accesses
tem
be
r,
20
02
10
:21
Microprocessor access to the external SRAM is provided to allow configuration and
monitoring of individual connections. The VPI/VCI search state machine allocates a
single cycle at the end of each search for microprocessor access. The maximum
time to complete a SRAM access is 1200 ns with a SYSCLK frequency of 50 MHz.
The average completion time is less than 360 ns.Upon placing the device in stand-by
mode (default upon power up), all SRAM cycles become available to the
microprocessor. This allows for rapid configuration of the device at start-up.
,1
9S
ep
SRAM writes are initiated by writing the values to be presented on the SD[39:0] and
SA[19:0] outputs to the External RAM Data and the External RAM Address registers.
The BUSY status bit and the BUSYB output are asserted until the actual SRAM
access is completed.
nT
hu
rsd
ay
SRAM reads are initiated by writing the values to be presented on the SA[19:0]
outputs to the External RAM Address registers. The values read on the SD[39:0] bus
can be read from the External RAM Data registers after the BUSY status bit and the
BUSYB output are deasserted.
liv
ett
io
The BUSYB output can be connected to a DMA request input of a DMA controller.
The rising edge of BUSYB would initiate the next SRAM access upon the completion
of the current access.
uo
fo
Writing Cells
yV
inv
ef
The RCMP-800 contains a one cell buffer for the assembly of a cell by the
microprocessor for presentation on the Output Cell Interface. Optional header
translation and CRC-10 protection provides full support of diagnostic and OAM
requirements.
Do
wn
loa
de
db
Writes are performed by manipulating the Microprocessor Buffer Control and Status
(0x11) and Microprocessor Buffer Data (0x12) registers. Follow the steps below to
write a cell:
1.)
Poll the INSRDY bit in the Microprocessor Insert Buffer Control and Status
register until it is a logic 1. Alternately, service the interrupts that result from
setting the INSRDYE bit in the Master Interrupt Enable #1 (0x04) register.
The INSRDYI bit in the Master Interrupt Status #1 (0x02) register is set
whenever the INSRDY bit is asserted.
2.)
Write the WRSOC bit in the Microprocessor Insert Buffer Control and Status
register. At the same time, ensure that the OLEN[2:0], CRC10, UPHDRX
______________________________________________________________________________________________
60
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
:53
and PHY[4:0] register bits are set to their correct values, depending on what
operation is required.
Write the cell contents to the Microprocessor Buffer Data register. Each
subsequent write enters the next word in the cell. The words shall be written
in the following order:
tem
be
r,
3.)
20
02
10
If UPHDRX is a logic 1, PHY[4:0] represents the input PHY address that the
cell is associated with and will be included in the search key used for VC
identification.
Contents
1
1st pre-pended word (optional)
...
...
,1
9S
ep
Word #
Last pre-pended word, M • N (optional)
M+1
1st post-pended word (optional)
hu
rsd
ay
M
...
nT
...
Last post-pended word, N < 6 (optional)
N+1
ATM header: GFC, VPI and VCI
ett
io
N
ATM header: VCI, PTI and CLP
liv
N+2
fo
N+3
uo
N+4
1st ATM payload word
2nd ATM payload word
...
24th ATM payload word
db
yV
N+27
inv
...
ef
N+5
HEC and User Defined Field
Do
wn
loa
de
If the cell's header is to be translated (UPHDRX logic 1), the number
appended words shall match that programmed in the Input Cell FIFO
Configuration register. If the cell's header is not be to translated (UPHDRX
logic 0), the number appended words shall match that programmed in the
Output Cell FIFO Configuration register. The RCMP-800 automatically
handles cell length mismatches. Extra words shall be stripped with no
consequences, but words that must be added to the end of the appended
bytes will have arbitrary contents; therefore, the resulting cell processing may
be unpredictable. Note that if extra words are to be stripped off, the first
words of the cell are discarded until the lengths are equal.
______________________________________________________________________________________________
61
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
:53
If the UPHDRX register bit is a logic 0, the written cell is presented verbatim
on the Output Cell Interface.
02
10
Upon completion of a cell write, the cell will be transferred in the next available time
slot.
tem
be
r,
20
The above sequence may be repeated to insert further cells. The assertion of the
INSRDY bit indicates the transfer has been completed.
Reading Cells
9S
ep
Cells received on the Input Cell Interface can be routed to the Microprocessor Cell
Buffer based on the contents of the cell.
fo
liv
ett
io
nT
2
3
4
5
6
7
Buffer Capacity
rsd
hu
ILEN[2:0]
18
18
17
17
16
15
uo
Words
in cell
27
28
29
30
31
32
ay
,1
The buffer has a capacity of fifteen to eighteen cells depending on the length of the
extracted cells:
yV
inv
ef
Maskable interrupt status bits are generated upon the receipt of a cell and upon a
buffer overflow. If a buffer overflow occurs, entire cells are lost (the new incoming
cells would be lost).
Do
wn
loa
de
db
Cells are written into the buffer without header translation. As an option, the HEC
byte location can be overwritten with the PHY device identification. The length of the
cell is determined by the CELLLEN[3:0] bits in the Input Cell FIFO Configuration
register and the UPURS bit of the Cell Processor Configuration register. If the
UPURS bit is a logic one, a causation word is prepended to the cell to indicate why
the cell was routed to the Microprocessor Cell Buffer and provide cell status
information.
______________________________________________________________________________________________
62
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
10
02
20
r,
tem
be
ep
nT
hu
rsd
ay
,1
9S
Definition
PHYID[4]
PHYID[3]
PHYID[2]
PHYID[1]
PHYID[0]
PROV
End_pt
Seg_End_pt
Reserved
NNI
VPC
OAM_type
TYP[3]
TYP[2]
TYP[1]
TYP[0]
io
CAUSE[15:0]
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
:53
The causation word has the following format:
ett
PHYID[4:0]: The index of the PHY device associated with the cell.
Provisioned indication. This bit is a logic 1 is the cell belongs to a
provision connection. A logic 0 indicates the connection search failed
to find a VC Table Record for the cell. The End_pt, Seg_Eng_pt, NNI
and VPC bits are undefined if PROV is a logic 0.
End_pt:
Indicates if the connection is provisioned as an OAM flow end point.
yV
inv
ef
uo
fo
liv
PROV:
Do
wn
loa
de
db
Seg_Eng_pt: Indicates if the connection is provisioned as an OAM segment flow
end point.
NNI:
Indicates if the connection is associated with a Network-Network
Interface (NNI). A logic 0 means the connection belongs to a UserNetwork Interface (UNI).
VPC:
Indicates if the connection is provisioned as a Virtual Path Connection
(VPC). A logic 0 means the connection is provisioned as a Virtual
Channel Connection (VCC).
______________________________________________________________________________________________
63
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
20
r,
io
nT
hu
rsd
ay
,1
9S
ep
tem
be
Cell Type
User
AIS
RDI
Continuity Check
Loopback
Forward Monitoring
Backward Reporting
Monitoring/Reporting
Activate/Deactivate
Undefined OAM
Reserved
Forward RM
Backward RM
Invalid PTI
Reserved
OAM cell with errored
CRC-10.
uo
fo
liv
TYP[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
02
Cell type. It is encoded as follows:
ett
TYP[3:0]
10
:21
:53
OAM_type: A logic 1 identifies a segment OAM cell. A logic 0 identifies an end-toend OAM cell. This bit is not defined when the TYP[3:0] field is 0000,
1011, 1100 or 1101.
Do
wn
loa
de
db
yV
inv
ef
The EXTCA bit of the Microprocessor Extract Buffer Control and Status (0x11)
register is asserted if one or more complete cells are available in the buffer. If DMA
control is enabled (DMAEN bit logic 1), the DREQ output is also asserted upon
receipt of a cell. The first read of the Microprocessor Cell Buffer after either the
EXTCA bit or the DREQ is asserted returns the first word of the cell. Subsequent
reads return the remainder of the cell. The sequence of the words is the same as for
buffer writes (see above). At any time the read pointer can be returned to the
beginning of the cell by setting the RESTART bit. The current cell is discarded upon
setting the ABORT bit. The DREQ output is deasserted during the read of the last
word of the cell.
______________________________________________________________________________________________
64
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
tem
be
r,
20
02
Register
Identification and Master Reset / Load Meters
Master Configuration
Interrupt Status #1
Interrupt Status #2
Interrupt Enable #1
Interrupt Enable #2
Master Clock Monitor
Latest Alarmed Connections
Input Cell FIFO Configuration
Physical Layer Cell Counter
Input Cell Counter (LSB)
Input Cell Counter (MSB)
Input Polling Configuration
Reserved
Microprocessor Extract Buffer Control and Status
Microprocessor Insert Buffer Control and Status
Microprocessor Cell Data
Reserved
Cell Processor Configuration
Performance Monitoring Configuration 1
Performance Monitoring Configuration 2
ABR Cell Rate Policing Configuration
VBR/CBR Cell Rate Policing Configuration
Routing Configuration
Reserved
CRAM Configuration
External RAM Address (LSB)
External RAM Address (MSB) and Access Control
External RAM Data (LSB)
External RAM Data
External RAM Data (MSB)
Maximum VC Table Index
Search Key Construction
Field A Location and Length
Field B Location and Length
Reserved
Do
wn
loa
de
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D-0x0F
0x10
0x11
0x12
0x13-0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E-0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A-0x2F
:21
Normal Mode Register Memory Map
______________________________________________________________________________________________
65
PM7322 RCMP-800
STANDARD PRODUCT
:53
:21
10
02
20
r,
9S
ep
tem
be
Counter Status
Valid OAM Cell Count
Errored OAM Cell Count
Invalid Cell Count
Count of Cells Dropped Due to Congestion
Reserved
Output Cell FIFO Configuration
Reserved
Output Cell Counter (LSB)
Output Cell Counter (MSB)
Reserved
Master Test
Reserved for Test
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
0x30
0x31
0x32
0x33
0x34
0x35-0x37
0x38
0x39
0x3A
0x3B
0x3C-0x3F
0x40
0x41-0x7F
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
______________________________________________________________________________________________
66
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
NORMAL MODE REGISTER DESCRIPTIONS
20
02
10
Normal mode registers are used to configure and monitor the operation of the RCMP800. Normal mode registers (as opposed to test mode registers) are selected when
TRS (A[6]) is low.
tem
be
r,
Notes on Normal Mode Register Bits:
,1
9S
ep
1. Writing values into unused register bits has no effect. However, to ensure
software compatibility with future, feature-enhanced versions of the product,
unused register bits must be written with logic 0. Reading back unused bits can
produce either a logic 1 or a logic 0; hence unused register bits should be masked
off by software when read.
hu
rsd
ay
2. All configuration bits that can be written into can also be read back. This allows
the processor controlling the RCMP-800 to determine the programming state of
the block.
io
nT
3. Writeable normal mode register bits are cleared to logic 0 upon reset unless
otherwise noted.
fo
liv
ett
4. Writing into read-only normal mode register bit locations does not affect RCMP800 operation unless otherwise noted.
Do
wn
loa
de
db
yV
inv
ef
uo
5. Certain register bits are reserved. These bits are associated with megacell
functions that are unused in this application. To ensure that the RCMP-800
operates as intended, reserved register bits must only be written with logic 0.
Similarly, writing to reserved registers should be avoided.
______________________________________________________________________________________________
67
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:53
Master Registers
10
02
20
r,
tem
be
ep
9S
,1
ay
rsd
nT
R
R
R
R
R
R
R
Default
0
X
X
X
X
X
X
X
X
0
0
1
0
0
1
0
hu
Function
RESET
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
TYPE[2]
TYPE[1]
TYPE[0]
ID[3]
ID[2]
ID[1]
ID[0]
io
Type
R/W
ett
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
:21
Register 0x00: Master Reset and Identity / Load Meters
uo
fo
liv
This register allows the revision of the RCMP-800 to be read by software. This
permits graceful migration to newer, feature enhanced versions of the RCMP-800.
yV
inv
ef
In addition, writing to this register simultaneously loads the aggregate performance
meter registers located at addresses 0x09, 0x0A, 0x0B, 0x31, 0x32, 0x33, 0x34,
0x3A and 0x3B.
Do
wn
loa
de
db
ID[3:0]:
The ID bits can be read to provide a binary RCMP-800 revision number.
TYPE[2:0]:
The TYPE bits can be read to distinguish the RCMP-800 from the other
members of the RCMP-800 family of devices.
RESET:
The RESET bit allows the RCMP-800 to be reset under software control. If the
RESET bit is a logic 1, the entire RCMP-800 is held in reset. This bit is not
self-clearing. Therefore, a logic 0 must be written to bring the RCMP-800 out
of reset. Holding the RCMP-800 in a reset state places it into a low power,
______________________________________________________________________________________________
68
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
:53
stand-by mode. A hardware reset clears the RESET bit, thus negating the
software reset.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
tem
be
r,
20
02
10
Note, unlike the hardware reset input, RSTB, the software reset bit, RESET
does not force the RCMP-800's digital output pins tristate.
______________________________________________________________________________________________
69
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
02
20
r,
tem
be
ep
9S
,1
ay
rsd
Default
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
1
hu
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Unused
Unused
Unused
Unused
Unused
Unused
BUSYPOL
DREQINV
XPOLVC
RDIVC
AISVC
POLVC
CCVC
SEL1SEC
CLKRATE
STANDBY
nT
Type
io
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
:21
Register 0x01: Master Configuration
inv
ef
uo
fo
liv
ett
STANDBY:
The STANDBY bit disables cell processing to avoid the passing of corrupted
cells while initializing the RCMP-800. When STANDBY is a logic 1, the
RCMP-800 is in a low power state with the cell processor and cell buffers held
in reset. Microprocessor registers and the external SRAM can still be
accessed. STANDBY resets to a logic 1.
Do
wn
loa
de
db
yV
If the STANDBY bit is set while cell processing is in progress, the processing
of cells currently in the pipeline is completed, but no more cells are transferred
into the RCMP-800.
CLKRATE:
The CLKRATE bit selects between a 25 MHz and 50 MHz SYSCLK frequency.
If CLKRATE is a logic 1, a 25 MHz clock is expected; otherwise, a 50 MHz
clock is expected. Other rates are allowable, but fault monitoring cells and
alarms will not be generated at correct intervals. The CLKRATE bit has no
effect if the SEL1SEC bit is a logic 1.
SEL1SEC:
The SEL1SEC bit determines the trigger for processing that relies on an one
second clock, such as AIS and RDI cell generation. If SEL1SEC is a logic 0,
______________________________________________________________________________________________
70
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
:21
:53
the one second clock is derived from the SYSCLK, which is assumed to be 25
or 50 MHz. If SEL1SEC is a logic 1, processing is initiated on the rising edge
of the ONESEC input.
ep
tem
be
r,
20
02
XPOLVC:
The XPOLVC (excessive policing) bit enables the updating of the Latest
Alarmed Virtual Connection register (0x07) upon the receipt of a cell belonging
to a connection which has a one in the most significant bit position of one of
the Non-Compliant Cell Count fields. If XPOLVC is a logic 1, the Latest
Alarmed Virtual Connection register will be loaded with the VC Table index of
the corresponding virtual connection.
ay
,1
9S
This functionality allows long integration intervals for well behaved
connections, while providing the ability to transfer the Non-Compliant Cell
Counts of unrestrained connections before they saturate.
ett
io
nT
hu
rsd
CCVC:
The CCVC bit enables the updating of the Latest Alarmed Virtual Connection
register (0x07) upon the change in a Continuity Check alarm status. If CCVC
is a logic 1, the Latest Alarmed Virtual Connection register will be loaded with
the VC Table index corresponding to the virtual connection whose “CC_alarm”
bit has changed.
yV
inv
ef
uo
fo
liv
POLVC:
The POLVC bit enables the updating of the Latest Alarmed Virtual Connection
register (0x07) upon the receipt of a cell violating a traffic contract. If POLVC
is a logic 1, the Latest Alarmed Virtual Connection register will be loaded with
the VC Table index corresponding to the virtual connection whose "POLI" bit
has been asserted.
Do
wn
loa
de
db
AISVC:
The AISVC bit enables the updating of the Latest Alarmed Virtual Connection
register (0x07) upon the change in an AIS alarm status. If AISVC is a logic 1,
the Latest Alarmed Virtual Connection register will be loaded with the VC
Table index corresponding to the virtual connection whose "AIS" bit has
changed.
RDIVC:
The CCVC bit enables the updating of the Latest Alarmed Virtual Connection
register (0x07) upon the change in a RDI alarm status. If RDIVC is a logic 1,
the Latest Alarmed Virtual Connection register will be loaded with the VC
Table index corresponding to the virtual connection whose “RDI” bit has
changed.
______________________________________________________________________________________________
71
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
:21
:53
DREQINV:
The DREQINV bit inverts the polarity of the DREQ primary output. If
DREQINV is a logic 0, the DREQ output is active high. If DREQINV is a logic
1, the DREQ output is active low.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
tem
be
r,
20
02
BUSYPOL:
The BUSYPOL bit sets the polarity of the BUSYB primary output. If BUSYPOL
is a logic 0, the BUSYB output is active low. If BUSYPOL is a logic 1, the
BUSYB output is active high.
______________________________________________________________________________________________
72
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
02
20
r,
tem
be
ep
9S
,1
ay
rsd
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
hu
Function
REG3I
XFERI
INSRDYI
UPCAI
UPFOVRI
VCVALID
FULLI
PCELLI
XPOLI
RDII
AISI
POLI
CCI
OAMERRI
PTIVCII
INVALI
nT
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
io
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
:21
Register 0x02: Master Interrupt Status #1
fo
liv
ett
This register allows the source of an active interrupt to be identified. All bits in this
register except REG3I are reset immediately after a read to this register.
db
yV
inv
ef
uo
INVALI:
The INVALI bit indicates a cell with an unprovisioned VPI/VCI combination or
invalid routing bits has been received. When logic 1, the INVALI bit indicates
one or more VC Table searches have not resulted in a match. A logic 1 may
also indicate that a Resource Management cell with an incorrect CRC-10 has
been received. This bit is cleared when this register is read.
Do
wn
loa
de
PTIVCII:
The PTIVCII bit indicates a cell with an invalid PTI or VCI field has been
received. When logic 1, the PTIVCII bit indicates one or more VCC cells have
contained PTI='111', one or more VPC cells with an invalid VCI field (VCI 7
through 15) or at least one VP Resource Management cell has been received
with PTI not equal to '110'. This bit is cleared when this register is read.
______________________________________________________________________________________________
73
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
tem
be
r,
20
02
10
:21
:53
OAMERRI:
The OAMERRI bit indicates an OAM cell has been with an incorrect OAM
Type, Function Type or Error Detection Code field. When logic 1, the
OAMERRI bit indicates one or more errored OAM cells have been received.
This bit is cleared when this register is read. Note that the assertion of the
OAMERRI bit for OAM cells with incorrect OAM Type or Function Type fields is
dependent on the state of the CNTUNDEF bit of the CRAM Configuration
register (register 0x20). If CNTUNDEF is a logic 1, then only OAM cells with
an incorrect Error Detection Code field (i.e. CRC-10 errors) will result in an
assertion of the OAMERRI bit.
ep
CCI:
ay
,1
9S
The CCI bit indicates a Continuity Check alarm has changed state. When logic
1, the CCI bit indicates the "CC_alarm" bit in the VC Table has changed for
one or more virtual connections. This bit is cleared when this register is read.
nT
hu
rsd
If the CCVC bit of the Master Configuration register is a logic 1, the Latest
Alarmed Virtual Connection register is updated with the VC Table index for the
virtual connection simultaneously with the setting of the CCI bit.
io
POLI:
uo
fo
liv
ett
The POLI bit indicates a non-compliant cell has been received. When logic 1,
the POLI bit indicates one or more cells have violated the traffic contract since
the last read of this register. This bit is cleared when this register is read.
yV
inv
ef
If the POLVC bit of the Master Configuration register is a logic 1, the Latest
Alarmed Virtual Connection register is updated with the VC Table index for the
virtual connection simultaneously with the setting of the POLI bit.
db
AISI:
Do
wn
loa
de
The AISI bit indicates an AIS alarm has changed state. When logic 1, the AISI
bit indicates one or more virtual connections have either entered or left the AIS
state. This bit is cleared when this register is read.
If the AISVC bit of the Master Configuration register is a logic 1, the Latest
Alarmed Virtual Connection register is updated with the VC Table index for the
virtual connection simultaneously with the setting of the AISI bit.
RDII:
The RDII bit indicates a RDI alarm has changed state. When logic 1, the RDII
______________________________________________________________________________________________
74
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
:53
bit indicates one or more virtual connections have either entered or left the RDI
state. This bit is cleared when this register is read.
20
02
10
If the RDIVC bit of the Master Configuration register is a logic 1, the Latest
Alarmed Virtual Connection register is updated with the VC Table index for the
virtual connection simultaneously with the setting of the RDII bit.
9S
ep
tem
be
r,
XPOLI:
The excessive policing indication (XPOLI) bit becomes a logic 1 upon the
receipt of a cell belonging to a connection which has a one in the most
significant bit position of one of the Non-Compliant Cell Count fields. This bit
is reset immediately after a read to this register.
rsd
ay
,1
If the XPOLVC bit of the Master Configuration register is a logic 1, the Latest
Alarmed Virtual Connection register is updated with the VC Table index for the
virtual connection simultaneously with the setting of the XPOLI bit.
io
nT
hu
PCELLI:
The PCELLI bit indicates a physical layer cell has been received. When logic
1, the PCELLI bit indicates one or more cells with an all zero VCI value and a
CLP=1 have been received. This bit is cleared when this register is read.
ef
uo
fo
liv
ett
VCVALID:
The VCVALID bit becomes a logic 1 when the Latest Alarmed Virtual
Connections register (0x07) contains valid information. This bit is NOT cleared
when this register is read. This bit is cleared when the entire contents of the
Latest Alarmed Virtual Connections register (0x07) FIFO have been read.
db
yV
inv
An image of the VCVALID bit is at address location (0x04). It is provided so
that VCVALID may be sampled without clearing the interrupt status bits in this
register.
Do
wn
loa
de
FULLI:
The FULLI bit becomes a logic 1 when the output buffer has been filled to its 4
cell capacity. This may indicate failure or congestion in the entity connected to
the Output Cell Interface. This bit is cleared when this register is read.
The FULLI bit may also become a logic 1 as a result of setting the FIFORST
bit of the Output Cell Configuration register (0x38). With the output FIFO
reset, it is unable to accept any cells, which is the same immediate symptom
as a full buffer.
______________________________________________________________________________________________
75
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
:21
:53
UPFOVRI:
The UPFOVRI bit is set high when a Microprocessor Cell Interface extract
buffer overrun occurs. This bit is reset immediately after a read to this register.
tem
be
r,
20
02
UPCAI:
The UPCAI bit indicates that a cell has been written into the Microprocessor
Cell extract buffer and is ready for processing. When logic 1, the UPCAI bit
indicates that the EXTCA bit in the Microprocessor Extract Buffer Control and
Status (0x10) register has been asserted. The UPCAI bit is cleared when this
register is read.
ay
,1
9S
ep
INSRDYI:
The INSRDYI bit indicates the Microprocessor Cell Interface insert buffer is
empty and is ready for another cell. This bit is cleared when this register is
read.
ett
io
nT
hu
rsd
XFERI:
The XFERI bit indicates that the aggregate cell counters have been
transferred to holding registers and the contents should be read. When logic
1, the XFERI bit indicates that either the XFER or OVR bit in the Counter
Status (0x30) register has been asserted. The XFERI bit is cleared when this
register is read.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
REG3I:
The REG3I bit indicates that at least one bit in Register 0x03, RCMP-800
Master Interrupt Status #2, is currently asserted.
______________________________________________________________________________________________
76
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
02
20
r,
tem
be
ep
9S
,1
ay
rsd
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
hu
R
R
R
R
R
R
R
R
R
Function
Unused
Unused
Unused
Unused
Unused
Unused
SRCHERRI
SPRTYI[4]
SPRTYI[3]
SPRTYI[2]
SPRTYI[1]
SPRTYI[0]
IPRTYI[1]
IPRTYI[0]
ISOCI
Unused
nT
Type
io
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
:21
Register 0x03: Master Interrupt Status #2
ef
uo
fo
liv
ett
ISOCI:
The ISOCI bit is set high when the ISOC input is sampled high during any
position other than the first word of the selected data structure. The write
address counter is reset to the first word of the data structure when ISOC is
sampled high. This bit is reset immediately after a read to this register.
Do
wn
loa
de
db
yV
inv
IPRTYI[1:0]:
The IPRTYI[1:0] bits indicate a parity error has been detected on the
IDAT[15:0] bus. When logic 1, the IPRTYI[1] bit indicates a parity error over
inputs IDAT[15:0] (in word parity mode) or IDAT[15:8] (in byte parity mode).
Similarly, when logic 1, the IPRTYI[0] bit indicates a parity error over inputs
IDAT[7:0] in byte parity mode. (IPRTYI[0] is unused in word parity mode, i.e.,
when the IBYTEPRTY register bit is logic zero). Both bits are cleared when
this register is read. Odd or even parity is selected using the IPTYP bit.
SPRTYI[4:0]:
The SPRTYI[4:0] bits indicate a parity error has been detected on the SD[39:0]
bus. When logic 1, the SPRTYI[4] bit indicates a parity error over inputs
SD[39:32]. When logic 1, the SPRTYI[3] bit indicates a parity error over inputs
SD[31:24]. When logic 1, the SPRTYI[2] bit indicates a parity error over inputs
SD[23:16]. When logic 1, the SPRTYI[1] bit indicates a parity error over inputs
______________________________________________________________________________________________
77
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
:53
SD[15:8]. When logic 1, the SPRTYI[0] bit indicates a parity error over inputs
SD[7:0]. All bits are cleared when this register is read.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
tem
be
r,
20
02
10
SRCHERRI:
The search error (SRCHERRI) bit indicates that a VCI/VPI search has failed
due to an improperly constructed secondary search table. This bit is set if the
secondary key search takes more then 40 branches or if single received cell
results in greater than 63 multicast cells when the LIMITMC register bit is logic
1. If the BADVCtoUP register bit is a logic 1, the cell associated with the failed
search is routed to the Microprocessor Cell Interface. This bit is cleared when
this register is read.
______________________________________________________________________________________________
78
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
02
20
r,
tem
be
ep
9S
,1
ay
rsd
Default
X
0
0
0
0
X
0
0
0
0
0
0
0
0
0
0
hu
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Unused
XFERE
INSRDYE
UPCAE
UPFOVRE
VCVALID
FULLE
PCELLE
XPOLE
RDIE
AISE
POLE
CCE
OAMERRE
PTIE
INVALE
nT
Type
io
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
:21
Register 0x04: Master Interrupt Enable #1
uo
fo
liv
ett
The above enable bits control the corresponding interrupt status bits in the RCMP800 Master Interrupt Status #1 register. When an enable bit is set to logic 1, the
INTB output is asserted low when the corresponding interrupt status bit is a logic 1.
db
yV
inv
ef
VCVALID:
The VCVALID bit becomes a logic 1 when the Latest Alarmed Virtual
Connections register (0x07) contains valid information. This bit is cleared
when the entire contents of the Latest Alarmed Virtual Connections register
(0x07) FIFO have been read.
Do
wn
loa
de
This bit is an image of the VCVALID bit in the Master Interrupt Status #1
register (0x02). It is provided so that VCVALID may be sampled without
clearing the interrupt status bits.
______________________________________________________________________________________________
79
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
02
20
r,
tem
be
ep
9S
,1
ay
rsd
Default
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
X
hu
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Unused
Unused
Unused
Unused
Unused
Unused
SRCHERRE
SPRTYE[4]
SPRTYE[3]
SPRTYE[2]
SPRTYE[1]
SPRTYE[0]
IPRTYE[1]
IPRTYE[0]
ISOCE
Unused
nT
Type
io
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
:21
Register 0x05: Master Interrupt Enable #2
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
The above enable bits control the corresponding interrupt status bits in the RCMP800 Master Interrupt Status #2 register. When an enable bit is set to logic 1, the
INTB output is asserted low when the corresponding interrupt status bit is a logic 1.
______________________________________________________________________________________________
80
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
10
02
20
r,
tem
be
ep
9S
,1
ay
rsd
R
R
R
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
hu
Function
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
IFCLKA
OFCLKA
SYSCLKA
nT
Type
io
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
:53
Register 0x06: Master Clock Monitor
inv
ef
uo
fo
liv
ett
This register provides activity monitoring on RCMP-800 clocks. When a monitored
clock signal makes a low to high transition, the corresponding register bit is set high.
The bit will remain high until this register is read, at which point, all the bits in this
register are cleared. A lack of transitions is indicated by the corresponding register
bit reading low. This register should be read at periodic intervals to detect clock
failures.
Do
wn
loa
de
db
yV
IFCLKA:
The IFCLK active (IFCLKA) bit monitors for low to high transitions on the
IFCLK output. IFCLKA is set high on a rising edge of IFCLK, and is set low
when this register is read.
OFCLKA:
The OFCLK active (OFCLKA) bit monitors for low to high transitions on the
OFCLK output. OFCLKA is set high on a rising edge of OFCLK, and is set low
when this register is read.
SYSCLKA:
The SYSCLK active (SYSCLKA) bit monitors for low to high transitions on the
SYSCLK input. SYSCLKA is set high on a rising edge of SYSCLK, and is set
low when this register is read.
______________________________________________________________________________________________
81
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
10
02
20
r,
tem
be
ep
9S
,1
ay
rsd
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
hu
Function
VCINDEX[15]
VCINDEX[14]
VCINDEX[13]
VCINDEX[12]
VCINDEX[11]
VCINDEX[10]
VCINDEX[9]
VCINDEX[8]
VCINDEX[7]
VCINDEX[6]
VCINDEX[5]
VCINDEX[4]
VCINDEX[3]
VCINDEX[2]
VCINDEX[1]
VCINDEX[0]
nT
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
io
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
:53
Register 0x07: Latest Alarmed Virtual Connections
inv
ef
uo
fo
liv
ett
VCINDEX[15:0]:
The VCINDEX[15:0] bits represent a pointer to the VC Table Record whose
"Status" field has changed recently. This register is updated when one of the
XPOLI, RDII, AISI, POLI or CCI bits in the Master Interrupt Status #2 register
is asserted. The XPOLVC, RDIVC, AISVC, POLVC and CCVC bits of the
Master Configuration register independently allow each of the five alarms to
update this register.
Do
wn
loa
de
db
yV
This register is FIFOed. Up to seven VC indices are stored and are accessed
by successive reads of this register. A logic one in the VCVALID bit position in
the Master Interrupt Status #1 register (0x02) indicates one or more VC
indices have been queued. (An image of the VCVALID bit is provided in
register address 0x04 for convenience.) An overflow of the FIFO results in
new information replacing the old. To guarantee no information is lost, this
register must be read within 3.8µs of the associated interrupt assertion. (This
assumes each of eight consecutive cells causes an alarm.) It is recommended
the entire contents of the FIFO be transferred and cached for subsequent
processing.
______________________________________________________________________________________________
82
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
tem
be
r,
20
02
10
:21
:53
VCINDEX[15:0] corresponds to the value which must be written into the
External RAM Address (LSB) register to access the new status information of
the virtual connection.
______________________________________________________________________________________________
83
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
02
20
r,
tem
be
ep
9S
,1
ay
rsd
Default
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
hu
Function
HECUDF
ICAINV
CELLPOST[3]
CELLPOST[2]
CELLPOST[1]
CELLPOST[0]
CELLLEN[3]
CELLLEN[2]
CELLLEN[1]
CELLLEN[0]
IBYTEPRTY
IPTYP
FIFODP[1]
FIFODP[0]
ICALEVEL0
FIFORST
nT
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
io
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
:21
Register 0x08: Input Cell FIFO Configuration
inv
ef
uo
fo
liv
ett
FIFORST:
The FIFORST bit is used to reset the four-cell input FIFO. When FIFORST is
set to logic zero, the input FIFO operates normally. When FIFORST is set to
logic one, the input FIFO is immediately emptied and ignores writes. The input
FIFO remains empty and continues to ignore writes until a logic zero is written
to FIFORST.
Do
wn
loa
de
db
yV
It is recommended that, whenever any other bit in this register or the Input
Polling Configuration register is changed, FIFORST be set to logic one upon
the change and set to logic zero after.
______________________________________________________________________________________________
84
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
:53
ICALEVEL0:
The ICALEVEL0 bit determines how the ICA[4:1] inputs are interpreted.
20
02
10
If ICALEVEL0 is a logic 1, the RCMP-800 checks for close compliance to the
SCI-PHY cell transfer handshake. If the ICA signal for the PHY whose cell is
currently being transferred is deasserted before the end of the cell, the cell will
be discarded.
ep
tem
be
r,
If ICALEVEL0 is a logic 0, the ICA signal may be deasserted early without the
loss of the cell. Once a cell transfer is initiated, the entire cell will be read
contiguously regardless of the state of the ICA signal.
,1
9S
ICALEVEL0 is ignored if the address polling mode is selected (IPOLL input is
high).
io
nT
hu
rsd
ay
FIFODP[1:0]:
The FIFODP[1:0] bits determine the input FIFO cell depth. FIFO depth control
may be important in systems where the cell latency through the RCMP-800
must be minimized. The RCMP-800 will stop reading cells when the specified
depth is reached. The selectable FIFO cell depths are shown below:
FIFODP[0]
0
1
0
1
FIFO DEPTH
4 cells
3 cells
2 cells
1 cell
ef
uo
fo
liv
ett
FIFODP[1]
0
0
1
1
Do
wn
loa
de
db
yV
inv
IPTYP:
The IPTYP bit selects even or odd parity for inputs IPRTY[1:0]. When set to
logic 1, input IPRTY[1] is the even parity bit for inputs IDAT[15:8] while input
IPRTY[0] is the even parity bit for inputs IDAT[7:0]. When set to logic 0, inputs
IPRTY[1:0] are the odd parity bits for inputs IDAT[15:0].
IBYTEPRTY:
The active-high input byte parity selector bit, IBYTEPRTY, selects between
byte parity (2 parity bits, each over an 8-bit byte) or word parity (1 parity bit
over a 16-bit word). If IBYTEPRTY is set high, IPRTY[1] is expected to be the
parity over IDAT[15:8] and IPRTY[0] is expected to be the parity over
IDAT[7:0]. If IBYTEPRTY is set low, IPRTY[1] is expected to be the parity
over IDAT[15:0] and IPRTY[0] is ignored. The IBYTEPRTY register bit is
ignored if the IBUS8 input is asserted, in which case IPRTY[0] is the parity
over IDAT[7:0] and IPRTY[1] is ignored.
______________________________________________________________________________________________
85
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
:21
:53
CELLLEN[3:0]:
The CELLLEN[3:0] bits determine the number of words appended to the input
cell.
tem
be
r,
20
02
When IBUS8 is a logic 1, the binary CELLLEN[3:0] value is the number of
bytes appended to the basic 53 byte ATM cell. The maximum cell length is 63
bytes; therefore, a CELLLEN[3:0] greater than 10 decimal results in 10
appended bytes.
9S
ep
When IBUS8 is a logic 0, the binary CELLLEN[3:0] value is the number of
words appended to the basic 27 word ATM cell. The maximum cell length is
32 words; therefore, a CELLLEN[3:0] greater than 5 decimal results in 5
appended words.
nT
hu
rsd
ay
,1
CELLPOST[3:0]:
The CELLPOST[3:0] bits determine the number of words in the input cell postpend. The numerical difference between CELLLEN[3:0] and CELLPOST[3:0]
represents the number of words in the pre-pend. It is inappropriate that
CELLPOST[3:0] exceed CELLLEN[3:0].
ett
io
When IBUS8 is a logic 1, the binary CELLPOST[3:0] value is the number of
bytes post-pended to the basic 53 byte ATM cell.
uo
fo
liv
When IBUS8 is a logic 0, the binary CELLPOST[3:0] value is the number of
words post-pended to the basic 27 word ATM cell.
Do
wn
loa
de
db
yV
inv
ef
ICAINV:
The ICAINV bit selects the active polarity of the ICA[4:1] signals. The default
configuration selects ICA[4:1] to be active high, indicating that a cell slot is
available in the input FIFO when high. When ICAINV is set to logic one, the
ICA[4:1] signals become active low. If the state of the ICAINV bit has been
changed, the input FIFO must be reset via the FIFORST bit in order to
properly initialize the ICA[4:1] outputs.
HECUDF:
The HECUDF bit determines whether or not the HEC/UDF octets are included
in cells transferred over the input interface. When set to logic 1 (default), the
HEC and UDF octets are included. When set to logic 0, these octets are
omitted. I.e., if BUS8 is logic 0, the third word of the 27-word ATM cell is
omitted and a 26-word cell (plus appended words) is transferred. If BUS8 is
logic 1, the fifth octet of the 53-octet ATM cell is omitted and a 52-octet cell
(plus appended octets) is transferred.
______________________________________________________________________________________________
86
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
02
20
r,
tem
be
ep
9S
,1
ay
rsd
R
R
R
R
R
R
R
R
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
hu
Function
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
PICELL[7]
PICELL[6]
PICELL[5]
PICELL[4]
PICELL[3]
PICELL[2]
PICELL[1]
PICELL[0]
nT
Type
io
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
:21
Register 0x09: Physical Layer Cell Count
fo
liv
ett
This register provides a count of the idle cells erroneously passed from the physical
layer.
yV
inv
ef
uo
PICELL[7:0]:
The PICELL[7:0] bits indicate the number of Physical Layer cells presented to
the Input Cell Interface during the last accumulation interval. A Physical Layer
cell is identified by a VPI value of zero, a VCI value of zero and a CLP value of
one. Physical Layer cells should not be present at the ATM Layer.
Do
wn
loa
de
db
A write to either address 0x00, 0x09, 0x0A or 0x0B loads the register with the
current counter value and resets the internal 8 bit counter to 1 or 0. The
counter reset value is dependent on if there was a count event during the
transfer of the count to the Physical Layer Idle Cell Counter registers. The
counter should be polled every second to avoid saturating. The contents of
these registers are valid within four IFCLK cycles after a transfer is triggered
by a write to address 0x00, 0x09, 0x0A or 0x0B.
______________________________________________________________________________________________
87
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
10
02
20
r,
tem
be
ep
9S
,1
ay
rsd
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
hu
Function
ICELL[15]
ICELL[14]
ICELL[13]
ICELL[12]
ICELL[11]
ICELL[10]
ICELL[9]
ICELL[8]
ICELL[7]
ICELL[6]
ICELL[5]
ICELL[4]
ICELL[3]
ICELL[2]
ICELL[1]
ICELL[0]
nT
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
:53
Register 0x0A: Input Cell Counter (LSB)
______________________________________________________________________________________________
88
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
10
02
20
r,
tem
be
ep
9S
,1
ay
rsd
R
R
R
R
R
R
R
R
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
hu
Function
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
ICELL[23]
ICELL[22]
ICELL[21]
ICELL[20]
ICELL[19]
ICELL[18]
ICELL[17]
ICELL[16]
nT
Type
io
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
:53
Register 0x0B: Input Cell Counter (MSB)
ett
ICELL[23:0]:
inv
ef
uo
fo
liv
The ICELL[23:0] bits indicate the number of cells read from the input FIFO
during the last accumulation interval. The count includes all user information
and OAM cells, regardless of whether the VPI/VCI value is provisioned. The
count does not include physical layer idle cells (VPI=0, VCI=0, CLP=1) and
unassigned cells (VPI=0, VCI=0, CLP=0).
Do
wn
loa
de
db
yV
A write to either address 0x00, 0x09, 0x0A or 0x0B loads the registers with the
current counter value and resets the internal 24 bit counter to 1 or 0. The
counter reset value is dependent on if there was a count event during the
transfer of the count to the Input Cell Counter registers. The counter should be
polled at least every 10 seconds to avoid saturating. The contents of these
registers are valid within four SYSCLK cycles after a transfer is triggered by a
write to address 0x00, 0x09, 0x0A or 0x0B.
______________________________________________________________________________________________
89
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
10
02
20
r,
tem
be
ep
9S
,1
ay
rsd
Default
X
X
X
X
X
X
X
X
X
0
1
0
0
0
0
0
hu
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Reserved
NNI
PHYDEV[4]
PHYDEV[3]
PHYDEV[2]
PHYDEV[1]
PHYDEV[0]
nT
Type
io
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
:53
Register 0xC: Input Polling Configuration
uo
fo
liv
ett
PHYDEV[4:0]:
The PHYDEV[4:0] bits are used when the RCMP-800 polls PHY devices using
IADDR[4:0] (i.e. when IPOLL is high). They indicate the number of PHY
devices to be polled as follows:
Meaning
inv
ef
PHYDEV[4:0]
Do
wn
loa
de
db
yV
00000
Poll all 32 PHY devices.
00001
Poll PHY#1 thru PHY#2
00010
Poll PHY#1 thru PHY#3
:
:
11110
Poll PHY#1 thru PHY#31
11111
Poll all 32 PHY devices
Setting PHYDEV[4:0] such that more PHY devices are polled than are actually
connected to the RCMP-800 will not cause malfunction (provided ICA[1] is
pulled low when undefined) but may result in loss of cell throughput due to
unnecessarily long polling cycle times.
______________________________________________________________________________________________
90
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:53
NNI:
tem
be
r,
20
02
10
:21
The NNI bit selects whether the first four bits of the ATM cell header are used
when determining whether a cell should be discarded because it is
Unassigned or one which is reserved for the Physical Layer. When set to logic
1 (default), the NNI format is used and first four bits of the ATM cell header
must be zeros for a cell to be indentified as an Unassigned or Physical Layer
cell. When set to logic 0, the UNI format is used and first four bits of the ATM
cell header are ignored.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
If a mixture of UNI and NNI cells pass through the Input Cell Interface, this
register bit should be set to a logic 1. Any Physical Layer UNI cells which
contain non-zero GFC fields shall be passed through the input FIFO and
subsequently rejected by the VC Identification algorithm. This results in a
increment of the Invalid Cell Count instead of the Physical Layer Cell Count.
______________________________________________________________________________________________
91
PM7322 RCMP-800
STANDARD PRODUCT
10
02
20
r,
tem
be
ep
9S
,1
ay
rsd
Default
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
hu
W
W
R/W
R/W
R/W
Function
EXTCA
ILEN[2]
ILEN[1]
ILEN[0]
Unused
Unused
Unused
Unused
Unused
Unused
Unused
ABORT
RESTART
EXTPHYID
DMAEN
EXTRST
nT
Type
R
R
R
R
io
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
:21
Register 0x10: Microprocessor Extract Buffer Control and Status
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
inv
ef
uo
fo
liv
ett
EXTRST:
The EXTRST bit is used to reset the extract FIFO. When EXTRST is set to
logic 0, the extract FIFO operates normally. When EXTRST is set to logic 1,
the extract FIFO is immediately emptied and ignores writes. The extract FIFO
remains empty and continues to ignore writes until a logic 0 is written to
EXTRST.
Do
wn
loa
de
db
yV
DMAEN:
The DMA enable (DMAEN) bit allows generation of a DMA request upon
reception of a cell in the extract buffer. If DMAEN is a logic 1, the DREQ
output is asserted when a complete cell has been written into the extract FIFO.
The first read of the Microprocessor Cell Data register after DREQ is asserted
returns the first word of the cell. Subsequent reads of the Microprocessor Cell
Data register return the remaining words in the cell. When the cell contents
are exhausted, the DREQ output is deasserted even if more cells are
contained in the cell buffer. This eases the identification of cell boundaries.
If DMAEN is a logic 0, the DREQ output is held deasserted.
______________________________________________________________________________________________
92
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
r,
20
02
10
:21
:53
EXTPHYID:
The extract physical link identification (EXTPHYID) bit allows the HEC byte of
each extracted cell to be overwritten with physical link identification associated
with the extracted cell, which is indicated on the IPHYID[4:0] inputs as the cell
is stored in the extract buffer. The IPHYID will consist of a 5-bit number in the
range 0 to 31, and will be right justified within the HEC byte of the cell. A value
of 0 represents PHY 1, a value of 1 represents PHY 2, etc. up to PHY 32.
tem
be
If EXTPHYID is set to a logic 1, the HEC byte will be overwritten.
If EXTPHYID is set to a logic 0, the HEC byte will be unchanged.
hu
rsd
ay
,1
9S
ep
RESTART:
The restart cell read (RESTART) bit resets the microprocessor cell read
pointer. If RESTART is set to a logic 1 during a cell read, the next word read
from the Microprocessor Cell Data register will be the first word of the current
cell. Subsequent reads from the Microprocessor Cell Data register return the
remaining words in the cell.
io
nT
RESTART is not readable and is cleared upon a read of the Microprocessor
Cell Data register (0x12).
uo
fo
liv
ett
ABORT:
The read abort (ABORT) bit allows the microprocessor to discard a cell without
reading the remaining contents. If ABORT is set to a logic 1, the current cell
being read is purged from the buffer and the DREQ output will be deasserted.
Do
wn
loa
de
db
yV
inv
ef
ABORT is not readable and is cleared upon a read of the Microprocessor Cell
Data register (0x12).
______________________________________________________________________________________________
93
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
tem
be
ep
9S
rsd
ay
,1
ILEN[2:0] = 111, cell length = 32 words
ILEN[2:0] = 110, cell length = 31 words
ILEN[2:0] = 101, cell length = 30 words
ILEN[2:0] = 100, cell length = 29 words
ILEN[2:0] = 011, cell length = 28 words
ILEN[2:0] = 010, cell length = 27 words
ILEN[2:0] = 001, RESERVED
ILEN[2:0] = 000, RESERVED
r,
20
02
10
:21
:53
ILEN[2:0]:
The input cell length (ILEN[2:0]) status bits represent the length of the
extracted cell currently being read. ILEN[2:0] will be valid throughout the
transfer of the cell. This status information may be used to control the number
of microprocessor reads for each particular cell, and would typically be read
just prior to reading the cell data. Since valid cell lengths range from 32 words
to 27 words, values of these bits are:
liv
ett
io
nT
hu
EXTCA:
The microprocessor cell available (EXTCA) status bit indicates that at least
one cell is present in the cell extract buffer. EXTCA is set to logic 1 when the
last word of a cell is received. EXTCA is cleared to logic 0 when the last word
in the buffer is read by the microprocessor. If multiple cells exist in the buffer,
then EXTCA will remain at logic 1 until the last word of the last cell is read.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
Assertion of the EXTCA status bit also results in a maskable interrupt.
______________________________________________________________________________________________
94
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
02
20
r,
tem
be
ep
9S
,1
ay
rsd
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
hu
Function
INSRDY
Unused
Unused
Unused
WRSOC
PHY[4]
PHY[3]
PHY[2]
PHY[1]
PHY[0]
OLEN[2]
OLEN[1]
OLEN[0]
UPHDRX
CRC10
INSRST
nT
Type
R
io
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
:21
Register 0x11: Microprocessor Insert Buffer Control and Status
inv
ef
uo
fo
liv
ett
INSRST:
The INSRST bit is used to reset the insert FIFO. When INSRST is set to logic
0, the insert FIFO operates normally. When INSRST is set to logic 1, the
insert FIFO is immediately emptied and ignores writes. The insert FIFO
remains empty and continues to ignore writes until a logic 0 is written to
INSRST.
db
yV
Any transfer from the insert FIFO currently in progress will be aborted.
Do
wn
loa
de
CRC10:
The CRC-10 enable (CRC10) bit forces the generation the Error Detection
Code (EDC) for cells written into the buffer. If CRC10 is set to logic 1 prior to
assembling the cell in the buffer, the last 10 bits of the cell are overwritten with
the standardized CRC-10 value calculated over the information field. In this
case, the 6 MSBs of the last word are overwriiten with zeros prior to CRC-10
generation, and hence 6 zeros will be transmiited along with the valid CRC-10.
UPHDRX:
The header translation (UPHDRX) bit controls the header processing of the
current cell written into the buffer.
______________________________________________________________________________________________
95
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
20
02
10
:21
:53
If UPHDRX was set to logic 1 prior to assembling the cell in the buffer, the
current cell has its header modified before presentation on the output bus.
The cell is also subject to policing, cell counting, multicasting and OAM
processing just as if had been received through the Input Cell Interface.
Therefore, the header information must correspond to a provisioned virtual
connection, or else the cell is discarded.
,1
9S
ep
tem
be
r,
If UPHDRX was a logic 0, the current cell is passed to the output without
modification, with the exception that appended bytes may be added or
stripped to ensure a correct cell length for the selected interface. The cell
need not belong to a provisioned connection. The cell is not policed and does
not affect the contents of Forward Monitoring cells and error counts. In other
words, besides presenting the cell on the Output Cell Interface, the RCMP-800
ignores the existence of the cell.
nT
hu
rsd
ay
OLEN[2:0]:
The OLEN[2:0] bits indicate the number of words in the inserted cell that the
microprocessor is about to write. Since valid cell lengths range from 32 words
to 27 words, values of these bits are:
inv
ef
uo
fo
liv
ett
io
OLEN[2:0] = 111, cell length = 32 words
OLEN[2:0] = 110, cell length = 31 words
OLEN[2:0] = 101, cell length = 30 words
OLEN[2:0] = 100, cell length = 29 words
OLEN[2:0] = 011, cell length = 28 words
OLEN[2:0] = 010, cell length = 27 words
OLEN[2:0] = 001, RESERVED
OLEN[2:0] = 000, RESERVED
Do
wn
loa
de
db
yV
PHY[4:0]:
The physical link identification bits (PHY[4:0]) determine the PHY association
of the current cell being written by the microprocessor. The state of PHY[4:0]
when the WRSOC is set selects the PHY device for that cell:
PHY[4:0]
00000
00001
00010
00011
...........
11111
Associated Source
PHY #1/single PHY
PHY #2
PHY #3
PHY #4
...........
PHY #32
______________________________________________________________________________________________
96
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
:21
:53
The interpretation of the PHY[4:0] bits depends on the state of the UPHDRX
bit. If UPHDRX is a logic 1, PHY[4:0] represents the input PHY the cell is
associated with and will be included in the search key used for VC
identification. If UPHDRX is a logic 0, PHY[4:0] is ignored.
9S
ep
tem
be
r,
20
02
WRSOC:
The write start of cell (WRSOC) bit must identify the first word of the current
cell that the microprocessor is writing. If WRSOC is a logic 1, the next word
written to the Microprocessor Cell Data register becomes the first word of the
cell. Subsequent writes to the Microprocessor Cell Data register fill the
remainder of the cell sequentially and the number of writes should correspond
to the programmed OLEN value. If WRSOC is set again before a complete
cell is written, the existing contents will be overwritten without transmission.
ay
,1
WRSOC is not readable.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
INSRDY:
The insert buffer ready (INSRDY) status bit indicates that the writeable cell
buffer is ready to accept another complete cell. It remains set for as long as
the buffer is not completely full. INSRDY is cleared upon the write of the first
word of a cell. Assertion of the INSRDY bit results in a maskable interrupt.
______________________________________________________________________________________________
97
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
02
20
r,
tem
be
ep
9S
,1
ay
rsd
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
hu
Function
MCD[15]
MCD[14]
MCD[13]
MCD[12]
MCD[11]
MCD[10]
MCD[9]
MCD[8]
MCD[7]
MCD[6]
MCD[5]
MCD[4]
MCD[3]
MCD[2]
MCD[1]
MCD[0]
nT
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
io
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
:21
Register 0x12: Microprocessor Cell Data
uo
fo
liv
ett
MCD[15:0]:
The MCD[15:0] contains the cell data destined to or read from the
Microprocessor Cell Buffer.
Do
wn
loa
de
db
yV
inv
ef
For the cell extract buffer, the EXTCA bit and associated maskable interrupt
indicate that a cell is available to be read. Alternately, the assertion of the
DREQ output (if enabled by the DMAEN bit) signals the presence of the cell.
Reads of this register return the words of the cell starting with the first. If
necessary, the read pointer can be reset to the start of the current cell by
setting the RESTART bit. Alternatively, the read pointer can be reset to the
start of the next cell by setting the ABORT bit.
In a polled mode, the INSRDY register bit indicates that the microprocessor
may write another cell. For interrupt driven systems, the INSRDYI interrupt
status bit and associated maskable interrupt indicate that a cell may be written.
______________________________________________________________________________________________
98
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
02
20
r,
tem
be
ep
9S
hu
GFC
COUNT
GPOLICE
PM
GPREPO
GVPIVCI
,1
BWDXLAT
ay
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
rsd
Function
UPURS
LB[1]
LB[0]
CSILOC[3]
CSILOC[2]
CSILOC[1]
CSILOC[0]
VCRAstuff
AUTORDI
nT
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
io
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
:21
Register 0x18: Cell Processor Configuration
ef
uo
fo
liv
ett
GVPIVCI:
If the GVPIVCI bit is a logic 1, VPI/VCI translation is globally enabled so ATM
VPI/VCI bytes can be replaced by the VC Table words at SRAM location
SA[19:16]=1000. If the GVPIVCI bit is a logic 0, the incoming VPI/VCI
combination passes through unaltered.
PM:
Do
wn
loa
de
db
yV
inv
GPREPO:
If the GPREPO bit is a logic 1, prepend/postpend is globally enabled so
appended bytes, HEC and UDF can be replaced by the VC Table words at
SRAM locations SA[19:16]=0011, 1000, 1001 and 1010. If the GPREPO bit is
a logic 0, the incoming bytes pass through unaltered with the exception of the
CLP bit. Note, however, that if the CSILOC[3:0] field is not 0x0, then the Cell
ID field will overwrite the selected pre/postpend byte or header byte.
If the PM bit is a logic 1, performance management is globally enabled. If the
PM bit is a logic 0, all performance management cells are ignored at endpoints and no statistics are maintained at intermediate points. When
performance management is disabled, no physical memory needs to be
provided at the SA[19:16]=1101, 1110 and 1111 locations.
______________________________________________________________________________________________
99
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
20
02
10
:21
:53
GPOLICE:
If the GPOLICE bit is a logic 1, cell rate policing is globally enabled on all
connections. (Policing can be disabled on a per-VC basis by clearing the
"Action[1:0]" field in the VC Table to zero.) If the GPOLICE bit is a logic 0, no
cell rate policing is performed and no physical memory needs to be provided at
the SA[19:16]=0100, 0101, 0110 and 0111 locations.
9S
ep
tem
be
r,
COUNT:
If the COUNT bit is a logic 1, per-VC counting is globally enabled. If the
COUNT bit is a logic 0, the CLP=0 and CLP=1 cell counts are not maintained
and no physical memory needs to be provided at the SA[19:16]=1011 and
1100 locations.
GFC:
nT
hu
rsd
ay
,1
The GFC bit determines if the GFC field in the ATM header is replaced or
passed through unaltered. If GFC is a logic 1, the GFC field in the incoming
cell is passed to the outgoing cell. If GFC is a logic 0, the GFC field is
replaced by contents of the VC Table. The GFC bit has no effect if the
connection belongs to a NNI.
fo
liv
ett
io
BWDXLAT:
If the BWDXLAT is a logic 1 and GVPIVCI is a logic 1, all backward generated
OAM cells have header translation performed on them. If BWDXLAT is a logic
0, the ingress VPI/VCI value is used in the header.
Do
wn
loa
de
db
yV
inv
ef
uo
AUTORDI:
The AUTORDI bit enables the generation of RDI cells while in an AIS alarm or
Continuity alarm state. If AUTORDI is a logic 1, an RDI cell is presented on
the Output Cell Interface immediately upon the reception of the first AIS cell at
a flow end-point and once a second thereafter until the AIS state is exited.
Likewise, if the CC_RDI bit in the VC table is set, RDI cells are sent once per
second if no user or Continuity Check cells have the received in the latest 5.5
+/- 0.5 (default) or 3.5 +/- 0.5 seconds. RDI cells can also be sent if the
"Send_RDI" bit in the VC Table Record is set.
VCRAstuff:
If the VCRAstuff bit is a logic 1, all cells routed to the Microprocessor Cell
Interface have the HEC and UDF bytes replaced with the VC Table index.
This enables the microprocessor to immediately determine the location of a
VC record in its data structure without having to perform its own binary search.
This feature is provided to enable high speed processing of cells.
______________________________________________________________________________________________
100
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
:21
:53
The EXTPHYID bit of the Microprocessor Extract Buffer Control and Status
register (0x10) takes precedence over the VCRAstuff bit. If the EXTPHYID is
set, the HEC byte location of extracted cells will contain the PHY identification
regardless of the state of VCRAstuff.
inv
ep
9S
,1
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
Definition
Disable overwrite
Appended byte 1
Appended byte 2
Appended byte 3
Appended byte 4
Appended byte 5
Appended byte 6
Appended byte 7
Appended byte 8
Appended byte 9
Appended byte 10
Header byte 1
Header byte 2
Header byte 3
Header byte 5
UDF
Do
wn
loa
de
db
yV
CSILOC[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
tem
be
r,
20
02
CSILOC[3:0]:
The CSILOC[3:0] bits determine which appended byte or header byte shall be
overwritten with a Cell ID field. This is used to quickly identify Forward RM,
Backward RM and generated Backward OAM cells. The CSILOC[3:0] field is
encoded as follows:
______________________________________________________________________________________________
101
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
:21
:53
LB[1:0]:
The LB[1:0] bits determine which loopback cells are copied to the
Microprocessor Cell Interface and which loopback cells are dropped (i.e. not
presented on the Output Cell Interface):
02
LB[1:0]
00
01
10
11
tem
be
r,
20
Do not copy; drop at flow end-points.
Do not copy; do not drop at flow end-points.
Copy and drop loopback cells at flow end-points.
Copy for all connections, drop at flow end-points.
nT
hu
rsd
ay
,1
9S
ep
UPURS:
The Microprocessor User Reason Symbol (UPURS) bit allows a causation
word to be prepended to cell extracted to the Microprocessor Cell Interface.
This allows an external microprocessor to immediately determine the reason a
cell was routed to the Microprocessor Cell Interface. The extracted cell length
will be one greater than the input cell length. Hence, this feature CANNOT be
used if the input cell length is 32-words.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
See the Microprocessor Interface description in the Functional Description
section for a description of the causation word.
______________________________________________________________________________________________
102
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
02
20
r,
tem
be
ep
9S
,1
ay
rsd
Default
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
hu
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
TAGAIS
AISRDIThresh
CCThresh
MERROR[4]
MERROR[3]
MERROR[2]
MERROR[1]
MERROR[0]
nT
Type
io
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
:21
Register 0x19: Performance Monitoring Configuration 1
inv
ef
uo
fo
liv
ett
MERROR[4:0]:
MERROR[4:0] is the binary representation of the threshold of BIP16 violations
(BIPV) per performance monitoring block required to declare a Severely
Errored Cell Block (SECB). BIPVs are not accumulated for SECBs. If
MERROR[4:0] is a binary zero, SECB is not declared as a result of excessive
BIPVs.
db
yV
This threshold applies to both received Forward Monitoring and Backward
Reporting cells.
Do
wn
loa
de
CCThresh:
The CCThresh bit controls the Continuity Check alarm threshold period, and
the period at which Continuity Check cells are generated. If CCThresh is a
logic 0, the CCalarm threshold period is 5.5 +/- 0.5 sec, and CC cells are
generated on two second boundaries. If CCThresh is a logic 1, the Continuity
Check alarm threshold period is 3.5 +/- 0.5 sec, and CC cells are generated on
one second boundaries.
______________________________________________________________________________________________
103
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
02
10
:21
:53
AISRDIThresh:
The AISRDIThresh bit controls the AIS and RDI alarm threshold periods. If
AISRDIThresh is a logic 0, the AIS and RDI alarm thresholds are 3.5 +/- 0.5
seconds. If AISRDIThresh is a logic 1, the AIS and RDI alarm thresholds are
2.5 +/- 0.5 sec.
ay
,1
9S
ep
tem
be
r,
20
TAGAIS:
The TAGAIS bit determines the coding of the Cell Status Information byte that
is inserted into the cell header or appended bytes for RCMP-800 generated
AIS cells. If TAGAIS is a logic 0, the AIS cell's Cell Status Information byte
contains a CELLID[2:0] encoded as 000 binary and the
BWDROUTINGTAG[7:3] is not inserted. If TAGAIS is a logic 1, AIS cell's Cell
Status Information byte contains a CELLID[2:0] encoded as 011 binary and
the BWDROUTINGTAG[7:3] is inserted into the 5 MSBs of the Cell Status
Information byte location.
nT
hu
rsd
Note that the TAGAIS does not affect the Cell Status Information byte for AIS
cells received through the Input Cell Interface or the Microprocessor Cell
Interface.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
The TAGAIS bit allows a more flexible treatment of generated AIS cells.
______________________________________________________________________________________________
104
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
02
20
r,
tem
be
ep
9S
,1
ay
rsd
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
hu
Function
MMISINS[7]
MMISINS[6]
MMISINS[5]
MMISINS[4]
MMISINS[3]
MMISINS[2]
MMISINS[1]
MMISINS[0]
MLOST[7]
MLOST[6]
MLOST[5]
MLOST[4]
MLOST[3]
MLOST[2]
MLOST[1]
MLOST[0]
nT
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
io
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
:21
Register 0x1A: Performance Monitoring Configuration 2
fo
liv
ett
The threshold given below applies to both received Forward Monitoring and
Backward Reporting cells.
db
yV
inv
ef
uo
MLOST[7:0]:
MLOST[7:0] is the binary representation of the threshold of lost cells per
performance monitoring block required to declare a Severely Errored Cell
Block (SECB). The number of lost cells is not counted for SECBs. If
MLOST[7:0] is a binary zero, SECB is not declared as a result of excessive
lost cells.
Do
wn
loa
de
MMISINS[7:0]:
MMISINS[7:0] is the binary representation of the threshold of misinserted cells
per performance monitoring block required to declare a Severely Errored Cell
Block (SECB). The number of misinserted cells is not counted for SECBs. If
MMISINS[7:0] is a binary zero, SECB is not declared as a result of excessive
lost cells.
______________________________________________________________________________________________
105
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
02
20
r,
tem
be
ep
9S
,1
ay
rsd
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
hu
Function
GCRA2[7]
GCRA2[6]
GCRA2[5]
GCRA2[4]
GCRA2[3]
GCRA2[2]
GCRA2[1]
GCRA2[0]
GCRA1[7]
GCRA1[6]
GCRA1[5]
GCRA1[4]
GCRA1[3]
GCRA1[2]
GCRA1[1]
GCRA1[0]
nT
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
io
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
:21
Register 0x1B: ABR Cell Rate Policing Configuration
uo
fo
liv
ett
It is important to note that this configuration register is only valid for ABR connections.
ABR connections are designated on a per-VC basis by the CONTYP bit in the
Configuration Field of the VC table.
db
FRM
0
BRM
1
0
1
OAM
0
1
GCRA1[0]GCRA1[1] GCRA1[2] GCRA1[3] GCRA1[4] GCRA1[5]
Do
wn
loa
de
Cell Type
CLP Bit
Reg Bit
yV
inv
ef
GCRA1[7:0]
The following table indicates upon which cell streams the first cell rate policing
instance (GCRA1) acts:
USER
0
GCRA1[6]
1
GCRA1[7]
A logic 1 written to any of the GCRA1[7:0] bits enables GCRA1 policing for
that particular cell stream. For example, to enable cell rate policing for GCRA1
on the user CLP=0+1 cell stream, the register configuration would be
GCRA2[7:0]=11000000. If GCRA1[7:0] = 00000000, the first GCRA policing
instance is globally disabled for ABR connections.
______________________________________________________________________________________________
106
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
0
BRM
1
0
OAM
0
1
1
02
FRM
20
GCRA2[0]GCRA2[1] GCRA2[2] GCRA2[3] GCRA2[4] GCRA2[5]
USER
0
GCRA2[6]
1
GCRA2[7]
r,
Cell Type
CLP Bit
Reg Bit
10
:21
:53
GCRA2[7:0]
The following table indicates upon which cell streams the second cell rate
policing instance (GCRA2) acts:
ep
tem
be
A logic 1 written to any of the GCRA2[7:0] bits enables GCRA2 policing for
that particular cell stream. If GCRA2[7:0] = 00000000, the second GCRA
policing instance is globally disabled for ABR connections.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
Note that Resource Management (RM) cells are considered distinct and
separate from OAM cells for the purposes of cell rate policing.
______________________________________________________________________________________________
107
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
02
20
r,
tem
be
ep
9S
,1
ay
rsd
Default
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
hu
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Unused
Unused
Unused
Unused
NCOUNT[1]
NCOUNT[0]
POLQNTM[1]
POLQNTM[0]
GCRA2[3]
GCRA2[2]
GCRA2[1]
GCRA2[0]
GCRA1[3]
GCRA1[2]
GCRA1[1]
GCRA1[0]
nT
Type
io
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
:21
Register 0x1C: VBR/CBR Cell Rate Policing Configuration
uo
fo
liv
ett
It is important to note that this configuration register is only valid for VBR/CBR
connections. VBR/CBR connections are designated on a per-VC basis by the
CONTYP bit in the Configuration Field of the VC table.
Do
wn
loa
de
db
Cell Type
CLP Bit
Reg Bit
yV
inv
ef
GCRA1[3:0]:
The GCRA1[3:0] bits determine the cell stream upon which the first cell rate
policing instance acts.
OAM
0
GCRA1[0]
USER
1
0
1
GCRA1[1] GCRA1[2] GCRA1[3]
A logic 1 written to any of the GCRA1[3:0] bits enables GCRA1 policing for
that particular cell stream. For example, to enable cell rate policing for GCRA1
on user CLP=0+1, the register configuration would be GCRA1[3:0] = 1100. If
GCRA1[3:0] = 0000, the first GCRA policing instance is globally disabled for
VBR/CBR connections.
Note that Resource Management (RM) cells are considered to be OAM cells
for the purposes of cell rate policing in VBR connections.
______________________________________________________________________________________________
108
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
1
GCRA2[1] GCRA2[2] GCRA2[3]
r,
GCRA2[0]
0
USER
02
CLP Bit
Reg Bit
OAM
20
Cell Type
0
1
10
:21
:53
GCRA2[3:0]:
The GCRA2[3:0] bits determine the cell stream upon which the second cell
rate policing instance acts.
ep
tem
be
A logic 1 written to any of the GCRA2[3:0] bits enables GCRA2 policing for
that particular cell stream. If GCRA2[3:0] = 0000, the second GCRA policing
instance is globally disabled for VBR/CBR connections.
,1
9S
Note that Resource Management (RM) cells are considered to be OAM cells
for the purposes cell rate policing in VBR connections.
hu
rsd
ay
POLQNTM[1:0]:
The POLQNTM[1:0] bits set the time quantum for the policing functions for
both ABR and VBR/CBR connections.
SYSCLK Period
1 times SYSCLK period.
2 times SYSCLK period
4 times SYSCLK period
8 times SYSCLK period
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
POLQNTM[1:0]
00
01
10
11
______________________________________________________________________________________________
109
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
:21
:53
NCOUNT[1:0]:
The NCOUNT[1:0] bits determine how the non-compliant cell counts of the VC
table are defined. NCOUNT[1:0] affects both ABR and non-ABR connections.
The following definitions are user programmable:
ep
tem
be
r,
20
02
non-compliant count #2
definition
non-compliant
CLP=1 cells.
dropped
CLP=1 cells.
Cells
9S
non-compliant count #1
definition
00
non-compliant
CLP=0 cells.
01
dropped
CLP=0 cells.
10
Cells which
are non-compliant
compliant with
with GCRA#1
ay
,1
NCOUNT[1:0]
Cells which
are non-compliant
with GCRA#1
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
11
GCRA#1 which are
non-compliant with
GCRA#2.
Cells which
are non-compliant
with GCRA#2
______________________________________________________________________________________________
110
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
02
20
r,
tem
be
ep
9S
,1
ay
rsd
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
nT
hu
Type
Function
R/W
CRC10toUP
R/W DROPCRC10
R/W ACTDEtoOCIF
R/W
CCtoUP
R/W DROPINVPTIVCI
R/W
DROPBRM
R/W
DROPFRM
R/W BADVCtoUP
R/W
BRMtoUP
R/W
FRMtoUP
R/W ACTDEtoUP
R/W INVPTIVCItoUP
R/W UNDEFtoUP
R/W
RDItoUP
R/W
AIStoUP
R/W
PMtoUP
io
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
:21
Register 0x1D: Routing Configuration
ef
uo
fo
liv
ett
PMtoUP:
If PMtoUP is a logic 1, all Performance Management OAM cells are copied to
the Microprocessor Cell Interface. Regardless of the state of this bit, all
Performance Management OAM cells are passed to the Output Cell Interface
if the RCMP-800 is not an end point for the connection.
Do
wn
loa
de
db
yV
inv
AIStoUP:
If the AIStoUP bit is a logic 1, all AIS cells are copied to the Microprocessor
Cell Interface. Regardless of the state of this bit, all AIS cells are passed to
the Output Cell Interface if the RCMP-800 is not an end point for the
connection.
RDItoUP:
If the RDItoUP bit is a logic 1, all RDI cells are copied to the Microprocessor
Cell Interface. Regardless of the state of this bit, all RDI cells are passed to
the Output Cell Interface if the RCMP-800 is not an end point for the
connection.
______________________________________________________________________________________________
111
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
20
02
10
:21
:53
UNDEFtoUP:
If the UNDEFtoUP bit is a logic 1, all OAM cells with an undefined OAM Type
or Function Type value are copied to the Microprocessor Cell Interface.
Regardless of the state of this bit, all OAM cells with an undefined OAM Type
or Function Type value are passed to the Output Cell Interface if the RCMP800 is not an end point for the connection.
9S
ep
tem
be
r,
INVPTIVCItoUP:
If the INVPTIVCItoUP bit is a logic 1, all VCC cells with an invalid PTI field
(PTI=111) and all VPC cells with an invalid VCI field (VCI 7 through 15) are
copied to the Microprocessor Cell Interface. The DROPINVPTIVCI register bit
determines whether cells with invalid PTI or VCI fields are passed to the
Output Cell Interface.
nT
hu
rsd
ay
,1
ACTDEtoUP:
If the ACTDEtoUP bit is a logic 1, all activate/deactivate OAM cells are copied
to the Microprocessor Cell Interface. Regardless of the state of this bit, all
activate/deactivate cells are passed to the Output Cell Interface if the RCMP800 is not an end point for the connection.
ef
uo
fo
liv
ett
io
FRMtoUP:
If the FRMtoUP bit is a logic 1, all forward Resource Management (RM) cells
are copied to the Microprocessor Cell Interface. Forward RM cells are
identified by zero in the DIR bit position in conjunction with PTI=110 for VC-RM
cells and by VCI=6 for VP-RM cells. If the VPRMSEL bit of the CRAM
Configuration register is a logic 1, VP-RM cells are further qualified by
PTI=110.
Do
wn
loa
de
db
yV
inv
BRMtoUP:
If the BRMtoUP bit is a logic 1, all backward Resource Management (RM) cells
are copied to the Microprocessor Cell Interface. Backward RM cells are
identified by a one in the DIR bit position in conjunction with PTI=110 for VCRM cells and VCI=6 for VP-RM cells. If the VPRMSEL bit of the CRAM
Configuration register is a logic 1, VP-RM cells are further qualified by
PTI=110.
BADVCtoUP:
If the BADVCtoUP bit is a logic 1, all cells with an unprovisioned VPI/VCI are
routed to the Microprocessor Cell Interface for header logging.
______________________________________________________________________________________________
112
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
02
10
:21
:53
DROPFRM:
If the DROPFRM bit is a logic 1, all forward RM cells are dropped (i.e. not
passed to the Output Cell Interface). Regardless of the state of this bit,
forward RM cells may be routed to the Microprocessor Cell Interface if the
FRMtoUP bit is set.
ep
tem
be
r,
20
DROPBRM:
If the DROPBRM bit is a logic 1, all backward RM cells are dropped (i.e. not
passed to the Output Cell Interface). Regardless of the state of this bit,
backward RM cells may be routed to the Microprocessor Cell Interface if the
BRMtoUP bit is set.
hu
rsd
ay
,1
9S
DROPINVPTIVCI:
The DROPINVPTIVCI bit controls the dropping of VCC cells with an invalid
PTI and all VPC cells with an invalid VCI field. If DROPINVPTIVCI is a logic 1,
all VCC cells with PTI='111' and all VPC cells with a VCI between7 through 15,
inclusive, are not routed to the Output Cell Interface. If DROPINVPTIVCI is a
logic 0, these cells are passed transparently.
ett
io
nT
CCtoUP:
If the CCtoUP bit is a logic 1, all Continuity Check cells are copied to the
Microprocessor Cell Interface.
yV
inv
ef
uo
fo
liv
ACTDEtoOCIF:
If the ACTDEtoOCIF bit is a logic 1, all Activate/Deactivate cells are routed to
the Output Cell Interface. If ACTDEtoOCIF is 0, then at flow end-points, all
Activate/Deactivate cells are dropped. Regardless of the state of this bit, all
Activate/Deactivate cells are presented by the Output Cell Interface if the
RCMP-800 is not a flow end-point.
Do
wn
loa
de
db
DROPCRC10:
If the DROPCRC10 bit is a logic 1, all OAM cells with an errored CRC-10 are
dropped (i.e. not passed to the Output Cell Interface). Regardless of the state
of this bit, if the RCMP-800 is a flow end-point, all OAM cells with an errored
CRC-10 are dropped.
CRC10toUP:
If the CRC10toUP bit is a logic 1, all OAM cells with an errored CRC-10 are
copied to the Microprocessor Cell Interface. Regardless of the state of this bit,
if the RCMP-800 is a flow end-point, all OAM cells with an errored CRC-10 are
dropped (i.e. not passed to the output Output Cell Interface). If the RCMP-800
is not an OAM end flow then the state of the DROPCRC10 bit determines
whether or not the cell is passed to the Output Cell Interface.
______________________________________________________________________________________________
113
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
02
20
r,
tem
be
ep
hu
DISVERIFY
LIMITMC
CNTUNDEF
9S
DROPCRCRM
,1
R/W
R/W
R/W
R/W
R/W
R/W
Default
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
ay
Function
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
rsd
Type
nT
CNTINVPTIVCI
VPRMSEL
io
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
:21
Register 0x20: CRAM Configuration
yV
inv
ef
uo
fo
liv
ett
VPRMSEL:
The VPRMSEL bit controls the identification of the VPC Resource
Management (VP-RM) cells. If VPRMSEL is a logic 0, VP-RM cells are
identified by a VCI=6; the PTI field is ignored. If VPRMSEL is a logic 1, VPRM cells are identified by a VCI=6 and a PTI=110. If the PTI field is not equal
to 110, the cell is flagged is invalid and optionally can be routed to the
Microprocessor Cell Interface.
Do
wn
loa
de
db
CNTINVPTIVCI:
The CNTINVPTIVCI controls the counting of cells with invalid PTI or VCI
values. If CNTINVPTIVCI is a logic 1, all VCC cells with PTI='111' and all VPC
cells with VCI values between 7 and 15, inclusive, result in an increment of the
Invalid Cell Count.
CNTUNDEF:
If the CNTUNDEF bit is a logic 1, OAM cells with undefined OAM Type and
Function Type fields result in an increment of the Errored OAM Cell Count
register. If CNTUNDEF is a logic 0, only CRC-10 errors result in an increment;
received OAM cells with undefined Type and Function fields will result in an
increment of the Vaild OAM Cell Count register.
______________________________________________________________________________________________
114
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
tem
be
r,
20
02
10
:21
:53
LIMITMC:
If this bit is a '1' then the RCMP-800 limits the maximum size of a multicast set
to 63 cells. If this bit is a '0' then a multicast set can be arbitrarily large. Setting
this bit to a '1' causes to the RCMP-800 stop processing a multicast linked list
after the 63rd multicast cell and the set the SRCHERRI register bit. This
enables the RCMP-800 to exit a multicast linked list which may have been
improperly constructed and contains an endless loop. If it desired to support
multicast sets greater then 63 cells the LIMITMC bit should set to a '0'.
9S
ep
DISVERIFY:
The Disable Verify bit controls whether or not the secondary search key is
used as part of the cell confirmation step.
nT
hu
rsd
ay
,1
If this bit is a logic 1 then, after the VC search is complete, the Secondary
search key IS NOT compared to the SA[19:16]=0010 word of the candidate
VC Table Record. All cells with a non-null Primary Key will be considered part
of a valid connection. This bit will typically be set high if the cell is identified
completely using only the Primary Key or if unprovisioned cells are not
possible.
liv
ett
io
If this bit is a logic 0, the binary search is completed with the "confirmation
step" which compares the secondary key to the SA[19:16]=0010 word of the
candidate VC Table Record.
ef
uo
fo
DROPCRCRM:
If DROPCRCRM is a logic 1, the Resource Management (RM) cells which
have a CRC-10 error are dropped.
db
yV
inv
If DROPCRCRM is a logic 0, the RM cells are transparently passed regardless
of whether the CRC10 is in error.
Do
wn
loa
de
Regardless of the DROPCRCRM bit, RM cells with CRC10 errors are
indicated via the INVALI bit of the Master Interrupt Status #1 register (0x02).
______________________________________________________________________________________________
115
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
02
20
r,
tem
be
ep
9S
,1
ay
rsd
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
hu
Function
SA[15]
SA[14]
SA[13]
SA[12]
SA[11]
SA[10]
SA[9]
SA[8]
SA[7]
SA[6]
SA[5]
SA[4]
SA[3]
SA[2]
SA[1]
SA[0]
nT
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
io
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
:21
Register 0x21: External RAM Address (LSB)
fo
liv
ett
This register is used in conjunction with the External RAM Address (MSB) and
Access Control register to access the external SRAM.
Do
wn
loa
de
db
yV
inv
ef
uo
SA[15:0]:
This register holds the 16 least significant bits of the external SRAM address
used for µP accesses. It identifies the desired VC Table Record.
______________________________________________________________________________________________
116
PM7322 RCMP-800
STANDARD PRODUCT
:53
10
02
20
r,
tem
be
ep
9S
,1
ay
R/W
R/W
R/W
R/W
rsd
R/W
R/W
R/W
R/W
R/W
Default
0
X
X
0
0
0
0
0
X
X
X
X
0
0
0
0
hu
Function
RWB
BUSY
Unused
WM[4]
WM[3]
WM[2]
WM[1]
WM[0]
Unused
Unused
Unused
Unused
SA[19]
SA[18]
SA[17]
SA[16]
nT
Type
R/W
R
io
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
:21
Register 0x22: External RAM Address (MSB) and Access Control
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
ef
uo
fo
liv
ett
This register allows the µP to access the external SRAM location addressed by the
SA[19:0] bits and perform the operation specified by the RWB bit. Writing to this
register with a valid address and RWB bit initiates a µP access request cycle. The
contents of the External RAM Address (LSB) register should be set to the desired VC
Table Record before this register is written.
Do
wn
loa
de
db
yV
inv
SA[19:16]:
The SA[19:16] bits represent the four most significant bits of the external
SRAM address used for µP accesses.
______________________________________________________________________________________________
117
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
tem
be
r,
20
02
10
:21
:53
WM[4:0]:
The write mask (WM[4:0]) is used to select which words of the SRAM data
SD[39:0] will be written to during a write operation. If any of WM[4:0] are a '1'
during a write operation the RCMP performs a read-write-back operation when
a write is requested. This is used to have the RCMP alter only selected SRAM
fields. When a write is requested the RCMP first reads the data held at
SA[19:0] (registers 0x21 and 0x22) then, as per the contents of WM[4:0], the
RCMP selectively writes the data held in the SD[39:0] registers (registers 0x23
to 0x25) or writes back the data just read.
,1
9S
ep
If WM[0] is a '1', when a write is requested, the RCMP retains the contents of
SD[7:0] during the write operation. Similarly setting, WM[4], WM[3], WM[2], or
WM[1] high cause the RCMP to retain the contents of SD[39:32], SD[31:24],
SD[23:16], or SD[15:8], respectively.
rsd
ay
If WM[4:0] = "00000" then no fields are masked during the write.
fo
liv
ett
io
nT
hu
BUSY:
The BUSY bit is high while a µP access request to the external SRAM is
pending. The BUSY bit goes low after the access has been completed. This
register should be polled until the BUSY bit goes low before another µP
access request is initiated. A µP access request is typically completed within
37 SYSCLK cycles. If the STANDBY bit in the Master Configuration is a logic
1, the access time is reduced to less than 5 SYSCLK cycles.
uo
RWB:
db
yV
inv
ef
The RWB bit selects the operation to be performed on the addressed SRAM
location: when RWB is set to a logic 1, a read from the external SRAM is
requested; when RWB is set to a logic 0, a write to the external SRAM is
requested.
Do
wn
loa
de
After reading SRAM address SA[19:16] = {1111, 1110, 1100 or 1011} the
RCMP-800 automatically clears (writes all zeros) the location read. A read to
these addresses causes the RCMP-800 to perform two SSRAM accesses.
First, the read requested. Next, a write of all zeros to the SSRAM location just
read.
Similarly, after reading SRAM address SA[19:16] = 0111, the RCMP-800
clears bits 31:0 of the location just read. Bits 39:32 of the address just read are
preserved.
______________________________________________________________________________________________
118
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
02
20
r,
tem
be
ep
9S
,1
ay
rsd
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
hu
Function
SD[15]
SD[14]
SD[13]
SD[12]
SD[11]
SD[10]
SD[9]
SD[8]
SD[7]
SD[6]
SD[5]
SD[4]
SD[3]
SD[2]
SD[1]
SD[0]
nT
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ett
io
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
:21
Register 0x23: External RAM Data (LSB)
yV
inv
ef
fo
uo
Function
SD[31]
SD[30]
SD[29]
SD[28]
SD[27]
SD[26]
SD[25]
SD[24]
SD[23]
SD[22]
SD[21]
SD[20]
SD[19]
SD[18]
SD[17]
SD[16]
db
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Do
wn
loa
de
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
liv
Register 0x24: External RAM Data
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
______________________________________________________________________________________________
119
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
10
02
20
r,
tem
be
ep
9S
,1
ay
rsd
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
hu
Function
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
SD[39]
SD[38]
SD[37]
SD[36]
SD[35]
SD[34]
SD[33]
SD[32]
nT
Type
io
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
:53
Register 0x25: External RAM Data (MSB)
db
yV
inv
ef
uo
fo
liv
ett
The External RAM Data registers contain either the data to be written into the
external SRAM when a write request is initiated or the data read from the external
SRAM when a read request has completed. If data is to be written to the external
SRAM, these Data registers must be written before the target location's address and
RWB=0 is written into the External RAM Address (MSB) and Access Control register,
initiating the access. If data is to be read from the external SRAM, only the target
location's address and RWB=1 is written into the External RAM Address (MSB) and
Access Control register, initiating the request. Within 37 SYSCLK cycles, these
registers will contain the requested data word.
Do
wn
loa
de
Note, these are not typical read/write registers. When performing a Read operation,
the data in these registers represents the external SRAM data which were read from
a previous external SRAM read operation.
______________________________________________________________________________________________
120
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
02
20
r,
tem
be
ep
9S
,1
ay
rsd
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
hu
Function
MAX[15]
MAX[14]
MAX[13]
MAX[12]
MAX[11]
MAX[10]
MAX[9]
MAX[8]
MAX[7]
MAX[6]
MAX[5]
MAX[4]
MAX[3]
MAX[2]
MAX[1]
MAX[0]
nT
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
io
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
:21
Register 0x26: Maximum VC Table Index
db
yV
inv
ef
uo
fo
liv
ett
MAX[15:0]
The MAX[15:0] bits represent the current maximum VC Table index (SA[15:0]).
It is used by the one second servicing algorithm as the first VC Table Record
serviced; the index is decremented with each subsequent connection serviced.
An accurate value in this location maximizes the efficiency of the RCMP-800.
Fixing this register to all ones guarantees all connections will be serviced each
second. Do not set MAX[15:0] to a value greater than supported by the depth
of SRAM provisioned.
Do
wn
loa
de
Setting MAX[15:0] to all zeros effectively disables (for all locations except
location SA[15:0] = 0x0000) the generation of AIS, RDI and Continuity Check
cells and disables the clearing of AIS, RDI and Continuity Check alarms.
______________________________________________________________________________________________
121
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
02
20
r,
tem
be
ep
9S
,1
ay
rsd
R/W
R/W
R/W
Default
X
X
X
X
X
0
0
0
X
X
X
X
X
X
X
X
hu
Function
Unused
Unused
Unused
Unused
Unused
PHY[2]
PHY[1]
PHY[0]
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
nT
Type
io
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
:21
Register 0x27: Search Key Construction
yV
1
X
Reserved
-
1
0
1
5
32
1
0
0
4
16
0
1
1
3
8
0
1
0
2
4
0
0
1
1
2
0
0
0
0 (single PHY interface)
1
1
PHY[1]
db
PHY[0]
Do
wn
loa
de
PHY[2]
inv
ef
uo
fo
liv
ett
PHY[2:0]:
The contents of PHY[2:0] determine the number of PHY ID bits in the Primary
Search Key. If less than all five PHY address lines should be considered
during the key search (as in the case where only a single PHY interface is
used) then PHY[2:0] must be programmed with the values below:
Number of PHY ID bits in Number of
Primary Key
Supported PHYs
______________________________________________________________________________________________
122
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
02
20
r,
tem
be
ep
9S
,1
io
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ay
R/W
R/W
R/W
R/W
R/W
Default
X
X
X
0
0
0
0
0
X
0
0
0
0
0
0
0
rsd
Function
Unused
Unused
Unused
LA[4]
LA[3]
LA[2]
LA[1]
LA[0]
Unused
SA[6]
SA[5]
SA[4]
SA[3]
SA[2]
SA[1]
SA[0]
hu
Type
nT
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
:21
Register 0x28: Field A Location and Length
liv
ett
This register holds the starting location and length of Field A within the Routing Word.
ef
uo
fo
SA[6:0]:
SA[6:0] form the binary address of the MSB of the Field A within the Routing
Word. SA[6] is the MSB of the address.
yV
inv
LA[4:0]:
Do
wn
loa
de
db
LA[4:0] gives the length of the Field A in bits. The length is stored in LA[4:0] as
binary value with LA[4] as MSB. If no Field A is to be used then LA[4:0] should
be set to '00000'. Valid values for this field range from '00000' to '10000.' As a
programming example: If a 10 bit Field A should be extracted starting at the
120th bit of the Routing Word, we would set LA ='01010' (length = 10) and
SA='1110111' (starting address = 119), i.e. write 0x0A77 to 0x28.
______________________________________________________________________________________________
123
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
02
20
r,
tem
be
ep
9S
,1
io
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ay
R/W
R/W
R/W
R/W
Default
X
X
X
X
0
0
0
0
X
0
0
0
0
0
0
0
rsd
Function
Unused
Unused
Unused
Unused
LB[3]
LB[2]
LB[1]
LB[0]
Unused
SB[6]
SB[5]
SB[4]
SB[3]
SB[2]
SB[1]
SB[0]
hu
Type
nT
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
:21
Register 0x29: Field B Location and Length
liv
ett
This register holds the starting location and length of Field B within the Routing Word.
ef
uo
fo
SB[6:0]:
SB[6:0] form the binary address of the MSB of the Field B within the Routing
Word. SB[6] is the MSB of the address.
yV
inv
LB[3:0]:
Do
wn
loa
de
db
LB[3:0] gives the length of the Field B in bits. The length is stored in LB[3:0] as
binary value with LB[3] as MSB. If no Field B is to be used then LB[3:0] should
be set to '0000'. Valid values for this field range from '0000' to '1011.' As a
programming example: If a 10 bit Field B should be extracted starting at the
120th bit of the Routing Word, we would set LB ='1010' (length = 10) and
SB0='1110111' (starting address = 119), i.e. write 0x0A77 to 0x29.
______________________________________________________________________________________________
124
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
02
20
r,
tem
be
ep
9S
,1
ay
rsd
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
hu
R
R
R
R
R
R
Function
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
DROPCH
INVALCH
OAMERRCH
OAMCH
XFER
OVR
nT
Type
io
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
:21
Register 0x30: Counter Status
uo
fo
liv
ett
This register contains status information indicating when counter data has been
transferred into the holding registers and indicating whether the holding registers have
been overrun. It also indicates if the any of the counts are non-zero.
yV
inv
ef
DROPCH:
The DROPCH bit is set to logic 1 if the Count of Cells Dropped Due to
Congestion is a non-zero value.
Do
wn
loa
de
db
INVALCH:
The INVALCH bit is set to logic 1 if the Invalid Cell Count register contains a
non-zero value.
OAMERRCH:
The OAMERRCH bit is set to logic 1 if the Errored OAM Cell Count register
contains a non-zero value.
OAMCH:
The OAMCH bit is set to logic 1 if the Valid OAM Cell Count register contains a
non-zero value.
______________________________________________________________________________________________
125
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:53
XFER:
tem
be
r,
20
02
10
:21
The XFER bit indicates that a transfer of counter data (i.e. data for one or
more of the Dropped Cells Due to Congestion register, Invalid Cell Count
register, Errored OAM Cell Count register and Valid OAM Cell Count register)
has occurred. A logic 1 in this bit position indicates that a latch request,
initiated by writing to one of the counter register locations, was received and a
transfer of the counter values has occurred. A logic 0 indicates that no transfer
has occurred. The XFER bit is cleared (acknowledged) by reading this
register. The XFERI bit of the Master Interrupt Status #1 is set when the
XFER bit is asserted.
ep
OVR:
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
The OVR bit is the overrun status of the holding registers. A logic 1 in this bit
position indicates that a previous transfer (indicated by XFER being logic 1)
has not been acknowledged before the next transfer clock has been issued
and that the contents of the holding registers have been overwritten. A logic 0
indicates that no overrun has occurred. The OVR bit is cleared by reading this
register. The XFERI bit of the Master Interrupt Status #1 is set when the OVR
bit is asserted.
______________________________________________________________________________________________
126
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
02
20
r,
tem
be
ep
9S
,1
ay
rsd
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
hu
Function
OAM[15]
OAM[14]
OAM[13]
OAM[12]
OAM[11]
OAM[10]
OAM[9]
OAM[8]
OAM[7]
OAM[6]
OAM[5]
OAM[4]
OAM[3]
OAM[2]
OAM[1]
OAM[0]
nT
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
io
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
:21
Register 0x31: Valid OAM Cell Count
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
OAM[15:0]:
The OAM[15:0] bits represent the number of valid OAM cells that have been
received since the last time the count was transferred. The count is
transferred by writing to either address 0x00, 0x31, 0x32, 0x33 or 0x34. Such
a write transfers the internally accumulated OAM cell count to this register
within three SYSCLK cycles and simultaneously resets the internal counter to
begin a new cycle of error accumulation. This transfer and reset is carried out
in a manner that ensures that coincident events are not lost.
The determination of a valid OAM cell is dependent on the state of the
CNTUNDEF bit of the CRAM Configuration register (register 0x20). If the
CNTUNDEF bit is a logic 1, then OAM cells with a correct CRC-10, but an
undefined Type of Function field will be counted as vaild OAM cells.
______________________________________________________________________________________________
127
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
02
20
r,
tem
be
ep
9S
,1
ay
rsd
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
hu
Function
OAMERR[15]
OAMERR[14]
OAMERR[13]
OAMERR[12]
OAMERR[11]
OAMERR[10]
OAMERR[9]
OAMERR[8]
OAMERR[7]
OAMERR[6]
OAMERR[5]
OAMERR[4]
OAMERR[3]
OAMERR[2]
OAMERR[1]
OAMERR[0]
nT
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
liv
ett
io
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
:21
Register 0x32: Errored OAM Cell Count
Do
wn
loa
de
db
yV
inv
ef
uo
fo
OAMERR[15:0]:
The OAMERR[15:0] bits represent the number of errored OAM cells that have
been received since the last time the count was transferred. The count
includes cells with an incorrect CRC-10, or cells with an undefined OAM Type
or Function Type field, depending on the state of the CNTUNDEF bit in the
CRAM Configuration register (register 0x20). The count is transferred by
writing to either address 0x00, 0x31, 0x32, 0x33 or 0x34. Such a write
transfers the internally accumulated errored OAM cell count to this register
within three SYSCLK cycles and simultaneously resets the internal counter to
begin a new cycle of error accumulation. This transfer and reset is carried out
in a manner that ensures that coincident events are not lost.
______________________________________________________________________________________________
128
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
02
20
r,
tem
be
ep
9S
,1
ay
rsd
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
hu
Function
INVAL[15]
INVAL[14]
INVAL[13]
INVAL[12]
INVAL[11]
INVAL[10]
INVAL[9]
INVAL[8]
INVAL[7]
INVAL[6]
INVAL[5]
INVAL[4]
INVAL[3]
INVAL[2]
INVAL[1]
INVAL[0]
nT
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
io
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
:21
Register 0x33: Invalid Cell Count
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
INVAL[15:0]:
The INVAL[15:0] bits represent the number of cells with invalid headers that
have been received since the last time the count was transferred. The count
includes cells with an unprovisioned VPI/VCI or with undefined PTI values
(optional). The count is transferred by writing to either address 0x00, 0x31,
0x32, 0x33 or 0x34. Such a write transfers the internally accumulated invalid
cell count to this register within three SYSCLK cycles and simultaneously
resets the internal counter to begin a new cycle of error accumulation. This
transfer and reset is carried out in a manner that ensures that coincident
events are not lost.
______________________________________________________________________________________________
129
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
02
20
r,
tem
be
ep
9S
,1
ay
rsd
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
hu
Function
DROP[15]
DROP[14]
DROP[13]
DROP[12]
DROP[11]
DROP[10]
DROP[9]
DROP[8]
DROP[7]
DROP[6]
DROP[5]
DROP[4]
DROP[3]
DROP[2]
DROP[1]
DROP[0]
nT
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
io
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
:21
Register 0x34: Count of Cells Dropped Due to Congestion
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
DROP[15:0]:
The DROP[15:0] bits represent the number of cells that have been discarded
due to an assertion of the CONG input since the last time the count was
transferred. The count is transferred by writing to either address 0x00, 0x31,
0x32, 0x33 or 0x34. Such a write transfers the internally accumulated dropped
cell count to this register within three SYSCLK cycles and simultaneously
resets the internal counter to begin a new cycle of error accumulation. This
transfer and reset is carried out in a manner that ensures that coincident
events are not lost.
______________________________________________________________________________________________
130
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
02
20
r,
tem
be
ep
9S
,1
ay
rsd
Default
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
hu
Function
HECUDF
OCAINV
CELLPOST[3]
CELLPOST[2]
CELLPOST[1]
CELLPOST[0]
CELLLEN[3]
CELLLEN[2]
CELLLEN[1]
CELLLEN[0]
OBYTEPRTY
OPTYP
Reserved
Reserved
OCALEVEL0
FIFORST
nT
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
io
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
:21
Register 0x38: Output Cell FIFO Configuration
ef
uo
fo
liv
ett
FIFORST:
The FIFORST bit is used to reset the four cell output FIFO. When FIFORST is
set to logic 0, the FIFO operates normally. When FIFORST is set to logic 1,
the FIFO is immediately emptied and ignores writes. The FIFO remains empty
and continues to ignore writes until a logic 0 is written to FIFORST.
yV
inv
It is recommended that, whenever any other bit in this register is changed,
FIFORST be set to logic one upon the change and set to logic zero after.
Do
wn
loa
de
db
The FULLI bit of the Master Interrupt Status #1 register (0x01) may become a
logic 1 as a result of setting the FIFORST bit. With the output FIFO reset, it is
unable to accept any cells, which is the same immediate symptom as a full
buffer.
OCALEVEL0:
The OCALEVEL0 bit determines what the OCA output indicates when it
transitions inactive. When OCALEVEL0 is set to logic 1, a deassertion of the
OCA[1] outputs indicate that the output FIFO is empty. When OCALEVEL0 is
set to logic 0, a deassertion of the OCA output indicates that the output FIFO
is near empty and contains only four words.
______________________________________________________________________________________________
131
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
02
10
:21
:53
OPTYP:
The OPTYP bit selects even or odd parity for outputs OPRTY[1:0]. When set
to logic 1, output OPRTY[1] is the even parity bit for outputs ODAT[15:8] and
output OPRTY[0] is the even parity bit for outputs ODAT[7:0]. When set to
logic 0, OPRTY[1:0] are the odd parity bits for outputs ODAT[15:0].
rsd
ay
,1
9S
ep
tem
be
r,
20
OBYTEPRTY:
The output byte parity, OBYTEPRTY, mode bit selects between byte and word
parity mode for the OPRTY[1:0] outputs. When the OBYTEPRTY bit is set to
logic one, byte parity mode is selected, otherwise, word parity mode is
selected. In byte parity mode, OPRTY[1] is the (odd or even) parity bit for the
ODAT[15:8] outputs, and OPRTY[0] is the parity bit for the ODAT[7:0] outputs.
In word parity mode, OPRTY[1] is the (odd or even) parity bit calculated for all
16 ODAT[15:0] outputs, and OPRTY[0] is held low. Word parity mode can
only be selected when the OBUS8 input is low (i.e., the 16-bit FIFO interface is
selected).
nT
hu
CELLLEN[3:0]:
The CELLLEN[3:0] bits determine the number of words in the output cell.
fo
liv
ett
io
When OBUS8 is a logic 1, the binary CELLLEN[3:0] value is the number of
bytes appended to the basic 53 byte ATM cell. The maximum cell length is 63
bytes; therefore, a CELLLEN[3:0] greater than 10 decimal results in 10
appended bytes.
yV
inv
ef
uo
When OBUS8 is a logic 0, the binary CELLLEN[3:0] value is the number of
words appended to the basic 27 word ATM cell. The maximum cell length is
32 words; therefore, a CELLLEN[3:0] greater than 5 decimal results in 5
appended bytes.
Do
wn
loa
de
db
CELLPOST[3:0]:
The CELLPOST[3:0] bits determine the number of words in the output cell
post-pend. The numerical difference between CELLLEN[3:0] and
CELLPOST[3:0] represents the number of words in the pre-pend. It is
inappropriate that CELLPOST[3:0] exceed CELLLEN[3:0].
When OBUS8 is a logic 1, the binary CELLPOST[3:0] value is the number of
bytes post-pended to the basic 53 byte ATM cell. When OBUS8 is a logic 0,
the binary CELLPOST[3:0] value is the number of words post-pended to the
basic 27 word ATM cell.
OCAINV:
The OCAINV bit selects the active polarity of the OCA signal. The default
______________________________________________________________________________________________
132
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
:21
:53
configuration selects OCA to be active high, indicating that a cell is available
when high. When OCAINV is set to logic one, the OCA signal becomes active
low. If the state of the OCAINV bit has been changed, the output FIFO must
be reset via the FIFORST bit in order to properly initialize the OCA output.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
tem
be
r,
20
02
HECUDF:
The HECUDF bit determines whether or not the HEC/UDF octets are included
in cells transferred over the output cell interface. When set to logic 1 (default),
the HEC and UDF octets are included. When set to logic 0, these octets are
omitted, i.e., if BUS8 is logic 0, the third word of the 27-word ATM cell is
omitted and a 26-word cell (plus appended words) is transferred. If BUS8 is
logic 1, the fifth octet of the 53-octet ATM cell is omitted and a 52-octet cell
(plus appended octets) is transferred.
______________________________________________________________________________________________
133
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
02
20
r,
tem
be
ep
9S
,1
ay
rsd
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
hu
Function
OCELL[15]
OCELL[14]
OCELL[13]
OCELL[12]
OCELL[11]
OCELL[10]
OCELL[9]
OCELL[8]
OCELL[7]
OCELL[6]
OCELL[5]
OCELL[4]
OCELL[3]
OCELL[2]
OCELL[1]
OCELL[0]
nT
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
:21
Register 0x3A: Output Cell Counter (LSB)
______________________________________________________________________________________________
134
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
10
02
20
r,
tem
be
ep
9S
,1
ay
rsd
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
hu
R
R
R
R
R
R
R
R
Function
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
OCELL[23]
OCELL[22]
OCELL[21]
OCELL[20]
OCELL[19]
OCELL[18]
OCELL[17]
OCELL[16]
nT
Type
io
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
:53
Register 0x3B: Output Cell Counter (MSB)
fo
liv
ett
OCELL[23:0]:
The OCELL[23:0] bits indicate the number of cells read from the output FIFO
during the last accumulation interval.
Do
wn
loa
de
db
yV
inv
ef
uo
A write to either address 0x00, 0x3A or 0x3B loads the registers with the
current counter value and resets the internal 24 bit counter to 1 or 0. The
counter reset value is dependent on if there was a count event during the
transfer of the count to the Output Cell Counter registers. The counter should
be polled at least every 10 seconds to avoid saturating. The contents of these
registers are valid within four OFCLK cycles after a transfer is triggered by a
write to the Output Cell Count register space.
______________________________________________________________________________________________
135
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
TEST FEATURES DESCRIPTION
20
02
10
Simultaneously forcing the CSB, RDB and WRB inputs low causes all digital output
pins and the data bus to be held in a high-impedance state. This test feature may be
used for board testing.
tem
be
r,
Test mode registers are used to apply test vectors during production testing of the
RCMP-800. Test mode registers (as opposed to normal mode registers) are selected
when TRS (A[6]) is high.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
The RCMP-800 supports a standard IEEE 1149.1 five signal JTAG boundary scan
test port for use in board testing. All digital device inputs except SD[39:0] and
SP[4:0] may be read and all digital device outputs except SD[39:0]. SP[4:0], SADSB,
SRWB, SOEB and SA[19:0] may be forced via the JTAG test port.
______________________________________________________________________________________________
136
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
02
20
r,
tem
be
ep
9S
,1
ay
rsd
io
nT
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
0
hu
BitTypeFunction Default
Bit 15
Unused
Bit 14
Unused
Bit 13
Unused
Bit 12
Unused
Bit 11
Unused
Bit 10
Unused
Bit 9
Unused
Bit 8
Unused
Bit 7
Unused
Bit 6
Unused
Bit 5
Unused
Bit 4
W
PMCTST
Bit 3
W
DBCTRL
Bit 2
R/W
Reserved
Bit 1
W
HIZDATA
Bit 0
R/W
HIZIO
10
:21
Register 0x40: Master Test
fo
liv
ett
This register is used to enable RCMP-800 test features. All bits, except PMCTST,
are reset to zero by a reset of the RCMP-800.
db
yV
inv
ef
uo
HIZIO, HIZDATA:
The HIZIO and HIZDATA bits control the tristate modes of the RCMP-800 .
While the HIZIO bit is a logic 1, all output pins of the RCMP-800 except the
data bus and output TDO. The microprocessor interface is still active. While
the HIZDATA bit is a logic 1, the data bus is also held in a high-impedance
state which inhibits microprocessor read cycles.
Do
wn
loa
de
DBCTRL:
The DBCTRL bit is used to pass control of the data bus drivers to the CSB pin.
When the DBCTRL bit is set to logic 1 and PMCTST is logic 1, the CSB pin
controls the output enable for the data bus. While the DBCTRL bit is set,
holding the CSB pin high causes the RCMP-800 to drive the data bus and
holding the CSB pin low tristates the data bus. The DBCTRL bit overrides the
HIZDATA bit. The DBCTRL bit is used to measure the drive capability of the
data bus driver pads.
PMCTST:
The PMCTST bit is used to configure the RCMP-800 for PMC's manufacturing
______________________________________________________________________________________________
137
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
:21
:53
tests. When PMCTST is set to logic 1, the RCMP-800 microprocessor port
becomes the test access port used to run the PMC "canned" manufacturing
test vectors. The PMCTST bit can be cleared by setting CSB to logic 1 or by
writing logic 0 to the bit.
20
02
Test Mode 0 Details
tem
be
r,
The RCMP-800 allows the logic levels on the device inputs to be read through the
microprocessor interface.
0x5C
0x62
0x63
0x64
SD[15]
SD[14]
SD[13]
SD[12]
SD[11]
SD[10]
SD[9]
SD[8]
SD[7]
SD[6]
SD[5]
SD[4]
SD[3]
SD[2]
SD[1]
SD[0]
SD[31]
SD[30]
SD[29]
SD[28]
SD[27]
SD[26]
SD[25]
SD[24]
SD[23]
SD[22]
SD[21]
SD[20]
SD[19]
SD[18]
SD[17]
SD[16]
SP[4]
SP[3]
SP[2]
SP[1]
SP[0]
SD[39]
SD[38]
SD[37]
SD[36]
SD[35]
SD[34]
SD[33]
SD[32]
ay
rsd
hu
nT
CONG
inv
ef
uo
fo
liv
ett
io
IDAT[14]1
IDAT[13]1 IPOLL
IDAT[12]1
IDAT[11]1 IBUS8
IDAT[10]1 ISOC1
IDAT[9]1 IPRTY[1]1
IDAT[8]1 IPRTY[0]1
IDAT[7]1 ICA[4]1
IDAT[6]1 ICA[3]1
IDAT[5]1 ICA[2]1
ONESEC IDAT[4]1 ICA[1]1
TCK
IDAT[3]1
TRSTB IDAT[2]1
TMS
IDAT[1]1
TDI
IDAT[0]1
0x7A
0x7B
OBUS8
ORDENB
db
Notes:
Must be clocked by IFCLK before being read.
Do
wn
loa
de
1.)
0x4A
IDAT[15]1
yV
D[15]
D[14]
D[13]
D[12]
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
0x48
,1
0x41
9S
ep
To enable test mode 0, the following addresses must be written with 0x0000: 0x49,
0x59, 0x61 and 0x79. Reading the following address locations returns the values for
the indicated inputs :
The following inputs can not be read using the TM0 feature: SYSCLK, IFCLK,
OFCLK, D[15:0], A[6:0], ALE, CSB, WRB, RDB and RSTB.
The SRAM interface pins can be controlled via the External RAM Address and
External RAM Data registers (0x21 through 0x25).
______________________________________________________________________________________________
138
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:53
JTAG Test Port
20
02
10
:21
The RCMP-800 JTAG Test Access Port (TAP) allows access to the TAP controller
and the 4 TAP registers: instruction, bypass, device identification and boundary scan.
Using the TAP, device input logic levels can be read, device outputs can be forced,
the device can be identified and the device scan path can be bypassed. For more
details on the JTAG port, please refer to the Operations section.
tem
be
r,
Instruction Register
Length - 3 bits
ep
9S
,1
ett
io
nT
hu
EXTEST
IDCODE
SAMPLE
BYPASS
BYPASS
STCTEST
BYPASS
BYPASS
Instruction
Codes, IR[2:0]
000
001
010
011
100
101
110
111
ay
Selected
Register
Boundary Scan
Identification
Boundary Scan
Bypass
Bypass
Boundary Scan
Bypass
Bypass
rsd
Instructions
fo
liv
Identification Register
Do
wn
loa
de
db
yV
inv
ef
uo
Length - 32 bits
Version number - 2H
Part Number - 7322H
Manufacturer's identification code - 0CDH
Device identification - 273220CDH
______________________________________________________________________________________________
139
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:53
Boundary Scan Register
10
:21
The least significant bit is the first bit to be scanned in on TDI and scanned out on
TDO.
91
90:75
74:73
72
71
70
69
I/O
I
O
68:67
66
65:63
O
I
I
62
61
60
ONESEC
D[15:0]
DOEB (for D[15:0])
A[6:0]
ALE
I
I/O
E
I
I
I
I
I
I
O
O
I
33
32
31
30
29
28
27
OBUS8
ORDENB
OCA
I
I
O
26
25
24
OFCLK
OSOC
ODATOEB (for
ODAT[15:0],
OSOC and
OPRTY[1:0]
OPRTY[1:0]
ODAT[15:0]
BUSYB
CONG
HIZ*
I
O
E
23
22
21
O
O
O
I
E
20:19
18:3
2
1
0
59
58:43
42
41:35
34
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
9S
CSB
WRB
RDB
RSTB
INTB
DREQ
OTSEN
r,
I
I
I
I
I
I/O
E
tem
be
SYSCLK
IDAT[15:0]
IPRTY[1:0]
ISOC
IFCLK
IAVALID_ICA[4]
IADDR_OEB (for
IAVALID_ICA[4] &
IADDR_ICA[3:2])
IADDR_ICA[3:2]
ICA[1]
IADDR_IWRENB[4
:2]
IWRENB[1]
IPOLL
IBUS8
Type
Pin/Enable
ep
Type
Boundary
Scan
Register Bit
,1
Pin/Enable
Boundary
Scan
Register Bit
20
02
Length - 92 bits
Do
wn
loa
de
db
* The HIZ enable tristates IADDR_IWRENB[4:2], IWRENB[1], DREQ, OCA, BUSYB,
SA[19:0], SOEB, SADSB, SRWB if set to a logic 1.
______________________________________________________________________________________________
140
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
OPERATION
10
SCI-PHY Extended Cell Format
tem
be
r,
20
02
The SCI-PHY extended cell format is a recent enhancement of the SCI-PHY bus
standard described in the "Saturn Compliant Interface for ATM Devices" document
(PMC940102). The extension allows for the appending of up to 10 bytes of additional
information.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
Figures 6 and 7 illustrate the 8 bit wide and 16 bit wide data structures. The length of
the pre-pends and post-pends are independently programmable for each interface.
______________________________________________________________________________________________
141
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
Bit 7
:53
Fig. 6 Eight Bit Wide Cell Format
:21
Bit 0
10
Prepend 1
tem
be
r,
20
02
Prepend 2
H2
Cell Byte 3
H3
Cell Byte 4
H4
UDF
rsd
Cell Byte 5*
PAYLOAD1
Total of
52 to 63
Bytes
ett
io
nT
hu
Cell Byte 6
9S
Cell Byte 2
,1
H1
ay
Cell Byte 1
ep
Prepend X
PAYLOAD48
Postpend 1
Postpend 2
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
Cell Byte 53
Postpend Y
* Cell Byte 5 may optionally be omitted.
______________________________________________________________________________________________
142
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
Bit 8
Bit 7
Bit 0
:21
Bit 15
:53
Fig. 7 Sixteen Bit Wide Cell Format
10
Prepend 1
r,
20
02
Prepend 2
H2
Cell Word 2
H3
H4
Cell Word 3*
UDF1
UDF2
Cell Word 4
PAYLOAD1
PAYLOAD2
Cell Word 5
PAYLOAD3
PAYLOAD4
Cell Word 6
PAYLOAD5
PAYLOAD6
Cell Word 27
PAYLOAD47
ep
H1
Total of
26 to 32
Words
PAYLOAD48
Postpend 1
Postpend 2
Postpend Y
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
Cell Word 1
tem
be
Prepend X
Do
wn
loa
de
db
yV
* Cell Word 3 may optionally be omitted.
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143
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:53
Synchronous Static RAMs
10
:21
The RCMP-800 interfaces directly to synchronous static RAMs commonly used as
cache for Intel Pentium and i486 processors.
Configuration
Access
02
Device
20
Vendor
CY7C1031-10
64K x 18
MCM67x618-11
64K x 18
MCM67x618-14
64K x 18
M67H618-14
64K x 18
M67H618-12
64K x 18
MT58LC64K18B2-12
64K x 18
MT58LC32K36B2-12
32K x 36
-
50 MHz
64K x 18
9 ns
66 MHz
64K x 18
10 ns
58 MHz
64K x 18
12 ns
50 MHz
KM718B86-9
KM718B86-10
12 ns
66 MHz
11 ns
66 MHz
14 ns
66 MHz
14 ns
50 MHz
12 ns
66 MHz
ep
9S
rsd
ay
,1
50 MHz
50 MHz
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
KM718B86-12
hu
Samsung
nT
SGS-Thomson
14 ns
tem
be
64K x 18
Motorola
Micron
Frequency
CY7C1031-12
io
Cypress
r,
Time
Max.
______________________________________________________________________________________________
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STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
OAM Cell Format
tem
be
r,
20
02
10
The automatic OAM cell handling supports a subset of the information fields. The
processing of particular fields is not practical on the RCMP-800. Cells can be
dropped to the Microprocessor Cell Interface for external processing if required. This
section describes the processing of received OAM cells and the coding of fields in the
generated OAM cells.
Received OAM Cells
9S
ep
The following illustrates the active fields in the received OAM cells. Any unsupported
fields are ignored.
Function Specific Fields
Reserved
(6 bits)
Error
Detection
Code (10 bits)
rsd
(45 octets)
ay
,1
OAM Function
Type
Type
(4 bits) (4 bits)
0000
Don't care
CRC-10
Don't care
Don't care
CRC-10
Don't care
Don't care
CRC-10
Don't care
Don't care
CRC-10
Don't care
CRC-10
Don't care
nT
0001
hu
AIS:
0001
fo
liv
0001
ett
io
RDI:
0100
ef
0001
uo
Continuity Check:
1000
yV
0001
inv
Loopback:
0000
MSN
TUC
Do
wn
loa
de
0010
db
Forward Monitoring Performance Management:
BIP-16
(1 oct.) (2 oct.) (2 oct.)
Time Stamp
Don't care
(4 octets)
Unused
Don't care
(36 octets)
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STANDARD PRODUCT
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ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
0001
:21
Don't care
CRC-10
Block Error Lost/Misdelivered
Result
Cell Count
(1 oct.)
(2 octets)
r,
20
Unused Delay Result
Don't care Don't care
(29 oct.)
(4 oct.)
tem
be
Unused Time Stamp
Don't care Don't care
(5 octets)
(4 oct.)
02
10
0010
:53
Backward Reporting Performance Management:
0010
MSN
TUC
000000
CRC-10
ay
,1
9S
0010
ep
Monitoring & Reporting Performance Management:
Delay
Result
Don't care
(29 octets) (4 oct.)
(4 octets)
ett
Activation/Deactivation:
Don't care
Don't care
CRC-10
fo
liv
Don't
Care
uo
1000
Block
Lost/
Error Misdelivered
Result Cell Count
(1 oct.)
(2 octets)
io
(1 oct.) (2 oct.) (2 oct.)
nT
hu
rsd
BIP-16 Time Stamp Unused
Don't care Don't care
db
yV
inv
ef
The Error Detection Code (EDC) is verified for all received OAM cells. The
polynomial represented by the 48 octet information field is divided by
x10+x9+x5+x4+x+1. All OAM cells which have an all zeros remainder are processed.
Cells with an incorrect EDC are discarded.
Do
wn
loa
de
If either the AIStoUP or the RDItoUP register bit is set, the associated cell type is
copied to the Microprocessor Cell Interface for OAM flows terminated by this RCMP800. This allows for external processing of the Failure Type and Failure Location
fields.
If the UNDEFtoUP register bit is set, OAM cells with undefined OAM Type fields are
routed to the Microprocessor Cell Interface for OAM flows terminated by this RCMP800.
______________________________________________________________________________________________
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STANDARD PRODUCT
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ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:53
Generated OAM Cells
Reserved
(45 octets)
(6 bits)
r,
20
Function Specific Fields
tem
be
OAM Function
Type
Type
(4 bits) (4 bits)
02
10
:21
The following illustrates the coding of fields in the generated OAM cells. The coding
of all supported fields is in accordance with the quoted references. Unsupported
fields are coded with the specified defaults.
0000
all octets 6AH
0001
all octets 6AH
000000
CRC-10
000000
CRC-10
000000
CRC-10
000000
CRC-10
9S
0001
ep
AIS:
Error
Detection
Code (10 bits)
ay
0001
rsd
Continuity Check:
all octets 6AH
hu
0100
nT
0001
,1
RDI:
0000
MSN
TUC
inv
ef
BIP-16
uo
fo
liv
ett
0010
io
Forward Monitoring Performance Management:
Unused
6AH
(36 octets)
Do
wn
loa
de
db
yV
(1 oct.) (2 oct.) (2 oct.)
Time Stamp
FFH
(4 octets)
______________________________________________________________________________________________
147
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STANDARD PRODUCT
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PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
:21
:53
The Monitoring Cell Sequence Number (MSN) is incremented with each generated
PM cell for the connection. The Total User Cell (TUC) number is incremented with
each user cell received and is never reset. The BIP-16 value is calculated over all
user cells since the last forward monitoring cell.
000000
20
0001
CRC-10
tem
be
r,
0010
02
Backward Reporting Performance Management:
Block Error Lost/Misdelivered
Result
Cell Count
(1 oct.)
(2 octets)
,1
9S
ep
Unused
6AH
(42 oct.)
liv
ett
io
nT
hu
rsd
ay
The Block Error Result contains the BIPV for the forward monitoring cell received. If
the BIPV is undefined, which occurs when the MSN is not expected or the Total User
Cell Difference (TUCD) is non-zero, the Block Error Result is coded as all ones. The
Lost/Misdelivered Cell Count is coded with the absolute value of the TUCD in the 15
least significant bits and a one in the most significant bit position if TUCD is negative
(i.e. cells have been lost.) Misinserted cells result in a zero in the most significant bit
position.
fo
The RCMP-800 does not generate combined Monitoring/Reporting cells.
inv
ef
uo
The RCMP-800 does not automatically generate Activation/Deactivation and
Loopback cells. These can be inserted through the Microprocessor Cell Interface.
The microprocessor is responsible for coding all fields except the CRC-10.
Do
wn
loa
de
db
yV
All generated OAM cells contain a correct Error Detection Code (EDC).
______________________________________________________________________________________________
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STANDARD PRODUCT
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PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
VC Identification Search Algorithm
9S
ep
tem
be
r,
20
02
10
Within the constraints imposed by the Primary and Secondary Search Table coding
rules, numerous search algorithms are supported. The building of a search data
structure is a software function and is normally performed by the supervising
microcontroller. A shadow data structure is required by the microcontroller to enact
the modifications to the data structure. (It is possible to avoid using a shadow data
structure, but efficiency is reduced by the need to perform searches through multiple
SRAM accesses via the RCMP-800, each taking up to 800ns. Also, diagnostic
possibilities are reduced.)
ay
,1
The algorithm presented below has the following features which optimize it
for VC identification:
Only those bits in the Secondary Search Key required to make an
unique identification are examined. This minimizes the average
search time.
2.)
The number of nodes in the Secondary Search Table is bounded by
the number of VC Table entries. Therefore, the depth of memory
required for the Secondary Search Table is equal to that required for
the VC Table.
3.)
Nodes can be added or deleted on the fly without corrupting a binary
search in progress.
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
1.)
db
Do
wn
loa
de
Overview
yV
A C-language example of the algorithm will be made available.
The VC search algorithm maps the cell's PHY identifier, VCI, VPI and selected
portions of appended bytes to a 16-bit VC Table address. Effectively, it performs the
operation of a Content Addressable Memory (CAM). The data structure created to
support the VC identification is designed around maximizing the efficiency of the
process.
It is the Select field in the Secondary Search Table which makes the search efficient,
because it allows each branching decision to be made based on only the first bit in
which two branches differ. That is, as two values are compared, starting with the
MSB (most significant bit) and moving to the LSB (least significant bit), the two can
______________________________________________________________________________________________
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PM7322 RCMP-800
STANDARD PRODUCT
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PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
02
10
:21
:53
be fully discriminated based on the first bit in which they differ. No other bits after
that bit, regardless of how much they differ, need to be considered. Because not all
bits are not examined in the binary search, the search is concluded with a
confirmation step which compares the Secondary Search Key against the VPI/VCI of
the candidate VC Table.
9S
ep
tem
be
r,
20
The following sub-sections describe the search table initialization, connection addition
and connection removal processes. Refer to the VC Identification sub-section of the
Functional Description section for definitions of the Primary and Secondary Search
Keys, for an overview of the search process and for a definition of the data
structures.
,1
Initialization
rsd
ay
The following are the microcontroller actions required to initialize the Search Tables
and VC Tables:
Set the STANDBY bit of the Master Configuration register (0x01) if not
already set by an asynchronous reset.
1.)
Write zeros (null pointer) to every Primary Search Table location (SA[19:16]
= 0001).
2.)
Write zeros to the fourth word (SA[19:16]=0011) of all VC Table entries. This
clears the "Active" bit in the CONFIG field.
3.)
Clear the STANDBY bit of the Master Configuration register (0x01).
inv
ef
uo
fo
liv
ett
io
nT
hu
1.)
yV
The remaining SRAM locations can be initialized when required.
db
Adding a Connection
Do
wn
loa
de
The following are the microcontroller actions required to provision a connection:
1.)
Determine the next available VC Table address. Initialize the contents of the
VC Table Record via the Microprocessor RAM Address and Data registers
(0x21 through 0x25). Care should be taken to set the following fields
appropriately:
All counts should be set to zero.
The "PM0" field should be set to one.
The "Extended Status" field should be set to 0x050.
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PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
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:53
The "Active" bit of the "Config" field should be set to one.
Perform a binary search to determine the insertion point. The last pointer
accessed in the search shall be the one modified, be it a Primary Search
Table entry, left branch or right branch.
3.)
Find a free Secondary Search Table entry and initialize it. The only
exception to this is when a single VC Table Record exists in a tree, in which
case the solitary Secondary Search Table entry is modified.
tem
be
r,
20
02
10
:21
2.)
9S
ep
The value of the "Select" is set to the index of the most significant bit which
differs between the new VC and the "nearest" existing VC, which was found
in step 2. A few insights need highlighting:
If there is an overlap between Primary and Secondary Search keys
(eg. the Primary key is the VPI), the intersecting bits are excluded
from the binary search based on the fact they will always be the
same in both keys.
2.)
Due to fact that the Primary Search key includes the PHY
identification, NNI and UNI connections will never reside in the same
binary tree. Therefore, the "Select" determination algorithm need all
start its bit comparison at the correct bit (the first bit of the ATM
header for NNI and the fifth bit of the ATM header for UNI) to ensure
a valid search tree.
Perform a SRAM write (via the Microprocessor RAM Address and Data
registers) to incorporate the new Secondary Search Table entry in the
existing tree structure. This step must be performed last to ensure a binary
search in progress is not corrupted.
Do
wn
loa
de
db
yV
inv
ef
4.)
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
1.)
______________________________________________________________________________________________
151
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
The binary tree is empty. In this case, the null primary search table pointer is
modified to point to a newly created Secondary Search Table entry.
Because no bits within the Secondary Search Key are required, both the left
and right branches of the Secondary Search Table entry point to the same
VC Table Record. The "select" field should be set to zero.
20
02
10
1.)
:53
Five distinct types of insertions are possible based on the existing tree structure:
tem
be
Primary
Search Table
AFTER
r,
BEFORE
a
0 1
z
1
z
ay
,1
9S
ep
0
hu
rsd
VC
TABLE
Ent r y
The binary tree contains only a single VC Table Record. Modify the "select"
field to index the most significant bit of the Secondary Search Key which
differs between the new and existing connection. Modify the left or right
branch, as appropriate, to point to the newly created VC Table Record.
yV
inv
ef
2.)
uo
fo
liv
ett
io
nT
Key to data structure diagrams:
a, b, c
- pointers to Secondary Search Table entries
w, x, y, z - pointers to VC Table entries
k,m,n
- "select" field contents
The shaded boxes indicate those fields which have been created or
modified.
Do
wn
loa
de
db
BEFORE
Primary
Search Table
AFTER
a
0 1
z
a
1
z
VC
TABLE
Ent r y
n 1
y
VC
TABLE
Ent r y
1
z
VC
TABLE
Ent r y
The diagram illustrates the case where the new VC has a one in the decision
bit position and the existing VC has a zero in the same bit position. If the
______________________________________________________________________________________________
152
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
The insertion point is at the root of the tree. This occurs when the new
decision bit index is greater any of the indices currently in the search tree. In
this case, the Primary Search Table entry is modified to point to the newly
created Secondary Search Table entry. The New Secondary Search Table
entry points to the new VC Table Record and the old tree root.
tem
be
r,
20
02
3.)
:21
:53
new VC had a zero in the decision bit position, the right branch would have
been modified instead.
Primary
Search Table
AFTER
ep
BEFORE
c
,1
9S
a
a
1
w
ay
k 0
0
b
hu
x
VC
TABLE
Ent r y
y
1
z
n 1
VC
TABLE
Ent r y
x
0
VC
TABLE
Ent r y
b
m 1
y
1 z
VC
TABLE
Ent r y
VC
TABLE
Ent r y
VC
TABLE
Ent r y
VC
TABLE
Ent r y
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
m1
nT
n 1
rsd
k>n>m
______________________________________________________________________________________________
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PM7322 RCMP-800
STANDARD PRODUCT
:53
The insertion point is in the middle of the binary tree. The new Secondary
Search Table entry points to the new VC Table Record and an existing node
in the tree. The parent of the existing node is modified to point to the new
Secondary Search Table entry in the final step of the insertion.
10
:21
4.)
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
20
Primary
Search Table
tem
be
1
z
k 0
k>n>m
9S
VC
TABLE
Ent r y
b
1
ay
,1
n 0
x
1
m 1
y
1
x
nT
VC
TABLE
Ent r y
1
VC
TABLE
Ent r y
w
z
VC
TABLE
Ent r y
VC
TABLE
Ent r y
VC
TABLE
Ent r y
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
VC
TABLE
Ent r y
hu
rsd
y
c
ep
b
a
r,
a
k 0
m1
AFTER
02
BEFORE
______________________________________________________________________________________________
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PM7322 RCMP-800
STANDARD PRODUCT
:53
The new Secondary Search Table entry is inserted at a leaf. The search for
a candidate insertion point ends on a node which already points to a VC
Table Record. The new Secondary Search Table entry points to the existing
VC Table Record and the new VC Table Record. The existing Secondary
Search Table entry is modified to point to the new Secondary Search Table
entry in the final step of the insertion.
20
02
10
:21
5.)
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
AFTER
Primary
Search Table
tem
be
r,
BEFORE
a
ep
a
1
9S
VC
TABLE
Ent r y
y
VC
TABLE
Ent r y
k 0
n 1
VC
TABLE
Ent r y
x
0
b
1
z
VC
TABLE
Ent r y
c
m 1
w
VC
TABLE
Ent r y
1
y
VC
TABLE
Ent r y
ett
io
nT
hu
VC
TABLE
Ent r y
k>n>m
z
,1
x
1
ay
n 1
b
rsd
k 0
fo
liv
Removing a Connection
uo
The following are the microcontroller actions required to remove a connection:
Find the location of the Secondary Search Table entry pointing to the
connection's VC Table Record.
2.)
Modify the parent node (be it the Primary Table entry or another Secondary
Search Table entry) of the Secondary Search Table entry being removed to
point to the node remaining after the connection removal. The only
exception to this is when two VC Table entries exist in a tree, in which case
the solitary Secondary Search Table entry is modified. The VC is now
considered unprovisioned and any cells belonging to the VC will be
discarded.
Do
wn
loa
de
db
yV
inv
ef
1.)
3.)
Tag the removed Secondary Search Table entry as free.
4.)
Read the final statistics for the connection from the VC Table Record. Clear
the "Active" bit of the CONFIG VC Table Record field and tag the record as
free.
______________________________________________________________________________________________
155
PM7322 RCMP-800
STANDARD PRODUCT
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PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
:21
:53
The connection removal process examples are not illustrated because the results are
exactly the reverse of the connection provisioning. (Swap the "BEFORE" and
"AFTER" labels.)
02
Multicast Connections
ep
tem
be
r,
20
The search table may be constructed so a single received cell results in an arbitrary
number of output cells. This is achieved through a linked list of Secondary Search
Table entries, each with an associated VC Table Record which defines the
characteristics of a outgoing VC. Adding and removing multicast VCs is done by
manipulating the linked list.
nT
hu
rsd
ay
,1
9S
All ones in the Select field of the Secondary Search Table entry identifies it as a
multicast linked list element, except for the last in the linked list. The Left_Branch
field contains the VC table address of the multicast VC. The Right_Branch field
points to the Search Table address of the next VC in the multicast. The linked list is
terminated by setting the Select field to an all zeroes value. An all zeroes value in
the Select field indicates that the Left_Branch field provides the final VC Search
Table Address of the multicast set.
io
Adding a Multicast Connection
fo
liv
ett
A multicast VC is inserted at the head of the linked list. The following are the
microcontroller actions required to provision a multicast connection:
Determine the next available VC Table address. Initialize the contents of the
VC Table Record via the Microprocessor RAM Address and Data registers
(0x21 through 0x25).
2.)
Perform a binary search to determine the head of the linked list. If the binary
search terminates at a VC Table Record which does not match the candidate
search key (i.e. empty list), the insertion proceeds as for a non-multicast
connect as described above.
Do
wn
loa
de
db
yV
inv
ef
uo
1.)
3.)
Find a free Secondary Search Table entry and initialize it. Set the
Left_Branch to point to the VC Table address of the new VC Table Record.
Set the Right_Branch to point to the Search Table address of the old head of
the linked list.
An extra step is required when a unicast VC is converted to a multicast with
two VCs. A second Secondary Search Table entry needs to be allocated
whose Left_Branch points to the existing VC Table Record. (Although not
used, it is suggested that the Right_Branch be set to all zeroes.) Set the
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______________________________________________________________________________________________
10
Perform an SRAM write (via the Microprocessor RAM Address and Data
registers) to incorporate the new Secondary Search Table entry in the
existing tree structure. This step must be performed last to ensure a binary
search in progress is not corrupted.
20
02
4.)
:21
:53
Select field to an all zeroes value to indicate this is the end of the linked list.
The new VC forms the head of the two element linked list.
tem
be
r,
The following diagram provides an example of an insertion.
AFTER
Primary
Search Table
9S
ep
BEFORE
a
b
1
z
nT
w 1
0
1
y
1
v
1
1
z
VC
TABLE
Ent r y
b
ones 1
x
1
c
ones 1
VC
TABLE
Ent r y
0
VC
TABLE
Ent r y
w 1
0
d
1
y
1
0
VC
TABLE
Ent r y
yV
inv
ef
uo
VC
TABLE
Ent r y
e
VC
TABLE
Ent r y
d
liv
ones 1
ones 1
VC
TABLE
Ent r y
io
c
ett
1
fo
VC
TABLE
Ent r y
x
hu
VC
TABLE
Ent r y
ones 1
k 0
rsd
k 0
ay
,1
a
db
MULTICAST
LINKED LIST
Do
wn
loa
de
Removing a Multicast Connection
Because each multicast Virtual Connection has an incoming VPI/VCI combination
identical to the other VCs in the multicast, the contents of the VC Table entries must
be examined to isolate the VC to be removed. Once identified, the linked list is
modified to bypass the VC.
The steps required to remove one element of a multicast are:
1.)
Find the location of the Secondary Search Table entry pointing to the head of
the multicast linked list.
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PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
Traverse the linked list to find the VC to be removed.
3.)
Modify the Secondary Search Table entry pointing to the node being
removed to point to the node following the one being removed, as illustrated
below. The VC is now considered unprovisioned.
02
10
:21
:53
2.)
ones 1
ones 1
w
VC
TABLE
Ent r y
VC
TABLE
Ent r y
d
1
x
1
ep
c
9S
VC
TABLE
Ent r y
1
y
0
1
ay
0 1
,1
x
rsd
ones 1
tem
be
r,
20
AFTER
BEFORE
ones 1
VC
TABLE
Ent r y
w
d
1
0
1
y
1
0
VC
TABLE
Ent r y
nT
hu
VC
TABLE
Ent r y
Tag as free.
d
io
Two special cases need to be accommodated:
uo
fo
liv
ett
i.) The VC to be removed is the tail of the list. In this case, the parent
node becomes the new tail and its Select field should be modified to be
all zeroes.
yV
inv
ef
ii.) The removal leaves only one VC in the multicast. The pointer to the
head of the list, should be modified to point to the surviving VC Table
Record. Two Secondary Search Table entries are freed up.
Tag the removed Secondary Search Table entry (or entries) as free.
5.)
Clear the "Active" bit of the CONFIG VC Table Record field and tag the
record as free. If the removed VC was the head of the linked list, read the
final statistics for the connection from the VC Table Record.
Do
wn
loa
de
db
4.)
______________________________________________________________________________________________
158
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
JTAG Support
tem
be
r,
20
02
10
The RCMP-800 supports the IEEE Boundary Scan Specification as described in the
IEEE 1149.1 standards. The Test Access Port (TAP) consists of the five standard
pins, TRSTB, TCK, TMS, TDI and TDO used to control the TAP controller and the
boundary scan registers. The TRSTB input is the active low reset signal used to
reset the TAP controller. TCK is the test clock used to sample data on input, TDI and
to output data on output, TDO. The TMS input is used to direct the TAP controller
through its states. The basic boundary scan architecture is shown below.
rsd
ay
Boundary Scan
Register
TDI
,1
9S
ep
Fig. 8 Boundary Scan Architecture
nT
hu
Device Identification
Register
Instruction
Register
and
Decode
Mux
DFF
TDO
Do
wn
loa
de
TMS
db
yV
inv
ef
uo
fo
liv
ett
io
Bypass
Register
Test
Access
Port
Controller
Control
Select
Tri-state Enable
TRSTB
TCK
______________________________________________________________________________________________
159
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
tem
be
r,
20
02
10
:21
:53
The boundary scan architecture consists of a TAP controller, an instruction register
with instruction decode, a bypass register, a device identification register and a
boundary scan register. The TAP controller interprets the TMS input and generates
control signals to load the instruction and data registers. The instruction register with
instruction decode block is used to select the test to be executed and/or the register
to be accessed. The bypass register offers a single bit delay from primary input, TDI
to primary output , TDO. The device identification register contains the device
identification code.
ay
,1
9S
ep
The boundary scan register allows testing of board inter-connectivity. The boundary
scan register consists of a shift register placed in series with device inputs and
outputs. Using the boundary scan register, all digital inputs, except SD[39:0] and
SP[4:0], can be sampled and shifted out on primary output TDO. In addition, patterns
can be shifted in on primary input, TDI and forced onto all digital outputs, except
SA[19:0], SOEB, SRWB, SADSB, SD[39:0] and SP[4:0].
rsd
TAP Controller
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
The TAP controller is a synchronous finite state machine clocked by the rising edge
of primary input, TCK. All state transitions are controlled using primary input, TMS.
The finite state machine is described below.
______________________________________________________________________________________________
160
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
:53
Fig. 9 TAP Controller Finite State Machine
10
TRSTB=0
20
0
Run-Test-Idle
Select-DR-Scan
0
ep
0
9S
1
1
r,
1
1
tem
be
1
02
Test-Logic-Reset
Select-IR-Scan
0
1
Capture-IR
0
rsd
ay
0
,1
Capture-DR
Shift-IR
1
1
0
0
1
1
Exit1-IR
Exit1-DR
liv
ett
io
nT
hu
Shift-DR
0
uo
fo
0
ef
inv
yV
0
1
0
0
1
0
Exit2-DR
db
Do
wn
loa
de
Pause-IR
Pause-DR
Exit2-IR
1
1
Update-DR
1
0
Update-IR
1
0
All transitions dependent on input TMS
______________________________________________________________________________________________
161
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
r,
tem
be
Run-Test-Idle
The run test/idle state is used to execute tests.
20
02
10
:21
:53
Test-Logic-Reset
The test logic reset state is used to disable the TAP logic when the device is in
normal mode operation. The state is entered asynchronously by asserting
input, TRSTB. The state is entered synchronously regardless of the current
TAP controller state by forcing input, TMS high for 5 TCK clock cycles. While
in this state, the instruction register is set to the IDCODE instruction.
ay
,1
9S
ep
Capture-DR
The capture data register state is used to load parallel data into the test data
registers selected by the current instruction. If the selected register does not
allow parallel loads or no loading is required by the current instruction, the test
register maintains its value. Loading occurs on the rising edge of TCK.
nT
hu
rsd
Shift-DR
The shift data register state is used to shift the selected test data registers by
one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK.
uo
fo
liv
ett
io
Update-DR
The update data register state is used to load a test register's parallel output
latch. In general, the output latches are used to control the device. For
example, for the EXTEST instruction, the boundary scan test register's parallel
output latches are used to control the device's outputs. The parallel output
latches are updated on the falling edge of TCK.
yV
inv
ef
Capture-IR
The capture instruction register state is used to load the instruction register
with a fixed instruction. The load occurs on the rising edge of TCK.
Do
wn
loa
de
db
Shift-IR
The shift instruction register state is used to shift both the instruction register
and the selected test data registers by one stage. Shifting is from MSB to LSB
and occurs on the rising edge of TCK.
Update-IR
The update instruction register state is used to load a new instruction into the
instruction register. The new instruction must be scanned in using the Shift-IR
state. The load occurs on the falling edge of TCK.
The Pause-DR and Pause-IR states are provided to allow shifting through the test
data and/or instruction registers to be momentarily paused.
______________________________________________________________________________________________
162
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
:53
The TDO output is enabled during states Shift-DR and Shift-IR. Otherwise, it is
tri-stated.
10
Boundary Scan Instructions
20
02
The following is a description of the standard instructions. Each instruction selects a
serial test data register path between input, TDI and output, TDO.
ep
tem
be
r,
BYPASS
The bypass instruction shifts data from input, TDI to output, TDO with one TCK
clock period delay. The instruction is used to bypass the device.
io
nT
hu
rsd
ay
,1
9S
EXTEST
The external test instruction allows testing of the interconnection to other
devices. When the current instruction is the EXTEST instruction, the boundary
scan register is place between input, TDI and output, TDO. Primary device
inputs can be sampled by loading the boundary scan register using the
Capture-DR state. The sampled values can then be viewed by shifting the
boundary scan register using the Shift-DR state. Primary device outputs can
be controlled by loading patterns shifted in through input TDI into the boundary
scan register using the Update-DR state.
inv
ef
uo
fo
liv
ett
SAMPLE
The sample instruction samples all the device inputs and outputs. For this
instruction, the boundary scan register is placed between TDI and TDO.
Primary device inputs and outputs can be sampled by loading the boundary
scan register using the Capture-DR state. The sampled values can then be
viewed by shifting the boundary scan register using the Shift-DR state.
Do
wn
loa
de
db
yV
IDCODE
The identification instruction is used to connect the identification register
between TDI and TDO. The device's identification code can then be shifted
out using the Shift-DR state.
STCTEST
The single transport chain instruction is used to test out the TAP controller and
the boundary scan register during production test. When this instruction is the
current instruction, the boundary scan register is connected between TDI and
TDO. During the Capture-DR state, the device identification code is loaded
into the boundary scan register. The code can then be shifted out output, TDO
using the Shift-DR state.
______________________________________________________________________________________________
163
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
tem
be
r,
20
02
10
:21
:53
INTEST
The internal test instruction is not fully implemented. When this instruction is
the current instruction, the boundary scan register is connected between TDI
and TDO. During the Capture-DR state, primary outputs are sampled and
loaded into the boundary scan register.
______________________________________________________________________________________________
164
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
FUNCTIONAL TIMING
10
Input Cell Interface
20
02
Fig. 10 Input Cell Master Interface (IPOLL=0)
tem
be
r,
••••
IFCLK (I)
Ignored if ICALEVEL0 bit = 0
••••
ICA[y] (I)
••••
IWRENB[x] (O)
••••
rsd
ay
,1
9S
ep
ICA[x] (I)
nT
hu
IWRENB[y] (O)
••••
XX
XX
XX
W1
W2
••••
W(n-2) W(n-1)
W(n)
xx
xx
xx
W1
uo
fo
IDAT[15:0] (I)
liv
ett
io
ISOC (I)
••••
••••
yV
inv
ef
IPRTY[1:0] (I)
Do
wn
loa
de
db
The Input Cell Master Interface (IPOLL=0) diagram (Fig. 10) illustrates the operation
of the interface when it arbitrates accesses for a single or multiple PHYs. If operating
with a single PHY interface, only the ICA[1] and IWRENB[1] control signals are
active. When there is room for another cell in the RCMP-800 buffers and one of the
ICA[4:1] inputs indicates that there is a cell available, the RCMP-800 will respond by
asserting the associated IWRENB[4:1] output. The RCMP-800 only supports cell
level handshaking; IWRENB[x] remains asserted until the entire cell is written into the
FIFO. Once a transfer has been initiated, all bytes are assumed to be valid and
ICA[x] is ignored until the end of the cell if the ICALEVEL0 bit of the Input Cell FIFO
Configuration register (0x08) is a logic 0. If ICALEVEL0 is a logic 1, an early
deassertion of ICA[x] is considered a break in the protocol and the cell is discarded.
______________________________________________________________________________________________
165
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
:21
:53
There is a minimum of three clock cycles between one IWRENB[x] being deasserted
at the end of a cell and another IWRENB[y] being asserted at the start of the next
cell.
9S
ep
tem
be
r,
20
02
ISOC is expected to be high during the first word of the data structure. The length of
the data structure and the position of the ATM cell within the data structure is set by
the CELLLEN[3:0] and CELLPOST[3:0] bits of the Input Cell FIFO Configuration
register. It is not necessary for ISOC to be present each cell; the input cell write
address is generated by an internal counter that flywheels in the absence of ISOC. If
ISOC is sampled high during any byte other than the first byte of the data structure,
an interrupt may be generated and the input cell write address counter is reset to the
first byte of the data structure.
ay
,1
Fig. 11 Input Cell Interface Address Line Polling Master Configuration
(IPOLL=1) – Example 1
ICA[1] (I)
nT
hu
rsd
IFCLK (I)
CA(N+5)
CA(N+6)
CA(N+5)
CA(N+6)
io
CA(N+4)
1Fh
N+5
1Fh
N+6
1Fh
N+5
1Fh
N+6
1Fh
N+7
XX
W1
W2
W3
uo
N+4
ef
IADDR[4:0] (O)
fo
liv
ett
IWRENB[1] (O)
yV
inv
IAVALID (O)
Do
wn
loa
de
db
ISOC (I)
IDAT[15:0] (I)
W(n-7) W(n-6) W(n-5) W(n-4) W(n-3) W(n-2) W(n-1)
W(n)
XX
XX
IPRTY[1:0] (I)
______________________________________________________________________________________________
166
PM7322 RCMP-800
STANDARD PRODUCT
10
:21
:53
Fig. 12 Input Cell Interface Address Line Polling Master Configuration
(IPOLL=1) – Example 2
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
CA(N+8)
CA(N+9)
CA(N+8)
CA(N+9)
tem
be
r,
CA(N+7)
20
ICA[1] (I)
02
IFCLK (I)
N+7
1Fh
N+8
1Fh
N+9
1Fh
N+8
1Fh
N+9
1Fh
N+10
9S
IADDR[4:0] (O)
ep
IWRENB[1] (O)
ay
,1
IAVALID (O)
W(n-2) W(n-1)
W(n)
XX
XX
XX
XX
XX
XX
XX
W1
W2
W3
io
IDAT[15:0] (I)
nT
hu
rsd
ISOC (I)
uo
fo
liv
ett
IPRTY[1:0] (I)
yV
inv
ef
Figures 11 and 12 illustrate the operation of the Input Cell Interface when it arbitrates
accesses for up to 32 PHYs using address line polling. The ICA[1] and IWRENB[1]
control signals are active.
Do
wn
loa
de
db
The PHY devices are polled cyclically beginning with PHY#(N+1) where N is the PHY
ID of the cell currently being transferred. The first PHY device to respond to polling
with an available cell indication is selected for transfer of the next cell. If no PHY
device responds with an available cell indication, the polling cycle repeats. If the
polling cycle repeats while the current cell is being transferred, however, the PHY ID
of the cell being transferred (i.e. N) is omitted from the polling sequence. This is
because PHY devices compliant with the UTOPIA Level 1 interface (which can be
used in polling mode with external glue logic) cannot indicate availability of a
subsequent cell while they are simultaneously transferring a cell. Once transfer of
the current cell is complete, PHY#N is re-inserted into the polling sequence.
When a PHY device with an available cell is found, polling ceases and the PHY
device is selected for transfer of the next cell. (If the PHY is found while a cell is
______________________________________________________________________________________________
167
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
02
10
:21
:53
being transferred, its ID is output on IADDR[4:0] and held until the start of the next
cell transfer.) The PHY device recognises that it has been selected to send the next
cell to the RCMP-800 by the presence of its ID on IADDR[4:0] during the clock cycle
prior to IWRENB[1] being asserted low. After IWRENB[1] is asserted low (i.e. at the
start of the next cell transfer), the polling process starts again.
9S
ep
tem
be
r,
20
Figure 11 shows an example in which the first PHY to be found with a cell available is
PHY#(N+5) and the successful poll occurs during a cell transfer. The value N+5 is
therefore output on IADDR[4:0] and held until the start of the next cell transfer. Note
that because of the pipelined nature of the polling process, PHY#(N+6) is
unavoidably polled before PHY#(N+5) is selected. The polling reply from PHY#(N+6)
is ignored. If, for any reason, PHY#(N+5) and deasserts ICA[1] before the start of the
next cell transfer, the polling process starts over.
ett
io
nT
hu
rsd
ay
,1
Figure 12 shows a second example in which the first PHY to be found with a cell
available is PHY#(N+8) and the successful poll occurs after the previous cell transfer
has completed. In this case, the value N+8 is output on IADDR[4:0] for three clock
cycles after which IWRENB[1] is asserted to initiate transfer of the next cell. (Three
clock cycles is the minimum required to re-sample ICA[1] and confirm that the cell is
still available, i.e. that the PHY has not changed its mind.) Again, because of the
pipelined nature of the polling process, PHY#(N+9) is unavoidably polled before
PHY#(N+8) is selected.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ISOC is expected to be high during the first word of the data structure. The length of
the data structure and the position of the ATM cell within the data structure is set by
the CELLLEN[3:0] and CELLPOST[3:0] bits of the Input Cell FIFO Configuration
register. It is not necessary for ISOC to be present each cell; the input cell write
address is generated by an internal counter that flywheels in the absence of ISOC. If
ISOC is sampled high during any byte other than the first byte of the data structure,
an interrupt may be generated and the input cell write address counter is reset to the
first byte of the data structure.
______________________________________________________________________________________________
168
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:53
Output Cell Interface
OCA (O)
••••
ORDENB (I)
••••
OSOC (O)
••••
ODAT[15:0] (O)
XX
••••
OPRTY[1:0] (O)
XX
10
••••
20
02
OFCLK (I)
:21
Fig. 13 Output Cell Interface Single-PHY Slave ( OTSEN=0)
ep
tem
be
r,
OCALEVEL0 = 0
invalid read, no data available
W(n-5) W(n-4) W(n-3) W(n-2) W(n-1) XX
9S
W2
W(n)
XX
XX
XX
W(1)
,1
W1
rsd
ay
••••
ett
io
nT
hu
The Output Synchronous FIFO Timing Single-PHY Slave (OTSEN=0) diagram (Fig.
13) illustrates the operation of the Output Cell Interface as a bus slave with tristating
disabled. The diagram illustrates the case where the OCAINV bit is a logic 0; the
sense of the OCA output may be inverted by setting OCAINV to a logic 1.
db
yV
inv
ef
uo
fo
liv
The RCMP-800 indicates a cell is available by asserting the output cell available
output, OCA. OCA remains high until the FIFO is near empty (four words remaining),
empty or an error condition is detected. Selection of empty and near empty is made
using the OCALEVEL0 bit in the Output FIFO Configuration register. For the near
empty option, OCA transitions low four words before the last word of the last cell is
read from the FIFO. OCA remains low for a minimum of one OFCLK clock cycle and
then can transition high to indicate that there are additional cells available.
Do
wn
loa
de
Note that if the Output Cell Interface is not near empty, OCA will remain asserted,
such that cells can be read out back-to-back.
______________________________________________________________________________________________
169
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
••••
ORDENB (I)
••••
OSOC (O)
••••
:21
OCA (O)
10
••••
02
OFCLK (I)
:53
Fig. 14 Output Cell Interface Single-PHY Slave ( OTSEN=1)
tem
be
r,
20
OCALEVEL0 = 0
invalid read, no data available
W1
••••
W2
W(n)
XX
W(1)
9S
••••
,1
OPRTY[1:0] (O)
W(n-5) W(n-4) W(n-3) W(n-2) W(n-1)
ep
ODAT[15:0] (O)
rsd
ay
The Output Cell Interface Single-PHY Slave (OTSEN=1) diagram (Fig. 14) illustrates
the operation of the Output Cell Interface with tristating enabled.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
The functional behaviour is the same as when tristating is disabled except that OSOC,
ODAT[15:0] and OPRTY[1:0] are tristated the cycle after ORDENB is deasserted.
______________________________________________________________________________________________
170
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
ABSOLUTE MAXIMUM RATINGS
-40°C to +85°C
Storage Temperature
-40°C to +125°C
Supply Voltage
-0.5V to +6.0V
Voltage on Any Pin
-0.5V to VDD+0.5V
Static Discharge Voltage
±1000 V
Latch-Up Current
±100 mA
9S
ep
tem
be
r,
20
02
10
Case Temperature under Bias
±20 mA
Lead Temperature
+220°C
+150°C
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
Absolute Maximum Junction Temperature
rsd
ay
,1
DC Input Current
______________________________________________________________________________________________
171
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
D.C. CHARACTERISTICS
Parameter
Min
Max
Units Conditions
VIL
Input Low Voltage
(TTL Only)
-0.5
0.8
Volts
VIH
Input High
Voltage
(TTL Only)
2.0
VDD
+0.5
Volts
VOL
Output or Bidirectional Low
Voltage
(TTL Only)
VOH
Output or Bidirectional High
Voltage
(TTL Only)
VT+
Reset Input High
Voltage
VT-
Reset Input Low
Voltage
VTH
Reset Input
Hysteresis
Voltage
IILPU
Input Low Current +175 +350 +525
(Pull ups)
µA
VIL = GND, Notes 1, 3
IIHPU
Input High
Current (Pull ups)
-10
+10
µA
VIH = VDD, Notes 1, 3
IIL
Input Low Current
-10
+10
µA
VIL = GND, Notes 2, 3
IIH
Input High
Current
-10
+10
µA
VIH = VDD, Notes 2, 3
CIN
Input Capacitance
,1
ep
tem
be
Guaranteed Input LOW
Voltage
Guaranteed Input HIGH
Voltage
Volts
VDD = min, IOL = -2 mA,
Note 3
Volts
VDD = min, IOH = 2 mA,
Note 3
3.5
Volts
uo
fo
liv
ett
io
nT
VDD
-0.5V
hu
rsd
ay
0.4
r,
Symbol
9S
Typ
20
02
10
(TC = -40°C to +85°C, VDD = 5 V ±5%)
(Typical Conditions: TC = 25°C, VDD = 5 V)
inv
ef
0.6
Volts
Do
wn
loa
de
db
yV
1
5
Volts
pF
______________________________________________________________________________________________
172
PM7322 RCMP-800
STANDARD PRODUCT
CIO
Bidirectional
Capacitance
5
pF
IDDOP
Operating Current
Processing Cells
:53
pF
:21
5
10
Output
Capacitance
02
COUT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
20
r,
mA
9S
ep
tem
be
670
VDD = 5.25 V, Outputs
Unloaded,
SYSCLK =50 MHz,
IFCLK = 50 MHz,
OFCLK = 50 MHz,
,1
Notes on D.C. Characteristics:
rsd
ay
1. Input pin or bidirectional pin with internal pull-up resistor.
hu
2. Input pin or bidirectional pin without internal pull-up resistor
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
3. Negative currents flow into the device (sinking), positive currents flow out of
the device (sourcing).
______________________________________________________________________________________________
173
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS
10
(TC = -40°C to +85°C, VDD = 5 V ±5%)
20
Parameter
Min
Max
r,
Symbol
02
Microprocessor Interface Read Access (Fig. 15)
Address to Valid Read Set-up Time
tHAR
Address to Valid Read Hold Time
tSALR
Address to Latch Set-up Time
tHALR
Address to Latch Hold Time
tVL
Valid Latch Pulse Width
tSLR
Latch to Read Set-up
tHLR
Latch to Read Hold
tPRD
Valid Read to Valid Data Propagation Delay
tZRD
10 (typ)
ns
5 (typ)
ns
10
ns
10
ns
20
ns
0
ns
5
ns
nT
hu
rsd
ay
,1
9S
ep
tem
be
tSAR
Units
ns
Valid Read Negated to Output Tristate
20 (typ)
ns
tPDREQ
Valid Read Asserted to DREQ Deasserted
50 (typ)
ns
tZINTH
Valid Read Negated to INTB Tristate
50
ns
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
50
______________________________________________________________________________________________
174
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
:53
Fig. 15 Microprocessor Interface Read Timing
Address
r,
20
Valid
02
A[6:0]
10
tSAR
tHAR
tem
be
tS ALR
tV L
ep
tHALR
9S
ALE
ay
,1
tHLR
rsd
tS LR
tP DREQ
io
nT
hu
(CSB+RDB)
fo
liv
ett
DREQ
ef
uo
tZ INTH
yV
inv
INTB
Do
wn
loa
de
db
tPRD
tZ RD
Valid Data
D[15:0]
Notes on Microprocessor Interface Read Timing:
1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point
of the reference signal to the 1.4 Volt point of the output.
______________________________________________________________________________________________
175
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
:53
2. Maximum output propagation delays are measured with a 100 pF load on the
Microprocessor Interface data bus, (D[15:0]).
10
3. A valid read cycle is defined as a logical OR of the CSB and the RDB signals.
20
02
4. Microprocessor Interface timing applies to normal mode register accesses only.
tem
be
r,
5. In non-multiplexed address/data bus architecture's, ALE should be held high,
parameters tSALR, tHALR, tVL, and tSLR are not applicable.
ep
6. Parameter tHAR is not applicable if address latching is used.
ay
,1
9S
7. When a set-up time is specified between an input and a clock, the set-up time is
the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of
the clock.
nT
hu
rsd
8. When a hold time is specified between an input and a clock, the hold time is the
time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the
clock.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
9. Output tristate delay is the time in nanoseconds from the 1.4 Volt point of the
reference signal to ±300mV of the termination voltage on the output. The test
load is 50Ω to 1.4V in parallel with 10 pf to GND.
______________________________________________________________________________________________
176
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
Min
Max
10
Parameter
Units
Address to Valid Write Set-up Time
10
tSDW
Data to Valid Write Set-up Time
20
ns
tSALW
Address to Latch Set-up Time
ns
tHALW
Address to Latch Hold Time
tVL
Valid Latch Pulse Width
tSLW
Latch to Write Set-up
tHLW
Latch to Write Hold
tHDW
Data to Valid Write Hold Time
tHAW
Address to Valid Write Hold Time
tVWR
Valid Write Pulse Width
02
tSAW
20
Symbol
:53
Microprocessor Interface Write Access (Fig. 16)
10
ns
20
ns
0
ns
5
ns
5
ns
5
ns
40
ns
nT
hu
rsd
ay
,1
9S
ep
tem
be
r,
10
ns
liv
ett
io
Fig. 16 Microprocessor Interface Write Timing
Valid Address
uo
fo
A[6:0]
tS LW
tHLW
Do
wn
loa
de
db
ALE
tV L
tH ALW
yV
inv
ef
tS ALW
tSAW
tVWR
tH AW
(CSB+WRB)
tS DW
D[15:0]
tH DW
Valid Data
______________________________________________________________________________________________
177
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
:21
Notes on Microprocessor Interface Write Timing:
02
1 A valid write cycle is defined as a logical OR of the CSB and the WRB signals.
20
2. Microprocessor Interface timing applies to normal mode register accesses only.
tem
be
r,
3. In non-multiplexed address/data bus architecture's, ALE should be held high,
parameters tSALW, tHALW, tVL, and tSLW are not applicable.
ep
4. Parameter tHAW is not applicable if address latching is used.
ay
,1
9S
5. When a set-up time is specified between an input and a clock, the set-up time is
the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of
the clock.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
6. When a hold time is specified between an input and a clock, the hold time is the
time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the
clock.
______________________________________________________________________________________________
178
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
RCMP-800 TIMING CHARACTERISTICS
10
(TC = -40°C to +85°C, VDD = 5 V ±5%)
20
Description
Min
r,
Symbol
02
Input Cell Interface (Fig. 17 and 18)
tem
be
IFCLK Frequency
tHIDAT
IDAT[15:0] Hold time to IFCLK
tSIPRTY
IPRTY[1:0] Set-up time to IFCLK
tHIPRTY
IPRTY[1:0] Hold time to IFCLK
tSISOC
ISOC Set-up time to IFCLK
tHISOC
ISOC Hold time to IFCLK
tSICA
ICA[4:1] Set-up time to IFCLK
tHICA
ICA[4:1] Hold time to IFCLK
tPIWRENB
IFCLK High to IWRENB[4:1] Valid
CL = 50 pF
CL = 20 pF
fo
uo
ef
inv
IFCLK High to IADDR[4:0] Valid
CL = 50 pF
CL = 20 pF
IFCLK High to IAVALID Valid
CL = 50 pF
CL = 20 pF
Do
wn
loa
de
tPIAVALID
db
yV
tPIADDR
40
2
Units
52
MHz
60
%
ns
1
ns
2
ns
1
ns
2
ns
1
ns
2
ns
1
ns
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
tSIDAT
IFCLK Duty Cycle
IDAT[15:0] Set-up time to IFCLK
Max
1
1
15
12
ns
ns
1
1
15
12
ns
ns
1
1
1
15
15
12
ns
ns
ns
______________________________________________________________________________________________
179
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
:53
Fig. 17 Input Cell Interface Master (IPOLL=0) Timing
tH
ICA
ICA
20
02
tS
10
IFCLK
tH
IDAT
tem
be
tS
r,
ICA[4:1]
IDAT
9S
tH
IPRTY
IPRTY
,1
tS
ep
IDAT[15:0]
ISOC
rsd
tH
ISOC
hu
tS
ay
IPRTY[1:0]
io
nT
ISOC
ett
tP IWRENB
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
IWRENB[4:1]
______________________________________________________________________________________________
180
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
:53
Fig. 18 Input Cell Interface Master (IPOLL=1) Timing
ICA
02
tH
ICA
20
tS
10
IFCLK
tH
IDAT
IDAT
ep
tS
tem
be
r,
ICA[1]
IPRTY
,1
tH
IPRTY
rsd
ay
tS
9S
IDAT[15:0]
tH
ISOC
nT
ISOC
io
tS
hu
IPRTY[1:0]
liv
ett
ISOC
uo
fo
tP IWRENB
inv
ef
IWRENB[1]
yV
db
Do
wn
loa
de
IADDR[4:0]
tP IADDR
tP IAVALID
IAVALID
______________________________________________________________________________________________
181
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
Description
Min
Units
52
MHz
60
%
ns
tPOSOC
OFCLK High to OSOC Valid,
02
ORDENB Hold time to OFCLK
20
tHORDENB
40
4
1
ns
1
1
15
12
ns
ns
1
1
15
12
ns
ns
15
12
ns
ns
15
ns
1
15
ns
1
1
15
12
ns
ns
9S
ep
CL = 50 pF
CL = 20 pF
tem
be
r,
tSORDENB
OFCLK Duty Cycle
ORDENB Set-up time to OFCLK
rsd
ay
,1
OFCLK High to ODAT[15:0] Valid,
CL = 50 pF
CL = 20 pF
OFCLK High to OPRTY[1:0] Valid,
CL = 50 pF
CL = 20 pF
1
1
tPOFCLK
OFCLK High to Output Enable
1
tZOFCLK
OFCLK High to Output Tristate
tPOCA
OFCLK High to OCA Valid,
uo
fo
liv
ett
io
nT
hu
tPOPRTY
Max
10
OFCLK Frequency
tPODAT
:21
Symbol
:53
Output Cell Interface (Fig. 19)
Do
wn
loa
de
db
yV
inv
ef
CL = 50 pF
CL = 20 pF
______________________________________________________________________________________________
182
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:53
Fig. 19 Output Cell Interface Slave Timing
10
:21
OTSEN = 0:
02
OFCLK
r,
20
tS ORDENB tH ORDENB
tem
be
ORDENB
ep
tP ODAT
,1
9S
ODAT[15:0]
ay
tP OPRTY
tP OCA
io
nT
hu
rsd
OPRTY[1:0]
liv
ett
OCA
fo
ef
uo
OSOC
Do
wn
loa
de
db
yV
inv
OTSEN = 1:
OFCLK
tP OSOC
ORDENB
tPOFCLK
tZOFCLK
ODAT[15:0]
OPRTY[1:0]
OSOC
Valid Data
______________________________________________________________________________________________
183
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
Min
tCYC
SYSCLK Period
19.2
tSSD
SYSCLK Duty Cycle
SD[39:0] and SP[4:0] Set-up time to
tHSD
SYSCLK
SD[39:0] and SP[4:0] Hold time to SYSCLK
tPSD
SYSCLK High to SD[39:0] and SP[4:0] Valid
tZSD
SYSCLK High to SD[39:0] and SP[4:0]
tPSA
Units
†
ns
60
%
20
02
40
Max
10
Description
4
2
ns
ns
tem
be
r,
Symbol
:53
Synchronous SRAM Interface (Fig. 20)
15
ns
Tri-state
SYSCLK High to SA[19:0] Valid,CL = 50pf
CL = 20pf
1
2
1
15
15
12
ns
ns
tPSADSB
SYSCLK High to SADSB Valid,CL = 50pf
CL = 20pf
2
1
15
12
ns
tPSOEB
SYSCLK High to SOEB Valid,
CL = 50pf
CL = 20pf
2
1
15
12
ns
tPSRWB
SYSCLK High to SRWB Valid,
CL = 50pf
CL = 20pf
2
1
15
12
ns
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
2
1
Do
wn
loa
de
t CYC <
db
yV
inv
ef
† The SYSCLK period must be less than 16 times the maximum of the IFCLK and
OFCLK periods for correct operation of the internal FIFOs, but it will usually be
constrained by the cell throughput required. To guarantee a sustained throughput
of N cell/s:
N(Max. Search Tree Depth + 17)
______________________________________________________________________________________________
184
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
:53
Fig. 20 Synchronous SRAM Interface Timing
tPSA
20
t CYC
02
10
SYSCLK
tem
be
r,
SA[19:0]
9S
ep
tP SADSB
tP SADSB
rsd
tP SOEB
hu
tP SOEB
ay
,1
SADSB
io
nT
SOEB
tP SRWB
liv
ett
tP SRWB
uo
fo
SRWB
tSSD
tZSD
inv
ef
tPSD
Valid RCMP
Data
Valid SRAM
Data Out
Do
wn
loa
de
db
yV
SD[39:0],
SP[4:0]
tHSD
______________________________________________________________________________________________
185
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
Description
Min
0
tSTMS
TCK Duty Cycle
TMS Set-up time to TCK
40
10
tHTMS
TMS Hold time to TCK
tSTDI
TDI Set-up time to TCK
tHTDI
TDI Hold time to TCK
tPTDO
TCK Low to TDO Valid
Units
6
MHz
60
%
ns
10
ns
10
ns
10
ns
0
20
ns
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
tem
be
r,
20
02
TCK Frequency
Max
10
Symbol
:21
JTAG Port Interface (Fig. 21)
______________________________________________________________________________________________
186
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
:53
Fig. 21 JTAG Port Interface Timing
tS TDI
tH TDI
20
tH TMS
r,
tS TMS
02
10
TCK
9S
ep
tem
be
TMS
nT
hu
rsd
ay
,1
TDI
ett
io
TCK
fo
liv
tP TDO
Do
wn
loa
de
db
yV
inv
ef
uo
TDO
______________________________________________________________________________________________
187
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
Notes on Input Timing:
20
02
10
1. When a set-up time is specified between an input and a clock, the set-up time is
the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of
the clock.
tem
be
r,
2. When a hold time is specified between an input and a clock, the hold time is the
time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the
input.
ep
Notes on Output Timing:
,1
9S
1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point
of the reference signal to the 1.4 Volt point of the output.
hu
rsd
ay
2. Maximum and minimum output propagation delays are specified with a 50 pF load
on the outputs, unless otherwise noted.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
3. Output tristate delay is the time in nanoseconds from the 1.4 Volt point of the
reference signal to ±300mV of the termination voltage on the output. The test
load is 50Ω to 1.4V in parallel with 10 pf to GND.
______________________________________________________________________________________________
188
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
10
:21
ORDERING AND THERMAL INFORMATION
DESCRIPTION
240 Slugged Plastic Quad Flat Pack (PQFP)
CASE TEMPERATURE
Theta Ja
24 °C/W
r,
PART NO.
PM7322-SI
20
02
PART NO.
PM7322-SI
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
tem
be
-40°C to +85°C
Theta Jc
8 °C/W
______________________________________________________________________________________________
189
PM7322 RCMP-800
STANDARD PRODUCT
:53
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
:21
MECHANICAL INFORMATION
10
240 Pin Slugged Plastic Quad Flat Pack (S Suffix):
D
02
A
20
240
D1
tem
be
r,
Pin 1
Designator
1
ep
e
Hy
rsd
ay
,1
9S
E1
E
hu
nT
EXPOSED HEATSINK
ett
SEE DETAIL A
liv
0-10 DEG.
NOTES: 1) ALL DIMENSIONS IN MILLIMETER.
STANDOFF
2) DIMENSIONS SHOWN ARE NOMINAL
WITH TOLERANCES AS INDICATED.
A1
fo
.25
uo
SEATING
C
3) FOOT LENGTH "L" IS MEASURED AT
GAGE PLANE, 0.25 ABOVE SEATING PLANE.
C
0-7 DEG
L
LEAD COPLANARITY
ccc
inv
0.13-0.23
b
ef
PLANE
8-12 DEG.
A2
io
Hx
A
8-12 DEG.
C
yV
DETAIL A
PACKAGE TYPE: 240 PIN SLUGGED METRIC PLASTIC QUAD FLATPACK-SMQFP
BODY SIZE: 32 x 32 x 3.40 MM
A1
3.15
0.25
A2
D
D1
E
E1
L
2.90
34.35
31.90
34.35
31.90
0.45
34.60
32.00
34.60
32.00
0.60
34.85
32.10
34.85
32.10
0.75
db
A
Min.
Do
wn
loa
de
Dim.
Nom.
Max.
4.10
0.50
3.60
e
b
ccc
Hx
Hy
0.17
0.50
0.22
0.27
24.20
24.20
0.10
______________________________________________________________________________________________
190
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
tem
be
r,
20
02
10
:21
:53
NOTES
______________________________________________________________________________________________
191
PM7322 RCMP-800
STANDARD PRODUCT
PM
PMC-940904, ISSUE 6
ROUTING CONTROL, MONITORING AND POLICING 800 Mbps
______________________________________________________________________________________________
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
tem
be
r,
20
02
10
:21
:53
NOTES
db
______________________________________________________________________________________________
Do
wn
loa
de
Seller will have no obligation or liability in respect of defects or damage caused by unauthorized use, mis-use,
accident, external cause, installation error, or normal wear and tear. There are no warranties, representations or
guarantees of any kind, either express or implied by law or custom, regarding the product or its performance, including
those regarding quality, merchantability, fitness for purpose, condition, design, title, infringement of third-party rights,
or conformance with sample. Seller shall not be responsible for any loss or damage of whatever nature resulting from
the use of, or reliance upon, the information contained in this document. In no event will Seller be liable to Buyer or to
any other party for loss of profits, loss of savings, or punitive, exemplary, incidental, consequential or special
damages, even if Seller has knowledge of the possibility of such potential loss or damage and even if caused by
Seller’s negligence.
© 1997 PMC-Sierra, Inc.
PMC-940904(R6) ref PMC-940903(A9)
Issue date: August, 1997.
______________________________________________________________________________________________
PMC-Sierra, Inc.
105-8555 Baxter Place, Burnaby, BC Canada V5A 4V7 604 415-6000