ETC PM7800?

PMC-Sierra, Inc.
Released
Digital Correction Signal Processor
PM7800 PALADIN-10
Data Sheet
ISSUE 4
Digital Correction Signal Processor
11
:49
:25
PM
PMC-2001646
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PM7800
Data Sheet
PROPRIETARY AND CONFIDENTIAL
Released
Issue 4: May, 2002
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Digital Correction Signal Processor
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
PMC-Sierra, Inc.
Released
Digital Correction Signal Processor
PM7800 PALADIN-10
Data Sheet
ISSUE 4
Digital Correction Signal Processor
:25
PM
PMC-2001646
:49
PUBLIC REVISION HISTORY
Issue Date
Details of Change
Issue 1
January, 2001
Document created.
Issue 2
March, 2001
Modified voltage tolerances for VDD and VDDI.
Modified CPUMODE2 connection (tied to VDD rather than GND).
Minor editorial changes.
Issue 3
July, 2001
• Removed I2C references throughout to reflect the fact that I2C is not
supported.
• Changed Figure 3-1 on page 7: changed GND to VSS and VCC to
VDD to match labels used in pin descriptions.
• Text edits in Section 5.1 on page 16.
• Modified procedure for Programming the WAIT_N Register
(Section 5.1.2 on page 23).
• Inserted text and diagram regarding relative timing of SPI inputs in
Section 5.3 on page 26.
• Added section (Section 5.4.2 on page 31) describing bug affecting
Power_Attenuator_Delay and Power_Correction_Delay circuits. Modified Figure 5-25 on page 33 to reflect this issue.
• Revision number incremented to 1; i.e., rev_code changed to
178000CD. Affects Section 5.6 on page 34 and Table 6-3 on page 41.
• Changed VT+ and VT- values to 2.2V min and 0.8V max, respectively,
in DC Characteristics. Also, changed VTH to 0.87V typ.
• IIH text edit in Table 8-1 on page 51.
• added IDDOP (VDDI) and IDDOP (VDDO) in DC Characteristics.
• Changed notes at start of AC Timing.
• Removed Relative Timing Diagrams and table for serial interface in AC
Timing.
• Changed min/max loading from 0/40pF to 15/30pF on toe, tdp, toz,
and trp, in Table 9-2 on page 54; toe, in Table 9-3 on page 55; and toe,
top, and toz in Table 9-7 on page 59.
Issue 4
May, 2002
Added patent numbers, corrected connections to DSP, added GPIO 18.
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Issue No.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
PMC-Sierra, Inc.
Released
Digital Correction Signal Processor
PM7800 PALADIN-10
Data Sheet
ISSUE 4
Digital Correction Signal Processor
PM
PMC-2001646
:49
:25
CONTENTS
11
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
02
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 PALADIN Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 PALADIN-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3.1 System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3.2 Signal Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 PM7800 DCSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4.2 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4.4 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4.5 Patent Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1 CPU, Address Decoder and Miscellaneous Interfaces . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1.1 Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.2 Programming the WAIT_N Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2 Data Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2.1 VREF Interface and FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2.2 VOBS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2.3 VD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2.4 Dual-Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2.5 Single-Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3.1 Serial Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.4 Hop Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.4.1 Power and Carrier Values and Hop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.4.2 Bug that affects Power_Attenuator_Delay and Power_Correction_Delay . . . 31
5.5 GPIO Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.5.1 Status Output Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.5.2 Power Attenuator Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.5.3 Watchdog Timer Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.6 JTAG Test Access Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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6 Test Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
i
PMC-Sierra, Inc.
Released
Digital Correction Signal Processor
PM7800 PALADIN-10
Data Sheet
ISSUE 4
Digital Correction Signal Processor
PM
PMC-2001646
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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6.1 Full Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.2 RAMBIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.3 OE_N Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.4 JTAG Boundary Scan, IEEE 1149.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.4.1 TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.4.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.4.2.1 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.4.2.2 Identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.4.2.3 Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.4.3 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.4.4 Boundary Scan Cells
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
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8 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
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9 AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.1 RESET_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.2 CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.3 VREF, VOBS, VD Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.3.1 Dual-Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.3.2 Single-Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
9.4 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9.4.1 Serial Interface AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9.5 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.6 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
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10 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
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11 Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
ii
PMC-Sierra, Inc.
Released
Digital Correction Signal Processor
PM7800 PALADIN-10
Data Sheet
ISSUE 4
Digital Correction Signal Processor
PM
PMC-2001646
:25
LIST OF TABLES
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin Description and Cell Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PM7800 Connections to C54xx Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PM7800 Connections to Address Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Miscellaneous PM7800 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Functional Timing for WAIT_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Programming the WAIT_N Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Full-Scan Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Input Observation Cell (IN_CELL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
D.C.Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
RESET_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
CPU Interface - DCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
CPU Interface - CPUCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Dual-Clock System timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Single-Clock System timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
AC Timing for Serial Inputs (SCLK, SCS_N, SD, HOP_N) . . . . . . . . . . . . . . . 58
GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
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Table 1-1
Table 4-1
Table 5-1
Table 5-2
Table 5-3
Table 5-4
Table 5-5
Table 6-1
Table 6-2
Table 6-3
Table 6-4
Table 7-1
Table 8-1
Table 9-1
Table 9-2
Table 9-3
Table 9-4
Table 9-5
Table 9-6
Table 9-7
Table 9-8
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
iii
PMC-Sierra, Inc.
Released
Digital Correction Signal Processor
PM7800 PALADIN-10
Data Sheet
ISSUE 4
Digital Correction Signal Processor
PM
PMC-2001646
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System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
PM7800 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Diagram (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
CPU, Address Decoder and Miscellaneous Interfaces. . . . . . . . . . . . . . . . . . . . 16
Read Cycle (CPUMODE0 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Read Cycle (CPUMODE0 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Back-to-Back Read Cycles (CPUMODE0 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . 20
Back-to-Back Read Cycles (CPUMODE0 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . 20
Back-to-Back Write Cycles (CPUMODE0 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . 21
Back-to-Back Write Cycles (CPUMODE0 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . 21
WAIT_N Timing - Reads (CPUMODE0 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . 22
WAIT_N Timing - Reads (CPUMODE0 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 22
WAIT_N Timing - Writes (CPUMODE0 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . 22
WAIT_N Timing - Writes (CPUMODE0 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Data Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Dual-Clock System timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Single-Clock System timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Serial (SPI), Hop, and GPIO Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Relative Timing of SPI Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SPI carrier_stream (spi_clock_polarity = 0, falling edge of SCLK is active) . . 28
SPI carrier_stream (spi_clock_polarity = 1, rising edge of SCLK is active) . . . 28
SPI power_stream (spi_clock_polarity = 0, falling edge of SCLK is active) . . . 28
SPI power_stream (spi_clock_polarity = 1, rising edge of SCLK is active) . . . 28
SPI word_stream (spi_clock_polarity = 0, falling edge of SCLK is active) . . . 29
SPI word_stream (spi_clock_polarity = 1, rising edge of SCLK is active) . . . . 29
SPI hop_stream (spi_clock_polarity = 0, falling edge of SCLK is active) . . . . . 29
SPI hop_stream (spi_clock_polarity = 1, rising edge of SCLK is active) . . . . . 30
Power Attenuator Outputs - shown with active-low pulse on GPIO17 . . . . . . . 33
Watchdog Timer Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
JTAG and Scan Test Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Boundary-Scan Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
TAP Controller Finite State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Output Cell (OUT_CELL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Bi-directional Cell (IO_CELL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Layout of Output Enable and Bidirectional Cells . . . . . . . . . . . . . . . . . . . . . . . . 49
RESET_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
CPU Interface - DCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
CPU Interface - CPUCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Dual-Clock System timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Single-Clock System timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
AC Timing for Serial Inputs (SCLK, SCS_N, SD, HOP_N) . . . . . . . . . . . . . . . 58
GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
wn
Do
Figure 1-1
Figure 2-1
Figure 3-1
Figure 5-1
Figure 5-2
Figure 5-3
Figure 5-4
Figure 5-5
Figure 5-6
Figure 5-7
Figure 5-8
Figure 5-9
Figure 5-10
Figure 5-11
Figure 5-12
Figure 5-13
Figure 5-14
Figure 5-15
Figure 5-16
Figure 5-17
Figure 5-18
Figure 5-19
Figure 5-20
Figure 5-21
Figure 5-22
Figure 5-23
Figure 5-24
Figure 5-25
Figure 5-26
Figure 5-27
Figure 6-1
Figure 6-2
Figure 6-3
Figure 6-4
Figure 6-5
Figure 9-1
Figure 9-2
Figure 9-3
Figure 9-4
Figure 9-5
Figure 9-6
Figure 9-7
:25
LIST OF FIGURES
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PMC-Sierra, Inc.
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Data Sheet
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Digital Correction Signal Processor
PM
PMC-2001646
JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
tem
be
r,
20
02
11
:49
:25
Figure 9-8
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PMC-Sierra, Inc.
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Digital Correction Signal Processor
PM7800 PALADIN-10
Data Sheet
ISSUE 4
Digital Correction Signal Processor
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
tem
be
r,
20
02
11
:49
:25
PM
PMC-2001646
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PMC-Sierra, Inc.
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Digital Correction Signal Processor
PM7800 PALADIN-10
Data Sheet
ISSUE 4
Digital Correction Signal Processor
PM
PMC-2001646
:25
1 Introduction
11
:49
This document describes the features, functionality, and physical characteristics of the PM7800
Digital Correction Signal Processor, which forms part of the PALADIN-10 system.
20
02
1.1 Definitions
Definitions
Abbreviation
Definition
ep
Table 1-1
tem
be
r,
The following table defines the terms and abbreviations used in this data sheet.
Adaptive Control Processing Compensation Engine
ADC
Analog to Digital Converter
AQM
Analog Quadrature Modulator
BGA
Super Ball Grid Array, the type of package used by this chip
BIST
Built-In Self-Test
BTS
Base Transceiver Station
(Node B in WCDMA)
CMOS
Complementary Metal Oxide Semiconductor
CPU
Central Processing Unit - in this context, the CPU is the ACPCE and the terms are used interchangeably
DAC
Digital to Analog Converter
DCSP
Digital Correction Signal Processor
DQM
Digital Quadrature Modulator
DSP
Digital-Signal Processor
EDGE
Enhanced Data Rates for GSM Evolution - 3rd generation GSM
(Global System for Mobile Communications)
FIFO
First-In, First-Out - a queuing mechanism
GPIO
General-Purpose Input-Output pin
GSM
Global System for Mobile Communications
RRME
WCDMA
,1
ay
rsd
hu
nT
io
ett
liv
fo
uo
ef
inv
yV
db
de
loa
wn
RAM
Do
NC
9S
ACPCE
No Connect, indicates an unused pin
Random-Access Memory
Radio Resource Management Entity
Wideband Code Division Multiple Access
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PM7800 PALADIN-10
Data Sheet
Digital Correction Signal Processor
PM
ISSUE 4
PMC-2001646
:25
1.2 PALADIN Technologies
20
02
11
:49
PALADIN is a family of distortion elimination chip technologies that enables the development of
higher performance, higher efficiency 2G and 3G base stations that utilize fewer and less expensive
components. Based on proprietary Digital Signal Processing (DSP) architectures and techniques,
PALADIN products feature:
tem
be
r,
• Digital Adaptive Predistortion for wideband amplifier linearization;
• Digital Correction for Analog Quadrature Modulation (AQM) distortion; and
• Constant-Gain Mode to facilitate operation at higher efficiency.
rsd
ay
,1
9S
ep
Emerging 3G wireless services require high capacity radio networks to deliver the high volume
multi-media data traffic that is central to the new "wireless internet" paradigm. High spectral
efficiency, the ability to maximize the data-carrying capacity of a limited amount of licensed
spectrum, will be key to the success of 3G radio networks. However, spectral efficiency is
fundamentally limited by distortion in the analog transmitter and power amplifier components of
the Base Transceiver Station (BTS).
liv
ett
io
nT
hu
PALADIN products eliminate distortion in the transmitter chain and power amplifier using fully
digital methods, permitting designers to replace many expensive and difficult to manufacture
analog IF and RF sub-systems, components which are often required to control distortion and
aggregate signals in many existing BTS designs.
de
1.3 PALADIN-10
db
yV
inv
ef
uo
fo
In particular, PALADIN can transform an inexpensive, simple, narrow-band Class AB power
amplifier into a wide-band, multi-carrier capable, high efficiency, digitally controlled amplifier
unit which can replace the expensive, low efficiency, feedforward-based multi-carrier power
amplifiers (MCPA) commonly used in many current 3G BTS designs. Furthermore, PALADIN
opens the door to the development of new BTS architectures that could feature "standard sockets"
for multiple air interfaces, multiple transmitter/amplifier "hot swap" redundancy, multiple
amplifier efficiency management, and smart antenna transceivers.
Do
wn
loa
PALADIN-10 is a wideband transceiver linearizer and distortion elimination chip solution for
multi-carrier high power radio transmitter applications. Based on high speed digital signal
processing (DSP), PALADIN-10 provides digital adaptive predistortion and preconditioning for
complex modulation signals with instantaneous bandwidths up to 10MHz. PALADIN-10 consists
of (1) the PM7800 Digital Correction Signal Processor (DCSP) chip and (2) the Adaptive Control
Processor Compensation Engine (APCE) running on an industry-standard programmable DSP1.
1. TMS320C54xx
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:25
1.3.1 System Diagram
tem
be
Basestation
Modem
r,
20
02
11
:49
Figure 1-1 shows a simplified system diagram of PALADIN-10 operating in the transmitter chain
of a typical multi-carrier base transceiver subsystem (BTS).
Vobs
hu
RF Downconverter
Observation Signal Path
PALADIN
Adaptive Control
SPI
Processor
Compensation Engine
(ACPCE)
nT
Command Interface
Main
Amp
io
local
BTS Controller
BSC or RRME
rsd
ay
CPU
RF Upconverter
9S
GPIO
SPI
HOP
VD
ep
PM7800
PALADIN-10
DCSP
,1
Vref
ADC
Baseband signal
DAC
Open Loop Predistortion
Signal Path
fo
liv
ett
TMS320C5410
System Diagram
yV
inv
ef
uo
Figure 1-1
Do
wn
loa
de
db
The PM7800 DCSP chip, also called the PALADIN predistortion kernel, is responsible for all the
real-time operations on the complex modulation baseband signal, from the base station modem,
that predistort and precondition it such that the modified signal at the main or power amplifier (PA)
will cancel out the distortions due to non-linearities in the PA and transmitter chain. The PM7800
DCSP chip supports all 3G and 2G air interfaces, including WCDMA, cdma2000 and IS-95, and
GSM/EDGE. The PM7800 DCSP chip is the very high speed “hardware” digital signal processor
component of the PALADIN-10 system.
The PALADIN ACPCE, also called the PALADIN predistortion firmware, is responsible for
carrying out all the nonreal-time complex computations necessary to generate predictive
parameters used inside the PM7800 DCSP. The PALADIN ACPCE is also responsible for control
functions and acts as the Master, taking commands from the base station controller (BSC) or some
radio resource management entity (RRME) and controlling the operation and functioning of the
PM7800 DCSP chip. The ACPCE runs on an external programmable DSP processor chip
(TMS320C5410), also referred to as the CPU. The ACPCE is fully software upgradeable via a
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Data Sheet
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Digital Correction Signal Processor
PM
PMC-2001646
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:49
:25
serial interface from the BSC or RRME. The current version of the ACPCE supports the WCDMA
air interface standard only. Versions supporting the other 2G and 3G air standards will be provided
as software updates. The PALADIN-10 ACPCE is the highly complex adaptive “software” digital
signal processor component of the PALADIN-10 system.
tem
be
r,
The signal flow through the PALADIN-10 system is as follows:
20
02
1.3.2 Signal Flow
rsd
ay
,1
9S
ep
In the forward direction, the composite (digitally combined single or multi-carrier complex
baseband) signal from the base station modem enters the PM7800 through the Vref port, where it
is interpolated to the correct rate, predistorted by the Digital Correction Signal (DCSP) Processor
core using parameters provided by the Adaptive Control Processor Compensation Engine
(ACPCE), and exits through the VD port. The predistorted signal output at the VD port is converted
to analog, up-converted, amplified, and applied to the antenna. This is called the open-loop
predistortion signal path, which is sometimes referred to as the transmit path or upconversion path.
fo
liv
ett
io
nT
hu
In the reverse direction, a small portion of the amplified signal is downconverted, re-sampled and
re-digitized, and enters the PM7800 through the Vobs port. This is called the observation or
sampling signal path, and is sometimes referred to as the downconversion path. The PM7800
concurrently captures the baseband signal (Vref) and observed signal (Vobs) for analysis by the
Adaptive Control Processor Compensation Engine (running on a TMS320C5410 DSP). The CPU
analyzes the captured data to monitor system performance, and adjusts the internal parameters of
the PM7800 DCSP accordingly.
uo
1.4 PM7800 DCSP
yV
inv
ef
The PM7800 DCSP chip is the very high speed “hardware” digital signal processor component of
the PALADIN-10 system. The remainder of this document describes the PM7800 DCSP chip only.
wn
predistortion kernel for linearization of power-amplifiers in wireless base-stations
up to 80MHz data-rate
interpolated up-conversion (1:N, where 1<=N<=10) of baseband input to the data-rate
generic 16-bit microprocessor bus interface for configuration, control, and monitoring
SPI serial interface for update of power and carrier values
48 general-purpose IO pins, eight of which are edge-triggered interrupt sources
standard five-signal IEEE 1149.1 JTAG test port for boundary scan board test purposes
low-power 1.8V CMOS core logic with 3.3V CMOS/TTL compatible digital inputs and
digital outputs
• Industrial temperature range (-40C to +85C)
Do
•
•
•
•
•
•
•
•
loa
1.4.1 Features
de
db
The ACPCE is described in a companion document: PMC-2002272, “PALADIN-10/PALADIN15 ACPCE Firmware User Manual.”
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Data Sheet
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Digital Correction Signal Processor
PM
PMC-2001646
:25
1.4.2 Interfaces
11
r,
20
02
Baseband interface to the base station modem (Vref)
Digital IF or Digital Baseband interface to DAC(s) and RF Upconverter (VD)
Digital IF or Digital Baseband interface from ADC(s) and RF Downconverter (Vobs)
GPIO and Serial (SPI) interface for auxiliary monitor and control
CPU interface to ACPCE processor (external C54xx DSP)
tem
be
•
•
•
•
•
:49
The major interfaces to the PM7800 DCSP include:
9S
ep
Note: The command interface to the BSC or RRME is through an SPI (serial) interface on the CPU
(TMS320C5410). The command interface is separately detailed in the companion document:
PMC-2002272, “PALADIN-10/PALADIN-15 ACPCE Firmware User Manual.”
,1
1.4.3 Applications
nT
hu
rsd
ay
• WCDMA Base Transceiver Subsystems (BTS)
• CDMA2000 BTS (requires firmware upgrade)
• GSM/TDMA/EDGE BTS (requires firmware upgrade)
ett
io
1.4.4 References
liv
1. TMS320VC5410 Fixed-Point Digital Signal Processor (Texas Instruments)
uo
fo
2. Section 8: Synchronous Serial Peripheral Interface, M68HC11 Reference Manual
(Motorola)
inv
ef
3. PMC-2002272, “PALADIN-10/PALADIN-15 ACPCE Firmware User Manual.”
yV
1.4.5 Patent Information
wn
loa
de
US Patent 5,990,734
US Patent 5,990,738
US Patent 6,054,894
US Patent 6,054,896
US Patent 6,342,810
US Patent 6,356,146 B1
Do
•
•
•
•
•
•
db
The technology discussed in this document is protected by the following Patents:
Other relevent Patents and Patent Applications may also exist.
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PMC-Sierra, Inc.
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Digital Correction Signal Processor
PM7800 PALADIN-10
Data Sheet
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Digital Correction Signal Processor
PM
PMC-2001646
:25
2 Block Diagram
02
11
:49
A block diagram of the PM7800 DCSP, showing the major interfaces is shown below as:
V
V
ref
D
vd_i[15:0]
vd_q[15:0]
tem
be
vref_i[15:0]
vref_q[15:0]
from
Baseband Modem
fo
dat[15:0]
strb1_n
strb2_n
cpuclk
uo
(MSTRB*)
R/(W*)
inv
ef
CLKOUT
yV
nT
liv
adr[17:0]
cs1_n
cs2
cpumode[4:0]
ep
gpio[23:0]
gpio[47:24]
hop_n
sd
sclk
scs_n
tck
trstb
tms
tdi
tdo
scansel
scanen
oe_n
JTAG
Scan Test
PM7800 Block Diagram
Do
wn
loa
de
Figure 2-1
CPU Interface
ett
A18-A16
A14-A0
D15-D0
db
io
wait_n
irq_n
READY
(INT3*)
hu
cs0_n
(PS*)
from
ACPCE
(TMS320C54xx)
rsd
ay
,1
dclk
refclk
from
Address
Decoder
vobs_i[15:0]
9S
obs
to
DAC(s) & RF
from
ADC(s) & RF
vobs_q[15:0]
V
reset_n
mute_n
r,
vd_fmt
20
PM7800 DCSP
3 Pin Diagram
The PM7800 is packaged in a 304-pin SBGA with a body size of 31mm x 31mm. The following
pin diagram shows the pinout from the ball-side of the package. Note that, for readability, the
aspect ratio of the diagram has been changed.
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NC
NC
VD_Q13
VD_Q10
VD_Q8
VD_Q4
VSS
DCLK
NC
VDDI
VSS
VD_Q5
VSS
VD_I2
VD_I3
VDD
VD_I6
VDDI
VDD
VD_I8
VD_I9
VSS
VD_I12
VSS
VSS
VD_I14
VD_I15
MUTE_N
GPIO0
VSS
GPIO45
GPIO5
GPIO3
GPIO46
GPIO6
GPIO4
GPIO47
VSS
GPIO7
VD_Q0
VDD
VSS
GPIO42
VSS
VDD
ADR0
GPIO43
CPUMODE3
VDD
VDDI
VDD
VD_Q2
VD_Q6
VDD
VD_Q11
VD_Q14
VDD
VD_I0
VD_I4
VDD
VD_I10
GPIO1
VDD
VDDI
VDD
VD_FMT
GPIO10
VDDI
ADR2
ADR1
GPIO44
GPIO8
GPIO11
VDDI
VSS
ADR3
ADR4
VDD
VDD
ADR5
ADR6
ADR7
ADR8
VSS
ADR9
ADR10
ADR11
VDDI
15
ADR12
ADR13
ADR14
VDD
VDDI
ADR15
ADR16
ADR17
CPUCLK
CS0_N
CS1_N
CS2
VOBS_I15
11
VSS
STRB1_N
STRB2_N
VDD
WAIT_N
IRQ_N
DAT0
DAT1
DAT2
DAT3
DAT4
DAT5
9
VDDI
DAT6
DAT7
VDD
VSS
DAT8
DAT9
DAT10
7
VSS
6
VDDI
5
DAT11
DAT12
DAT13
DAT14
VDD
VSS
DAT15
GPIO41
VDD
GPIO18
GPIO16
VDDI
GPIO38
GPIO39
GPIO40
RESET_N
GPIO26
GPIO21
VDD
VSS
GPIO20
3
GPIO28
GPIO27
GPIO23
VSS
VDD
VSS
2
VSS
VDDI
GPIO25
GPIO22
VSS
VDD
1
VREF_I2
VREF_I5
VREF_I7
VREF_Q14 VREF_Q15
VREF_I1
VREF_I4
VREF_I6
VREF_I10 VREF_I11
VSS
REFCLK
VDDI
VREF_I8
VSS
GPIO37
CPUMODE2
GPIO36
VSS
VDD
CPUMODE0
GPIO30
VSS
VDD
VSS
GPIO33
GPIO31
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
VDD
VSS
GPIO35
GPIO34
AC
AB
:49 Y
:A2A5
GPIO32
VSS
VREF_Q0
VSS
VREF_Q5
VREF_Q9
11
GPIO29
SCLK
VREF_Q3
VREF_Q4
VREF_Q8
02
VDDI
SCS_N
VREF_Q2
VDDI
VREF_Q7
20
CPUMODE1
VDD
SD
VDD
HOP_N
r,
VREF_Q1
VDD
VREF_Q6
VREF_Q10 VREF_Q11 VREF_Q12 VREF_Q13
VDD
VREF_I0
VREF_I3
VDD
VREF_I9
VREF_I12 VREF_I13 VREF_I14 VREF_I15
VDD
GPIO24
VDD
GPIO19
GPIO17
GPIO15
4
tem
be
ep
9S
VOBS_Q9
VOBS_Q10 VOBS_Q13
VOBS_Q11 VOBS_Q14 VOBS_Q15
VOBS_Q12
,1
VOBS_Q6
VOBS_Q7
VOBS_Q8
VSS
8
ay
rsd
VDD
VOBS_Q3
VOBS_Q4
VOBS_Q5
hu
VDDI
VOBS_Q0
VOBS_Q1
VOBS_Q2
10
nT
io
VOBS_I12
ett
VDD
VOBS_I10 VOBS_I13
VOBS_I11 VOBS_I14
VSS
12
liv
fo
VOBS_I6
VOBS_I7
VOBS_I8
VOBS_I9
13
uo
VOBS_I2
VOBS_I3
VOBS_I4
VOBS_I5
14
ef
inv
VDD
VOBS_I0
VOBS_I1
yV
TCK
TRSTB
TMS
VSS
16
db
GPIO14
de
TDI
GPIO13
loa
SCANSEL
17
SCANEN
VSS
18
TDO
wn
OE_N
Do
GPIO12
19
PM
PMC-Sierra, Inc.
CPUMODE4
NC
NC
VD_Q3
VD_Q7
VD_Q9
VD_Q12
VD_Q15
NC
VD_I1
VD_I5
VD_I7
VD_I11
VD_I13
GPIO2
NC
NC
VDD
VSS
GPIO9
20
ISSUE 4
VD_Q1
VSS
VDD
21
Pin Diagram (Bottom View)
PMC-2001646
VSS
22
23
Figure 3-1
Released
Digital Correction Signal Processor
PM7800 PALADIN-10
Data Sheet
Digital Correction Signal Processor
PMC-Sierra, Inc.
Released
Digital Correction Signal Processor
PM7800 PALADIN-10
Data Sheet
ISSUE 4
Digital Correction Signal Processor
PM
PMC-2001646
Pin Name
Type
Pin #
:49
Pin Description and Cell Types
Default
Functional Description
02
CPU Interface (47)
11
Table 4-1
:25
4 Pin Description
I
AB12
Hi-Z
This signal is either used as an access strobe or as a write strobe, depending on the setting of the CPUMODE0 pin. If the CPUMODE0 pin is connected to VSS, this signal is treated as an access strobe, if the
CPUMODE0 pin is connected to VDD, then this strobe is treated as a
WRITE_N strobe.
STRB2_N
I
AA12
Hi-Z
This signal is either used as an Read/Write_N cycle type indication or as a
read strobe, depending on the setting of the CPUMODE0 pin. If the
CPUMODE0 pin is connected to VSS, this signal is treated as an
Read/Write_N indication, if the CPUMODE0 pin is connected to VDD, then
this strobe is treated as a READ_N strobe.
CS0_N
I
AB13
Hi-Z
This signal is an active-low chip select. All three chip selects must be
asserted for the chip to be accessed.
CS1_N
I
AA13
Hi-Z
This signal is an active-low chip select. All three chip selects must be
asserted for the chip to be accessed.
CS2
I
Y13
Hi-Z
This signal is an active-high chip select. All three chip selects must be
asserted for the chip to be accessed.
ADR[17:0]
I
Y14,
AA14,
AB14,
AA15,
AB15,
AC15,
Y16,
AA16,
AB16,
Y17,
AA17,
AB17,
AC17,
AA18,
AB18,
AB19,
AA19,
AC20
Hi-Z
This is the eighteen-bit word-address bus. The bus addresses 256k 16-bit
words (512Kbytes) in the PM7800.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
tem
be
r,
20
STRB1_N
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PM7800 PALADIN-10
Data Sheet
Pin Name
Type
Pin #
Default
:25
Pin Description and Cell Types
Functional Description
:49
Table 4-1
Digital Correction Signal Processor
PM
ISSUE 4
PMC-2001646
IO
AB6,
Y7,
AA7,
AB7,
AC7,
Y8,
AA8,
AB8,
AA9,
AB9,
Y10,
AA10,
AB10,
AC10,
Y11,
AA11
Hi-Z
This is the 16-bit data bus.
WAIT_N
O
AC11
Output
High
This is the external wait signal, required when DCLK on the PM7800 is
slow. This output has programmable timing. See Programming the WAIT_N
Register section 5.1.2.
IRQ_N
O
AB11
Output
High
This is an active-low interrupt request pin.
CPUCLK
I
AC13
Hi-Z
CPU Clock Input. This is a Schmitt-trigger input.
CPUMODE0
I
Y3
Hi-Z
This pin configures the strobe-signalling mode of the PM7800. See CPU,
Address Decoder and Miscellaneous Interfaces section 5.1.
CPUMODE1
I
AA4
Hi-Z
CPUMODE2
I
AB4
Hi-Z
CPUMODE3
I
AA20
CPUMODE4
I
If this pin is connected to VDD, the WAIT circuit deactivates the internal version of the CPU write strobe for a programmable number of CPUCLK
cycles. See CPU, Address Decoder and Miscellaneous Interfaces
section 5.1.
This input is reserved and must be connected to VDD.
This pin selects a mode of operation that can be used to support processors, that require the read strobe and write strobe to be sampled on a specific edge of CPUCLK. See CPU, Address Decoder and Miscellaneous
Interfaces section 5.1.
Y21
Hi-Z
This pin enables additional delay on the WAIT_N output to provide more
hold time. See CPU, Address Decoder and Miscellaneous Interfaces
section 5.1.
I
N23
Hi-Z
Data clock. This is a Schmitt-trigger input.
I
L1
Hi-Z
VREF clock. This is a Schmitt-trigger input. VREF is synchronous to this
clock in 2-clock systems.
loa
de
yV
Hi-Z
db
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
tem
be
r,
20
02
11
DAT[15:0]
REFCLK
Do
DCLK
wn
Data Interfaces (98)
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PM7800 PALADIN-10
Data Sheet
Pin Name
Type
Pin #
Default
:25
Pin Description and Cell Types
Functional Description
:49
Table 4-1
Digital Correction Signal Processor
PM
ISSUE 4
PMC-2001646
IO
G1,
G2,
G3,
G4,
H2,
H3,
H4,
J1, J2,
J3,
K2,
K3,
K4,
L2,
L3, L4
Hi-Z
In normal modes, this bus is the I-channel of the baseband input signal.
In scan test mode, this bus is an output used for SCANOUT[31:16].
VREF_Q[15:0]
IO
M2,
M3,
N1,
N2,
N3,
N4,
P1,
P2,
P3,
P4,
R1,
R2,
T2,
T3,
T4, U1
Hi-Z
In normal modes, this bus is the Q-channel of baseband input signal.
In scan test mode, this bus is an output used for SCANOUT[15:0].
VOBS_I[15:0]
I
A11,
B11,
C11,
D11,
B12,
C12,
A13,
B13,
C13,
D13,
A14,
B14,
C14,
D14,
B15,
C15
Hi-Z
Input: I-channel of observed signal from power amplifier.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
tem
be
r,
20
02
11
VREF_I[15:0]
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PMC-Sierra, Inc.
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Data Sheet
Pin Name
Type
Pin #
Default
:25
Pin Description and Cell Types
Functional Description
:49
Table 4-1
Digital Correction Signal Processor
PM
ISSUE 4
PMC-2001646
I
B5,
B6,
C6,
A7,
B7,
C7,
D7,
B8,
C8,
D8,
A9,
B9,
C9,
A10,
B10,
C10
Hi-Z
Input: Q-channel of observed signal from power amplifier.
VD_I[15:0]
IO
G23,
G22,
G21,
H22,
H21,
H20,
J23,
J22,
J21,
K22,
K21,
K20,
L23,
L22,
L21,
L20
Hi-Z
In normal modes, this bus is the I-channel of output signal to the DAC.
In scan test mode, this bus is an input used for SCANIN[31:16].
VD_Q[15:0]
IO
N21,
N20,
P22,
P21,
P20,
R22,
R21,
T22,
T21,
T20,
U23,
U22,
U21,
U20,
V22,
W23
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
tem
be
r,
20
02
11
VOBS_Q[15:0]
In normal modes, this bus is the Q-channel of output signal to the DAC.
In scan test mode, this bus is an input used for SCANIN[15:0].
Do
wn
loa
de
db
yV
inv
Hi-Z
Serial Port (4)
SD
I
W4
Hi-Z
Serial Data input for the serial port. If unused, this pin must be connected to
VSS.
SCLK
I
U2
Hi-Z
Clock input for the serial port - Schmitt trigger.
If unused, this pin must be connected to VSS.
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PMC-Sierra, Inc.
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PM7800 PALADIN-10
Data Sheet
Pin Name
Type
Pin #
Default
:25
Pin Description and Cell Types
Functional Description
:49
Table 4-1
Digital Correction Signal Processor
PM
ISSUE 4
PMC-2001646
I
U3
Hi-Z
Chip Select for the serial port. This is a Schmitt-trigger input.
If unused, this pin must be connected to VSS.
HOP_N
I
U4
Hi-Z
This input can be used to activate the new carrier and power values. This is
a Schmitt-trigger input.
If unused, this pin must be connected to VSS.
20
02
11
SCS_N
tem
be
r,
JTAG and other test pins (8)
I
D16
Hi-Z
JTAG clock.
In normal operation, this pin must be connected to VSS.
TRSTB
I
C16
Hi-Z pulled
high
JTAG reset signal - active low. This is a Schmitt-trigger input with internal
pull-up resistor.
In normal mode (non-JTAG) this pin must be connected to RESET_N.
TMS
I
B16
Hi-Z pulled
high
JTAG test mode select input with internal pull-up resistor.
In normal operation, this pin must be driven high or left unconnected.
TDI
I
C17
Hi-Z pulled
high
JTAG test data input with internal pull-up resistor.
In normal operation, this pin must be driven high or left unconnected.
TDO
O
B18
Hi-Z
Tri-state output for JTAG test data. This is the only pin unaffected by OE_N.
SCANSEL
I
A17
Hi-Z
Scan MUX select. When high, this signal selects Scan test mode.
This pin must be connected to VSS in normal operation.
SCANEN
I
B17
Hi-Z
When high, this signal enables the Scan chain.
This pin must be connected to VSS in normal operation.
OE_N
I
A19
Hi-Z pulled
low
RESET_N
I
F3
MUTE_N
I
AA23
VD_FMT
I
Forces all pins except TDO to high impedance. This is a Schmitt-trigger
input with internal pull-down resistor.
In normal operation, this pin must be driven low or left unconnected.
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
TCK
ef
Miscellaneous (50)
System reset signal - active low. This is a Schmitt-trigger input with internal
pull-up resistor.
Hi-Z pulled
high
Mute input - active-low. When low, this signal forces VD to zero. This is a
Schmitt-trigger input with internal pull-up resistor.
Hi-Z
Configuration pin that sets the data format of the VD_I and VD_Q outputs:
0 -> offset-binary
1 -> 2s-complement.
db
yV
inv
Hi-Z pulled
high
Do
wn
loa
de
C20
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC-Sierra, Inc.
Released
Digital Correction Signal Processor
PM7800 PALADIN-10
Data Sheet
Pin Name
Type
Pin #
Default
:25
Pin Description and Cell Types
Functional Description
:49
Table 4-1
Digital Correction Signal Processor
PM
ISSUE 4
PMC-2001646
IO
W22,
Y23,
Y22,
Y19,
AB20,
AC21,
AA6,
Y5,
AA5,
AB5,
AC4,
AC3,
AA1,
Y1,
Y2,
W1
Hi-Z
General-purpose IO pins.
GPIO[31:28]
IO
W2,
W3,
V2,
F2
Hi-Z
General-purpose IO pins with rising-edge interrupt capability (see
Interrupt_Enable2 register).
GPIO[27:24]
IO
E2,
E3,
D1,
E4
Hi-Z
General-purpose IO pins with falling-edge interrupt capability (see
Interrupt_Enable2 register).
GPIO[23:19]
IO
D2,
C1,
D3,
A3,
C4
Hi-Z
GPIO[18]
IO
D5
Hi-Z
GPIO[17]
IO
B4
GPIO[16]
IO
GPIO[15:0]
IO
02
20
r,
tem
be
ep
9S
,1
ay
rsd
hu
nT
ett
io
inv
ef
uo
fo
liv
General-purpose IO pins.
General-purpose IO pins or a maskable Status Interrupt output for the Base
Station Interface.
General-purpose IO pins or Power_Attenuator_Pulse output (see
GPIO_Secondary_Function_Select registers).
C5
Hi-Z
General-purpose IO pins or Watchdog_Timer_Output (see
GPIO_Secondary_Function_Select registers).
A4,
D17,
C18,
A20,
C19,
B20,
A21,
D19,
C23,
D22,
E22,
D23,
E23,
F21,
G20,
F22
Hi-Z
General-purpose IO pins or Power_Attenuator_Output[15:0] (see
GPIO_Secondary_Function_Select registers).
yV
Hi-Z
db
de
loa
wn
Do
11
GPIO[47:32]
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PMC-Sierra, Inc.
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Digital Correction Signal Processor
PM7800 PALADIN-10
Data Sheet
Pin Name
Type
Pin #
Default
:25
Pin Description and Cell Types
Functional Description
:49
Table 4-1
Digital Correction Signal Processor
PM
ISSUE 4
PMC-2001646
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
tem
be
r,
20
02
Ground supply.
uo
A2
A6
A8
A12
A16
A18
A22
B1
B3
B21
B23
C2
C22
F1
F23
H1
H23
M1
M23
T1
T23
V1
V23
AA2
AA22
AB1
AB3
AB21
AB23
AC2
AC6
AC8
AC12
AC16
AC18
AC22
ef
P
Do
wn
loa
de
db
yV
inv
VSS
11
Power Supply (84)
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PM7800 PALADIN-10
Data Sheet
:49
11
02
20
r,
tem
be
ep
9S
,1
ay
rsd
E20,
K23,
R23,
W20,
AC19,
AC14
AC9,
AC5,
V3,
R3,
K1,
E1,
A5,
D10,
A15,
B19
hu
P
nT
VDDI
3.3V IO voltage supply.
io
A1
A23
B2
B22
C3
C21
D4
D6
D9
D12
D15
D18
D20
F4
F20
J4
J20
M4
M20
R4
R20
V4
V20
Y4
Y6
Y9
Y12
Y15
Y18
Y20
AA3
AA21
AB2
AB22
AC1
AC23
ett
P
Functional Description
1.8V Core voltage supply.
Do
wn
loa
de
db
yV
inv
VDD
Default
liv
Pin #
fo
Type
uo
Pin Name
:25
Pin Description and Cell Types
ef
Table 4-1
Digital Correction Signal Processor
PM
ISSUE 4
PMC-2001646
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PM7800 PALADIN-10
Data Sheet
Digital Correction Signal Processor
PM
ISSUE 4
PMC-2001646
:26
5 Functional Description
A18-A16
A14-A0
D15-D0
dat[15:0]
strb1_n
strb2_n
cpuclk
(MSTRB*)
R/(W*)
rsd
ay
CLKOUT
tem
be
9S
adr[17:0]
,1
ACPCE
(TMS320C54xx)
ep
wait_n
irq_n
READY
(INT3*)
CPU Interface
cs0_n
(PS*)
r,
PM7800 DCSP
Address
Decoder
20
02
11
:49
5.1 CPU, Address Decoder and Miscellaneous Interfaces
CPU, Address Decoder and Miscellaneous Interfaces.
liv
ett
io
Figure 5-1
nT
hu
cs1_n
cs2
cpumode[4:0]
inv
ef
uo
fo
The CPU interface is designed to “look” like the interface to a slow asynchronous SRAM device,
with some added functionality to reduce glue logic. The CPU interface is primarily designed for a
TI TMS320C54xx General Purpose DSP processor, but some flexibility is provided to support
other processors.
Do
wn
loa
de
db
yV
Internally, the CPU access cycle is synchronized to the DCLK to allow a simultaneous CPU write
to, and data path read from, the same memory location - this is to provide fail-safe operation of the
internal dual-port RAM. This requirement significantly slows down the access speed of the CPU
interface, especially at EDGE sample clock rates in the 13MHz range. The slow access speed can
result in a longer access time than what can be generated by the internal wait-state machine of the
processor when the processor is fast and DCLK is slow. To generate longer CPU access cycles, a
wait signal (WAIT_N) is generated by the PM7800. The WAIT_N signal is generated by the wait
circuit which is clocked by CPUCLK.
The PM7800 needs to detect cycle-to-cycle transitions on the CPU bus. Detecting the cycle-tocycle change is complicated because the cycle-inactive indication (deassertion of the strobes)
between cycles can be short for write-to-write cycles, and short or non-existent for read-to-read
cycle transitions. To simplify the design and stay within synchronous design practices, cycle-tocycle transition-detection is achieved by the direct approach of sampling the control signal(s)
inactive, or by the indirect approach of sampling the control strobes a programmable number of
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PMC-Sierra, Inc.
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Digital Correction Signal Processor
PM7800 PALADIN-10
Data Sheet
ISSUE 4
Digital Correction Signal Processor
PM
PMC-2001646
:49
:26
clock cycles after the WAIT_N signal is deasserted - if the strobes are still active, then the start of
another cycle is assumed.
9S
ep
tem
be
r,
20
02
11
The operation of the wait circuit - clocked by CPUCLK - is as follows: sample control strobes
active, assert WAIT_N for Assert_Wait_Cycles (register 0x0_0010 bits 6:0) CPUCLK’s, negate
WAIT_N for Negate_Wait_Cycles (register 0x0_0010 bits 11:8) CPUCLK’s, then sample control
strobes again. Another cycle has started if the control strobes are still active. The TI processor’s
internal wait-state circuit continues to count while WAIT_N is asserted. This results in the waitstate circuitry re-aligning itself with the TI cycle at each transition since the TI cycle will end as
soon as it detects WAIT_N negated. Other processors’ internal wait-state circuits may halt while
WAIT_N is asserted: in this case, the Assert_Wait_Cycles and Negate_Wait_Cycles registers must
be programmed so that they match the length of the processor accesses.
hu
rsd
ay
,1
To further support the case where the de-assertion period of the strobe signal between back-to-back
writes is too short to be reliably detected by DCLK, the PM7800 must be programmed to
temporarily deassert its internal version of the write strobe: CPUMODE1, when tied to VDD,
selects this operation. The Fake_End_Length register (register 0x0_0010 bits 15:12) sets the
duration, in CPUCLK’s, for which the write strobe is deasserted.
uo
fo
liv
ett
io
nT
The C54xx interface has an access strobe (either I/O or memory), an area indication (either DS# or
PS# for data or program memory or IS# for I/O space select), a R/W# indication, a data bus and an
address bus. To support C54xx processors, STRB1_N and STRB2_N must be connected to the
access strobe and R/W# indicator respectively, and CPUMODE0 must be tied to VSS. Processors
with read and write strobes can be supported by tying CPUMODE0 to VDD, and connecting the
write strobe to STRB1_N and the read strobe to STRB2_N.
inv
ef
The CPUMODE2 pin is reserved and should be tied to VDD.
de
db
yV
The CPUMODE3 pin, when tied to VDD, selects a mode of operation that can be used to support
processors, e.g. ARM, that require the read strobe to be sampled on the falling edge of CPUCLK
and the write strobe to be sampled on the rising edge. The CPUMODE3 pin must be tied to VSS.
Do
wn
loa
The PM7800 can be configured to provide additional hold time from CPUCLK before negating
WAIT_N - this may be required to support processors, e.g. ARM, that require longer hold times on
WAIT_N. CPUMODE4, when tied to VDD, selects additional hold time. The CPUMODE4 pin
must be tied to VSS.
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PM7800 PALADIN-10
Data Sheet
Digital Correction Signal Processor
PM
ISSUE 4
PMC-2001646
Connect To
(TMS320C5410)
11
Signal
(PM7800)
:49
PM7800 Connections to C54xx Processor
Description
02
Table 5-1
:26
The following table describes how to connect the PM7800 to a C5410 processor.
MSTRB#
This signal is the active-low program memory access strobe.
STRB2_N
R/W#
This signal is the Read/Write# cycle type indication.
WAIT_N
READY
When the WAIT_N signal is asserted low, the TI chip extends the current cycle until the
WAIT_N signal negated to a high state.
IRQ_N
INT3#
INT3 is one of the four interrupt inputs.
ADR[17:00]
ADDR[18:16],
ADDR[14:00]
The TI bus is word addressed, as is the PM7815.
DAT[15:00]
DATA[15:00]
Data is connected straight across.
CPUCLK
CLKOUT
The master clock output for the TI processor.
Maximum CPU clock frequency 100 MHz.
r,
tem
be
ep
9S
,1
ay
This signal is the program space access strobe.
ett
PS#
Description
liv
CS0_N
Miscellaneous PM7800 Connections
HIGH
CPUMODE2
HIGH
CPUMODE3
LOW
CPUMODE4
inv
CPUMODE1
de
wn
LOW
Do
Description
The CPU signalling style is access strobe and read/write# indication.
yV
LOW
db
CPUMODE0
ef
Connect To
loa
Signal
(PM7815)
uo
fo
Table 5-3
CS2
nT
Connect To
io
Signal
(PM7815)
CS1_N
rsd
PM7800 Connections to Address Decoder
hu
Table 5-2
20
STRB1_N
The WAIT circuit forces the internal version of the CPU write strobe inactive for a programmable number of CPUCLK cycles.
Reserved.
All inputs sampled on rising edge of CPUCLK.
No additional delay on WAIT_N.
LOW
Connected to the two other chip select inputs.
HIGH
Connected to the two other chip select inputs.
5.1.1 Functional Timing
The following timing diagrams give functional timing for the CPU interface. Because this interface
is asynchronous to DCLK, AC timing parameters (tis, tih, toe, top, toz, tw) are shown here for clarity
but are defined in AC Timing section 9.
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PM7800 PALADIN-10
Data Sheet
Read Cycle (CPUMODE0 = 0)
20ns
DCLK
T0
40ns
T1
60ns
T2
80ns
T3
100ns
T4
T5
120ns
T6
:26
0ns
:49
Figure 5-2
Digital Correction Signal Processor
PM
ISSUE 4
PMC-2001646
t ih
11
t is
T7
STRB1_N
t is
20
02
STRB2_N
tem
be
CSx
t ih
r,
5TDCLK
t oz
toz
t ih
ep
t is
9S
ADR[17:0]
t oe
0ns
20ns
DCLK
T1
T2
60ns
T3
80ns
100ns
T4
T5
120ns
T6
ett
STRB1_N
t ih
liv
t is
uo
fo
STRB2_N
t is
t oz
t ih
5TDCLK
ef
CSx
inv
toz
t ih
yV
t is
t oe
t op
Do
wn
loa
de
db
ADR[17:0]
DAT1[15:0]
T7
io
T0
40ns
hu
Read Cycle (CPUMODE0 = 1)
nT
Figure 5-3
rsd
ay
,1
DAT1[15:0]
t op
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PM7800 PALADIN-10
Data Sheet
0ns
50ns
T0
T1
T2
100ns
T3
T4
T5
:26
Back-to-Back Read Cycles (CPUMODE0 = 0)
150ns
T6
T7
T8
200ns
T9 T10 T11 T12 T13 T14
:49
Figure 5-4
Digital Correction Signal Processor
PM
ISSUE 4
PMC-2001646
11
DCLK
02
tis
20
STRB1_N
STRB2_N
r,
3TDCLK
5TDCLK
CSx
5TDCLK
tis
ep
tis
ADR[17:0]
toz
tem
be
tis
adr2
9S
adr1
toe
top
DAT[15:0]
top
toz
data2
0ns
nT
Back-to-Back Read Cycles (CPUMODE0 = 1)
50ns
T1
T2
T3
T4
100ns
T5
uo
tis
inv
tis
ef
STRB2_N
T8
T9 T10 T11 T12 T13 T14
3TDCLK
5TDCLK
yV
CSx
db
de
toz
5TDCLK
tis
tis
adr1
toe
adr2
top
top
data1
Do
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
top
toz
data2
wn
loa
T7
fo
STRB1_N
DAT[15:0]
T6
200ns
liv
DCLK
ADR[17:0]
150ns
ett
T0
io
Figure 5-5
hu
rsd
ay
,1
data1
top
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PM7800 PALADIN-10
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0ns
20ns
DCLK
40ns
T0
T1
60ns
T2
80ns
T3
100ns
T4
T5
t ih
STRB1_N
t is
t ih
t ih
t is
t is
t ih
t is
t is
t ih
t is
20
t is
ep
tem
be
r,
STRB2_N
ADR[17:0]
t ih
9S
t is
T6
02
Note2
CSx
120ns
11
t is
t is
:26
Back-to-Back Write Cycles (CPUMODE0 = 0)
:49
Figure 5-6
Digital Correction Signal Processor
PM
ISSUE 4
PMC-2001646
0ns
20ns
DCLK
nT
Back-to-Back Write Cycles (CPUMODE0 = 1)
40ns
T1
ett
T0
io
Figure 5-7
hu
rsd
ay
,1
DAT[15:0]
T2
tis
inv
CSx
ef
STRB2_N
yV
tis
T4
T5
120ns
T6
tih
tis
tih
tis
tih
tis
tih
tis
tih
de
db
ADR[17:0]
T3
100ns
Note2
uo
STRB1_N
80ns
tis
fo
liv
tis
60ns
wn
Do
Note:
loa
DAT[15:0]
1. The system designer need not worry about violating tis and tih - all inputs are treated as
asynchronous signals. Setup and hold times are specified here to identify the clock edge
on which the signal is sampled.
2. If deassertion of the strobe cannot be detected by DCLK, CPUMODE1 must be tied to
VDD to program the PM7800 to temporarily deactivate the internal write strobe - See
Functional Description section 5. .
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WAIT_N Timing - Reads (CPUMODE0 = 0)
100ns
200ns 300ns
400ns
500ns
600ns
700ns 800ns
900ns
1
700ns 800ns
900ns
1
700ns
900ns
1
11
0ns
:49
Figure 5-8
:26
PM
PMC-2001646
02
CPUCLK
20
STRB1_N
r,
STRB2_N
Twait_n_delay
tem
be
Twait_n_asserted
Twait_n_negated
WAIT_N Timing - Reads (CPUMODE0 = 1)
0ns
100ns
200ns 300ns
400ns
500ns
600ns
nT
hu
CPUCLK
rsd
Figure 5-9
ay
,1
9S
ep
WAIT_N
STRB1_N
ett
io
STRB2_N
liv
Twait_n_asserted
Twait_n_negated
fo
Twait_n_delay
yV
inv
ef
uo
WAIT_N
Figure 5-10 WAIT_N Timing - Writes (CPUMODE0 = 0)
100ns
200ns
300ns
400ns
500ns
600ns
de
CPUCLK
db
0ns
loa
STRB1_N
Do
wn
STRB2_N
First rising edge of STRB1_N
Twait_n_delay
Twait_n_asserted
Twait_n_negated
WAIT_N
Tfake_end_length
internal_write_strobe
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PM
PMC-2001646
Figure 5-11 WAIT_N Timing - Writes (CPUMODE0 = 1)
100ns
200ns
300ns
400ns
500ns
600ns
700ns
900ns
11
CPUCLK
800ns
:49
0ns
02
STRB1_N
STRB2_N
20
First rising edge of STRB1_N
r,
Twait_n_delay
Twait_n_negated
tem
be
Twait_n_asserted
WAIT_N
ep
Tfake_end_length
,1
min
hu
Parameter
ay
Functional Timing for WAIT_N
rsd
Table 5-4
9S
internal_write_strobe
Description
2TCPUCLK
Twait_n_asserted
(Assert_Wait_Cycles[6:0] + 1)TCPUCLK
Twait_n_negated
(Negate_Wait_Cycles[3:0] + 1) TCPUCLK
WAIT_N negated width
Tfake_end_length
(Fake_End_Length[3:0] + 1) TCPUCLK
Internal fake_end length for back-to-back writes.
STRBx to WAIT_N delay
WAIT_N pulse width
fo
liv
ett
io
nT
Twait_n_delay
ef
uo
5.1.2 Programming the WAIT_N Register
Programming the WAIT_N Register
db
Table 5-5
yV
inv
The following are guidelines for programming the WAIT_N register:
de
Formula
loa
Assert_Wait_Cycles = round-up {6Tdclk /Tcpuclk -1}
wn
Negate_Wait_Cycles = round-up {3 + 32 / Tcpuclk}
Do
internal_c54_wait > Negate_Wait_Cycles
Comment
Must satisfy PM7800 read-access time of 6 dclk periods
Must be long enough to allow the C54 to end the current cycle, and to
flush the cycle_active out of the cpuclk synchronizers.
The C54 must be programmed such that it will not start another cycle
before WAIT_N can be reasserted.
where internal_c54_wait is the number of wait cycles programmed
in the C54xx processor.
Fake_End_Length = round-up{max{[(Tdclk + 2ns) / Tcpuclk - 1] :
[1.5 + 32 / Tcpuclk]}}
Must be long enough for the PM7800 to sample its internal
fake_wait_inactive with dclk.
Must also be long enough that fake_wait_inactive is held until past
the rising edge of STRB1_N (shown in Figure 5-10 on page 22 and
Figure 5-11 on page 23).
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Baseband
Modem
11
:49
:26
5.2 Data Interfaces
dclk
refclk
vobs_i[15:0]
rsd
ay
vd_fmt
RF Downconverter
9S
obs
Main
Amp
,1
V
RF Upconverter
ep
reset_n
mute_n
20
vobs_q[15:0]
D
r,
vd_i[15:0]
vd_q[15:0]
V
ref
tem
be
V
DAC
DAC
vref_i[15:0]
vref_q[15:0]
ADC
ADC
02
PM7800 DCSP
nT
hu
Figure 5-12 Data Interfaces
ett
io
5.2.1 VREF Interface and FIFO
ef
uo
fo
liv
The VREF interface is used to input the reference signal in either offset-binary or two’scomplement notation. In the case of offset-binary format, the VREF_Data_Format bit in the Mode
register must be set to zero to instruct the PM7800 to convert the data to two’s-complement format
which is used throughout the chip. There are three modes of operation for the VREF interface:
de
db
yV
inv
1. VREF is clocked in by REFCLK and upsampled to the rate of the PM7800 clock,
DCLK, where fDCLK = N * fREFCLK. In this case, a FIFO is used to handle the skew
between REFCLK and DCLK, and to provide a steady supply of data to the interpolator.
Set the Bypass_FIFO and Interpolator_Bypass bits to zero (default) in this case.
Do
wn
loa
2. VREF is clocked in by REFCLK which is at the same rate as the PM7800 clock, DCLK,
that is, fDCLK = fREFCLK. In this case, a FIFO is used to handle the skew between
REFCLK and DCLK. The interpolator can be bypassed to reduce latency. Set the
Bypass_FIFO bit to zero (default) and the Interpolator_Bypass bit to one in this case.
3. VREF is at the same rate as and synchronous to DCLK. In this case, the FIFO and
interpolator can be bypassed to reduce system latency by setting the Bypass_FIFO and
Interpolator_Bypass bits to one in the Mode register. The REFCLK input is ignored and
should be connected to VSS.
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5.2.2 VOBS Interface
20
02
11
:49
The VOBS interface is used to input the observed signal from the ADC in either offset-binary or
two’s-complement notation. In the case of offset-binary format, the VOBS_Data_Format bit in the
Mode register must be set to zero to instruct the PM7800 to convert the data to two’s-complement
format.
tem
be
r,
5.2.3 VD Interface
9S
ep
The VD interface is used to output the predistorted signal to the DAC in either offset-binary or
two’s-complement notation. The VD_FMT pin selects offset-binary format when low, and two’scomplement format when high.
,1
5.2.4 Dual-Clock System
liv
ett
io
nT
hu
rsd
ay
Use the dual-clock system when VREF is synchronous to REFCLK (usually when VREF is
upsampled internally to the DCLK rate). TREFCLK must be an exact integer multiple of TDCLK, i.e.
TREFCLK = nTDCLK, where n = 1,2,...,10. REFCLK must be created from DCLK. In this case, a
FIFO and interpolator are used to upsample VREF to the DCLK rate. REFCLK must be created
from DCLK such that there is no varying phase shift that may cause under-run or over-run, i.e.
skew may exist between DCLK and REFCLK, but this skew must not vary over time by more than
one DCLK period.
fo
Figure 5-13 Dual-Clock System timing
20ns
60ns
80ns
100ns
120n
ef
DCLK
inv
VOBS
yV
VD
loa
de
db
REFCLK
VREF
40ns
uo
0ns
wn
5.2.5 Single-Clock System
Do
Use the single-clock system when all signals are synchronous to DCLK and the data-rate of VREF
is the same as the output data-rate of VD. In this case, connect the REFCLK pin to VSS, and bypass
the FIFO and interpolator to reduce latency through the chip.
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10ns
20ns
30ns
40ns
50ns
60ns
70ns
80ns
9
:49
0ns
:26
Figure 5-14 Single-Clock System timing
DCLK
11
VREF
02
VOBS
tem
be
r,
20
VD
,1
9S
ep
5.3 Serial Interface
rsd
ay
PM7800 DCSP
hop_n
sd
sclk
scs_n
liv
ett
io
nT
hu
gpio[23:0]
gpio[47:24]
inv
ef
uo
fo
Figure 5-15 Serial (SPI), Hop, and GPIO Interfaces
de
db
yV
The serial interface is used to input the next_power, next_carrier values, hop_stream command,
and general-purpose serial_word register. Also included in this interface is the HOP_N pin which
can be used to delay the effect of the hop_stream to a more precise time.
Do
wn
loa
The PM7800 supports the SPI specification included in the M68HC11 Reference Manual (section
8). Only the modes where CPHA = 1 is supported. CPOL may be 0 or 1, and the spi_clock_polarity
bit of the serial_mode register (0x0_0013 bit 2) is used to select the active clock edge. The PM7800
does not have a data output pin (MISO). The PM7800’s SCS_N pin is equivalent to the /SS pin,
and it can be tied to ground to reduce system pin requirements.
A transfer can be reset by deactivating SCS_N. If SCS_N is tied low (always active) then another
method must be used to reset the state machine. One way is to disable the serial interface by writing
a zero to the serial_interface_enable bit in the Serial_Mode register. Another way is to set
reg_serial_address[4:0] = 00000b (this is the default setting) and stream twenty-four 1’s into the
serial port: at some stage during the stream of 1’s, the idle state will be reached and the interface
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:26
will be held waiting for the first 0 of the address. Note that if the transfer is aborted after some data
has been sent, that data will already be shifted into the respective data register.
20
02
11
Relative timing of the SPI input signals is shown in Figure 5-16. Note that SCLK, SD, SCS_N can
be asynchronous to DCLK: Figure 5-16 shows timing for the inputs relative to the DCLK edges on
which they are detected. Notes:
tem
be
r,
• SCLK, SD, SCS_N are debounced using DCLK, therefore they must be present for two
consecutive DCLK edges to be properly detected. It is recommended that the minimum
pulse-width be 3 TDCLK, i.e. TSCLK >= 6TDCLK.
ay
,1
9S
ep
• SD and SCS_N are sampled by DCLK on the active edge of SCLK. Therefore, because
of the asynchronous relationship, it is recommended that SD and SCS_N be valid for one
DCLK either side of the active SCLK edge.
hu
rsd
Figure 5-16 Relative Timing of SPI Inputs
nT
Active edge of SCLK
>=3TD
ett
io
DCLK
fo
liv
SCLK
>=TD
>=3TD
db
yV
inv
ef
uo
SD, SCS_N
>=TD
loa
de
5.3.1 Serial Operation
Do
wn
All signal pins in the serial interface are synchronized to dclk and debounced to reject glitches
shorter than a dclk period - see AC Timing. There are four serial streams recognized by this
interface:
1. carrier_stream consists of three bytes as follows:
•
•
•
•
five address bits corresponding to reg_serial_address[4:0]
two bits = 00b, that indicate a carrier_stream
a r/w bit that must be zero
seven don’t-care bits
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• nine bits of the next_carrier value - in the order of msb to lsb
50ns
100ns
150ns
200ns
x
x x
x x x c8 c7 c6 c5 c4 c3 c2 c1 c0
20
a7 a6 a5 a4 a3 0 0 0 x
02
SCLK
SD
250
11
0ns
:49
Figure 5-17 SPI carrier_stream (spi_clock_polarity = 0, falling edge of SCLK is active)
tem
be
r,
SCS_N
Figure 5-18 SPI carrier_stream (spi_clock_polarity = 1, rising edge of SCLK is active)
0ns
50ns
100ns
150ns
a7 a6 a5 a4 a3 0 0 0 x
x
x x x c8 c7 c6 c5 c4 c3 c2 c1 c0
x x
rsd
ay
,1
SCS_N
9S
SD
250
ep
SCLK
200ns
liv
ett
io
five address bits corresponding to reg_serial_address[4:0]
two bits = 01b, that indicate a power_stream
a r/w bit that must be zero
eight bits of the next_power value - in the order of msb to lsb
fo
•
•
•
•
nT
hu
2. power_stream consists of two bytes as follows:
uo
Figure 5-19 SPI power_stream (spi_clock_polarity = 0, falling edge of SCLK is active)
20ns
40ns
60ns
80ns
100ns
120ns
140ns
160ns
1
ef
0ns
inv
SCLK
SD
0
1
0
p7 p6 p5 p4 p3 p2 p1 p0
yV
a7 a6 a5 a4 a3
de
db
SCS_N
0ns
20ns
40ns
60ns
80ns
100ns
120ns
140ns
160ns
wn
loa
Figure 5-20 SPI power_stream (spi_clock_polarity = 1, rising edge of SCLK is active)
Do
SCLK
SD
a7 a6 a5 a4 a3
0
1
0
p7 p6 p5 p4 p3 p2 p1 p0
SCS_N
3. word_stream consists of three bytes as follows:
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five address bits corresponding to reg_serial_address[4:0]
two bits = 10b, that indicate a word_stream
a r/w bit that must be zero
sixteen bits of the serial_word value - in the order of msb to lsb
11
•
•
•
•
Digital Correction Signal Processor
PM
ISSUE 4
PMC-2001646
50ns
100ns
150ns
200ns
250n
20
0ns
02
Figure 5-21 SPI word_stream (spi_clock_polarity = 0, falling edge of SCLK is active)
a7 a6 a5 a4 a3
1
0
0 w15w14w13w12w11w10 w9 w8 w7 w6 w5 w4 w3 w2 w1 w0
tem
be
SD
r,
SCLK
SCS_N
50ns
100ns
9S
0ns
ep
Figure 5-22 SPI word_stream (spi_clock_polarity = 1, rising edge of SCLK is active)
a7 a6 a5 a4 a3
1
0
250n
0 w15w14w13w12w11w10 w9 w8 w7 w6 w5 w4 w3 w2 w1 w0
ay
SD
200ns
,1
SCLK
150ns
nT
hu
rsd
SCS_N
ett
io
4. hop_stream consists of one byte as follows:
uo
fo
liv
• five address bits corresponding to reg_serial_address[4:0]
• two bits = 11b, that indicate a hop_stream
• a r/w bit that must be zero
ef
Figure 5-23 SPI hop_stream (spi_clock_polarity = 0, falling edge of SCLK is active)
yV
SCLK
SD
40ns
60ns
80ns
a6
a5
a4
a3
1
1
0
db
a7
de
SCS_N
20ns
inv
0ns
loa
HOP_N
Do
wn
carrier/power
Figure 5-23 shows how HOP_N can be used to delay the new carrier/power values.
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10ns
20ns
30ns
40ns
50ns
60ns
70ns
80ns
90ns
1
:49
0ns
:26
Figure 5-24 SPI hop_stream (spi_clock_polarity = 1, rising edge of SCLK is active)
SD
a7
a6
a5
a4
a3
1
1
0
02
SCS_N
11
SCLK
20
HOP_N
tem
be
r,
carrier/power
,1
9S
ep
Figure 5-24 shows a case where HOP_N is tied active so that the new carrier/power values take
effect immediately after the Hop_Stream.
rsd
ay
5.4 Hop Generation
ett
io
nT
hu
The hop_state_machine generates the Hop pulse that propagates throughout the chip and activates
the new carrier and power values. The Hop pulse is generated upon a write to the Hop bit in the
Control register, or on the later of HOP_N and a Hop_Stream. There are three methods of
operation:
uo
fo
liv
1. The Hop bit in the Control register controls the activation point.
The CPU writes to the next_carrier and/or next_power registers, then writes 1 to the
Hop bit in the Control register.
db
yV
inv
ef
2. HOP_N controls the activation point.
Carrier_Stream and Power_Stream are immediately followed by a Hop_Stream. Then
HOP_N is applied so that the new values are activated at the correct time. This is a
likely scenario for Multi_Band_Mode (e.g. single-carrier EDGE systems). This is
illustrated in Figure 5-23.
Do
wn
loa
de
3. Hop_Stream controls the activation point.
HOP_N is held active by connecting it to VSS, thereby reducing system pin
requirements. The Hop_Stream is used to activated new values at the correct time. This
is illustrated in Figure 5-24. Note that the final bit of the Hop_Stream can be delayed to
the desired time.
5.4.1 Power and Carrier Values and Hop
There are two parameters that are used throughout the device and must be explained here:
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11
:49
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• Power - Power selection by base station. This is an 8-bit integer value and its
interpretation is configured by the Power_Attenuation_Table, the
Power_Correction_Gain_Table, and the Carrier_Power_Map.
• Carrier - Carrier (or frequency band) selection by base station. This is a 9-bit integer
value and its interpretation is configured by the Carrier_Correction_Gain_Table and the
Carrier_Power_Map.
tem
be
r,
20
The Power and Carrier values can be input through the serial interface, or directly programmed by
the CPU. In either case, the values entered are Next_Power and Next_Carrier, and they become
active Power and Carrier values after the next Hop occurs (see Section 5.4, Hop Generation, on
page 30).
rsd
ay
,1
9S
ep
The new Power value propagates to the Power_Attenuation_Table after a delay controlled by the
Power_Attenuator_Delay register. The new Power and Carrier values propagate to all other areas
of the device after a delay controlled by the Power_Correction_Delay register. These two
programmable delays are designed to allow some control over the effects of power changes
throughout the system.
nT
hu
5.4.2 Bug that affects Power_Attenuator_Delay and Power_Correction_Delay
ett
io
The Power_Attenuator_Delay and Power_Correction_Delay circuits were intended to operate so
that:
uo
fo
liv
1. if Power_Attenuator_Delay > Power_Correction_Delay, the Power_Attenuator output
on GPIO[15:0] and the pulse output on GPIO17 are delayed with respect to the
power_correction_gain value applied inside the chip.
yV
inv
ef
2. if Power_Attenuator_Delay < Power_Correction_Delay, the Power_Attenuator output
on GPIO[15:0] and the pulse output on GPIO17 are earlier than the
power_correction_gain value applied inside the chip.
db
The bug has two ramifications:
wn
loa
de
• The relationship between these two delays must be such that Power_Attenuator_Delay
>= Power_Correction_Delay + 1, i.e. (2) above is not possible. We recommend that
Power_Correction_Delay is programmed to its default state of zero.
Do
• The Power_Attenuator output on GPIO[15:0] is not delayed but the pulse on GPIO17 is.
Therefore, the external attenuator device must use the pulse to latch the new
Power_Attenuator value.
See Section 5.5.2, Power Attenuator Outputs, on page 33.
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5.5 GPIO Pins
11
:49
These pins are general-purpose input-outputs. They are controlled and monitored through the
PM7800 register set. Some of the pins have secondary functions.
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
tem
be
r,
20
02
• GPIO[15:0] can be configured to output the value from the Power_Attenuator_Table.
• GPIO16 can be configured to output an active-low pulse of 32TDCLK duration when the
Watchdog Timer expires.
• GPIO17 can be configured to output a 5TDCLK pulse when a Hop occurs. The pulse is
positioned so that its leading edge is concurrent with changes in the value of the
Power_Attenuator_Table output at GPIO[15:0] - see Functional Timing. The polarity of
the pulse is selected by the Atten_Pulse_Polarity bit in the Mode register.
• GPIO[18] can be configured to output a low pulse when a subset of alarms have been
detected in the ACPCE Firmware. This pulse can be used to trigger a Status Request
across the Base Station Interface.
• GPIO[23:19] have no secondary function.
• GPIO[27:24] can be configured as falling-edge triggered interrupt sources. The interrupts
are enabled using the GPIO_Interrupt_Enable bits in the Interrupt_Enable2 register. The
interrupts are monitored and cleared in the Interrupt_Status_Clear register.
• GPIO[31:28] can be configured as rising-edge triggered interrupt sources. The interrupts
are enabled using the GPIO_Interrupt_Enable bits in the Interrupt_Enable2 register. The
interrupts are monitored and cleared in the Interrupt_Status_Clear register.
• GPIO[47:32] have no secondary function.
uo
5.5.1 Status Output Pulse
db
yV
inv
ef
The ACPCE firmware will output a pulse whenever an alarm occurs which is not masked. The
mask can be configured by the Base Station Controller. The output pulse occurs on GPIO18 and is
an active low pulse. The duration of the pulse depends on the operating speed of the DSP: at 25
MHz it is about 12 microseconds, at 100 MHz it is about 3 microseconds.
de
The boot kernel outputs a pulse on GPIO18 as well under the following circumstances:
Do
wn
loa
• Hard Reset/Power-on - indicates that the boot kernel is ready to send out the boot_status
response. After this response is read out the boot kernel commands for loading firmware
can be sent.
GPIO18 is not pulsed for Watchdog/Assert resets as these resets autostart the previous version of
firmware that was running. For Watchdog/assert the a pulse is sent as part of the ACPCE firmware
startup.
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:26
5.5.2 Power Attenuator Outputs
11
DCLK
02
power_correction_gain
r,
20
TD
tem
be
GPIO[15:0]
5TD
9S
ep
GPIO17
ay
,1
power_attenuator_delay*TD
hu
rsd
Figure 5-25 Power Attenuator Outputs - shown with active-low pulse on GPIO17
nT
5.5.3 Watchdog Timer Output
0ns
50ns
150ns
200ns
250ns
ett
io
100ns
32TDCLK
fo
liv
DCLK
ef
uo
GPIO16
Do
wn
loa
de
db
yV
inv
Figure 5-26 Watchdog Timer Output
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300ns
3
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:26
5.6 JTAG Test Access Port
tck
trstb
tms
tdi
tdo
scansel
scanen
oe_n
tem
be
r,
JTAG
20
02
PM7800 DCSP
ep
Scan Test
ay
,1
9S
Figure 5-27 JTAG and Scan Test Interfaces
nT
hu
rsd
The JTAG Test Access Port block provides JTAG support for boundary scan. The standard JTAG
EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST instructions are supported. The PM7800
identification code is 178000CD hexadecimal.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
The JTAG port is described in detail in Test Features section 6.
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Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
tem
be
r,
20
02
11
:49
:26
PM
PMC-2001646
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PM
PMC-2001646
:26
6 Test Features
11
:49
The PM7800 has four test modes: Full Scan, RAMBIST, OE_N Pin, and JTAG Boundary Scan.
02
6.1 Full Scan
Full-Scan Interface
Full-Scan Signal
tem
be
Table 6-1
r,
20
The core logic is tested using full scan. The following table describes the full-scan interface.
Pin
Description
SCANSEL
Selects full-scan mode: selects RESET_N to directly control all flop
sets and resets; disables RAM BIST; configures the SCANIN and
SCANOUT IO pads.
SCANEN
SCANEN
Enables the scan chain.
SCANIN[55:32]
GPIO[47:24]
SCANIN bus.
SCANIN[31:16]
VD_Q[15:0]
SCANIN bus.
SCANIN[15:0]
VD_I[15:0]
SCANIN bus.
SCANOUT[55:32]
GPIO[23:0]
SCANOUT bus.
SCANOUT[31:16]
VREF_Q[15:0]
SCANOUT bus.
SCANOUT[15:0]
VREF_I[15:0]
ett
io
nT
hu
rsd
ay
,1
9S
ep
SCANSEL
fo
liv
SCANOUT bus.
uo
6.2 RAMBIST
yV
inv
ef
These registers are for RAMBIST. They must remain in their default states during regular
operation.
BIST_Mode
db
0x0_00F0
loa
Type
Size
Bits
Description
Reset
RW
8
7:0
BIST test pattern bus which is replicated over
the RAM data bus. This bus is the seed used by
the BIST to generate patterns during the bist
test. It is also used in exercising the backdoor
feature by providing a method to shift in/out
data.
0
RW
1
8
This bit activates BIST testing.
0
Do
wn
BISTTEST[7:0]
de
Name
BISTEN
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BIST_Mode
Size
Bits
Description
BISTSIDE
RW
1
9
BISTSIDE is used to select between port A and
port B when performing a BIST test. Since
Predistorter1 contains dual-port RAM, two BIST
tests must be run, first with this bit = 0, and then
with this bit = 1.
0: port A
1: port B
BISTMODE[2:0]
RW
3
12:10
BISTMODE configures the BIST in several different modes:
000: bistmode_hold
001: bistmode_shift
010: bistmode_bist
011: bistmode_run
100: bistmode_reset
101 ~ 111: Reserved.
11
:49
Type
Reset
0
0
BIST_Result1
Size
Bits
BISTEND
RO
1
0
BISTRESULT
RO
1
0
1
The BISTRESULT bit indicates whether all
RAMs have passed or failed the BIST test. If
BISTRESULT transitions from high to low, a
RAM has experienced a compare failure (i.e. at
least one of the bisterror bits have been
asserted). Once a compare failure is detected,
BISTRESULT transitions to a low state, and
stays in that state for the remainder of the test.
0
15:2
BISTERROR bus to indicate compare failure on
a RAM word. Each bit corresponds to one of the
RAMs in the device. The BISTERROR bit associated with each RAM toggles high each time a
compare failure is detected.
0
ett
liv
fo
uo
ef
inv
yV
RO
14
Reset
The BISTEND bit indicates the BIST test
sequence has completed. When the BIST test
is complete, bistend transitions from low to
high.
0x0_00F4
BIST_Result2
Do
wn
loa
de
db
BISTERROR[13:0]
Description
nT
Type
io
Name
hu
0x0_00F2
rsd
ay
,1
9S
ep
tem
be
r,
20
02
Name
:26
0x0_00F0
Digital Correction Signal Processor
PM
ISSUE 4
PMC-2001646
Type
Size
Bits
Description
Reset
RO
7
6:0
BISTERROR bus to indicate compare failure on
a RAM word. Each bit corresponds to one of the
RAMs in the device. The BISTERROR bit associated with each RAM toggles high each time a
compare failure is detected.
0
Name
BISTERROR[20:14]
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6.3 OE_N Pin
02
11
:49
The OE_N pin, when high, deactivates all pins except TDO. TDO is a tri-state output driven during
boundary-scan testing only (see below); applying an active-low pulse to TRSTB ensures that TDO
is inactive.
20
6.4 JTAG Boundary Scan, IEEE 1149.1
9S
ep
tem
be
r,
The PM7800 supports the IEEE Boundary Scan Specification as described in the IEEE 1149.1
standards. The PM7800 JTAG Test Access Port (TAP) allows access to the TAP controller and the
four TAP registers: instruction, bypass, device identification and boundary scan. Using the TAP,
device input logic levels can be read, device outputs can be forced, the device can be identified and
the device scan path can be bypassed.
nT
hu
rsd
ay
,1
The Test Access Port (TAP) consists of the five standard pins, TRSTB, TCK, TMS, TDI and TDO
used to control the TAP controller and the boundary scan registers. The TRSTB input is the activelow reset signal used to reset the TAP controller. TCK is the test clock used to sample data on input,
TDI and to output data on output, TDO. The TMS input is used to direct the TAP controller through
its states.
fo
liv
ett
io
The boundary-can architecture is shown below.
Boundary Scan
Register
Device Identification
Register
ef
uo
TDI
yV
inv
Bypass
Register
Mux
DFF
TDO
Do
Control
TMS
wn
loa
de
db
Instruction
Register
and
Decode
Test
Access
Port
Controller
Select
Tri-state Enable
TRSTB
TCK
Figure 6-1
Boundary-Scan Architecture
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02
11
:49
:26
The boundary scan architecture consists of a TAP controller, an instruction register with instruction
decode, a bypass register, a device identification register and a boundary scan register. The TAP
controller interprets the TMS input and generates control signals to load the instruction and data
registers. The instruction register with instruction decode block is used to select the test to be
executed and/or the register to be accessed. The bypass register offers a single-bit delay from
primary input, TDI to primary output, TDO. The device identification register contains the device
identification code.
9S
ep
tem
be
r,
The boundary scan register allows testing of board inter-connectivity. The boundary scan register
consists of a shift register place in series with device inputs and outputs. Using the boundary scan
register, all digital inputs can be sampled and shifted out on primary output, TDO. In addition,
patterns can be shifted in on primary input, TDI and forced onto all digital outputs.
,1
6.4.1 TAP Controller
nT
hu
rsd
ay
The TAP controller is a synchronous finite state machine clocked by the rising edge of primary
input, TCK. All state transitions are controlled using primary input, TMS. The finite state machine
is described below.
TR STB=0
io
T e s t- L o g ic - R e s e t
1
ett
0
1
liv
R u n - T e s t- Id le
1
S e le c t- I R - S c a n
0
0
1
1
C a p tu re -IR
C a p tu r e - D R
uo
fo
0
1
S e le c t- D R - S c a n
0
ef
0
S h if t - IR
inv
S h if t- D R
1
1
0
1
yV
E x it1 - IR
E x it 1 - D R
0
db
0
P a u s e - IR
de
P a u s e -D R
0
1
loa
0
E x it2 - IR
1
1
wn
0
1
0
E x it 2 - D R
U p d a te -D R
Do
0
1
1
U p d a te -IR
1
0
0
A ll tr a n s itio n s d e p e n d e n t o n in p u t T M S
Figure 6-2
TAP Controller Finite State Machine
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:49
Test-Logic-Reset
tem
be
r,
20
02
The test logic reset state is used to disable the TAP logic when the device is in normal mode
operation. The state is entered asynchronously by asserting input, TRSTB. The state is entered
synchronously regardless of the current TAP controller state by forcing input, TMS high for 5 TCK
clock cycles. While in this state, the instruction register is set to the IDCODE instruction.
Run-Test-Idle
9S
ep
The run test/idle state is used to execute tests.
,1
Capture-DR
nT
hu
rsd
ay
The capture data register state is used to load parallel data into the test data registers selected by
the current instruction. If the selected register does not allow parallel loads or no loading is required
by the current instruction, the test register maintains its value. Loading occurs on the rising edge
of TCK.
ett
io
Shift-DR
fo
liv
The shift data register state is used to shift the selected test data registers by one stage. Shifting is
from MSB to LSB and occurs on the rising edge of TCK.
ef
uo
Update-DR
de
db
yV
inv
The update data register state is used to load a test register's parallel output latch. In general, the
output latches are used to control the device. For example, for the EXTEST instruction, the
boundary scan test register's parallel output latches are used to control the device's outputs. The
parallel output latches are updated on the falling edge of TCK.
loa
Capture-IR
Shift-IR
Do
wn
The capture instruction register state is used to load the instruction register with a fixed instruction.
The load occurs on the rising edge of TCK.
The shift instruction register state is used to shift both the instruction register and the selected test
data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK.
Update-IR
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:26
The update instruction register state is used to load a new instruction into the instruction register.
The new instruction must be scanned in using the Shift-IR state. The load occurs on the falling edge
of TCK.
20
02
The Pause-DR and Pause-IR states are provided to allow shifting through the test data and/or
instruction registers to be momentarily paused.
tem
be
r,
6.4.2 Registers
6.4.2.1 Instruction Register
,1
Selected Register
Boundary Scan
IDCODE
Identification
SAMPLE
Boundary Scan
BYPASS
Bypass
BYPASS
Bypass
STCTEST
Boundary Scan
101
BYPASS
Bypass
110
BYPASS
Bypass
111
nT
hu
rsd
EXTEST
liv
Instruction Codes, IR[2:0]
fo
Instructions
9S
Instruction Register
ay
Table 6-2
ep
Length = 3 bits
000
001
010
io
011
inv
ef
uo
ett
100
yV
6.4.2.2 Identification register
db
Length = 32 bits
Identification Register
Length
32 bits
wn
loa
de
Table 6-3
1h
Do
Version number
Part Number
7800h
Manufacturer's identification code
0CDh
Device identification
178000CDh
6.4.2.3 Boundary Scan Register
Name
Register Bit
-------------------------------- -----------OEB_GPIO7
333
Cell Type
--------OUT_CELL
Device ID
--------L
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ef
:26
:49
11
02
20
r,
tem
be
ep
9S
,1
ay
rsd
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
H
H
L
H
-
io
nT
hu
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
IN_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
ett
liv
fo
uo
332
331
330
329
328
327
326
325
324
323
322
321
320
319
318
317
316
315
314
313
312
311
310
309
308
307
306
305
304
303
302
301
300
299
298
297
296
295
294
293
292
291
290
289
288
287
286
285
284
283
282
281
280
279
278
277
276
275
274
273
272
271
270
269
268
267
266
265
264
263
262
261
260
259
258
257
256
inv
yV
db
de
loa
wn
Do
GPIO7
OEB_GPIO6
GPIO6
OEB_GPIO4
GPIO4
OEB_GPIO5
GPIO5
OEB_GPIO2
GPIO2
OEB_GPIO1
GPIO1
OEB_GPIO3
GPIO3
OEB_GPIO0
GPIO0
OEB_VD_I13
VD_I13
OEB_VD_I10
VD_I10
OEB_VD_I14
VD_I14
OEB_VD_I11
VD_I11
OEB_VD_I15
VD_I15
OEB_VD_I12
VD_I12
OEB_VD_I7
VD_I7
OEB_VD_I8
VD_I8
OEB_VD_I4
VD_I4
OEB_VD_I9
VD_I9
OEB_VD_I5
VD_I5
OEB_VD_I6
VD_I6
OEB_VD_I0
VD_I0
OEB_VD_I1
VD_I1
OEB_VD_I2
VD_I2
OEB_VD_I3
VD_I3
DCLK
OEB_VD_Q15
VD_Q15
OEB_VD_Q14
VD_Q14
OEB_VD_Q13
VD_Q13
OEB_VD_Q12
VD_Q12
OEB_VD_Q11
VD_Q11
OEB_VD_Q10
VD_Q10
OEB_VD_Q9
VD_Q9
OEB_VD_Q8
VD_Q8
OEB_VD_Q7
VD_Q7
OEB_VD_Q5
VD_Q5
OEB_VD_Q4
VD_Q4
OEB_VD_Q6
VD_Q6
OEB_VD_Q3
VD_Q3
OEB_VD_Q1
VD_Q1
OEB_VD_Q0
Digital Correction Signal Processor
PM
ISSUE 4
PMC-2001646
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ef
:26
:49
11
02
20
r,
tem
be
ep
9S
,1
ay
rsd
-
io
nT
hu
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
IN_CELL
IN_CELL
IN_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
OUT_CELL
OUT_CELL
OUT_CELL
OUT_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
ett
liv
fo
uo
255
254
253
252
251
250
249
248
247
246
245
244
243
242
241
240
239
238
237
236
235
234
233
232
231
230
229
228
227
226
225
224
223
222
221
220
219
218
217
216
215
214
213
212
211
210
209
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
inv
yV
db
de
loa
wn
Do
VD_Q0
OEB_VD_Q2
VD_Q2
OEB_GPIO47
GPIO47
OEB_GPIO46
GPIO46
OEB_GPIO45
GPIO45
MUTE_N
CPUMODE4
CPUMODE3
OEB_GPIO44
GPIO44
OEB_GPIO42
GPIO42
OEB_GPIO43
GPIO43
ADR1
ADR0
ADR2
ADR4
ADR8
ADR3
ADR7
ADR11
ADR6
ADR10
ADR5
ADR9
ADR14
ADR13
ADR17
ADR12
ADR16
ADR15
CS2
CS1_N
CS0_N
CPUCLK
STRB1_N
STRB2_N
OEB_WAIT_N
WAIT_N
OEB_IRQ_N
IRQ_N
OEB_DAT0
DAT0
OEB_DAT1
DAT1
OEB_DAT2
DAT2
OEB_DAT3
DAT3
OEB_DAT4
DAT4
OEB_DAT5
DAT5
OEB_DAT6
DAT6
OEB_DAT7
DAT7
OEB_DAT8
DAT8
OEB_DAT9
DAT9
OEB_DAT11
DAT11
OEB_DAT12
DAT12
OEB_DAT10
DAT10
OEB_DAT13
DAT13
OEB_DAT15
DAT15
OEB_DAT14
Digital Correction Signal Processor
PM
ISSUE 4
PMC-2001646
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Data Sheet
ef
:26
:49
11
02
20
r,
tem
be
ep
9S
,1
ay
rsd
-
io
nT
hu
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
IN_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
IN_CELL
IN_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
IN_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
IN_CELL
OUT_CELL
IO_CELL
IN_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
IN_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
ett
liv
fo
uo
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
inv
yV
db
de
loa
wn
Do
DAT14
OEB_GPIO41
GPIO41
OEB_GPIO38
GPIO38
OEB_GPIO37
GPIO37
OEB_GPIO39
GPIO39
VSS
OEB_GPIO36
GPIO36
OEB_GPIO40
GPIO40
CPUMODE1
CPUMODE0
OEB_SD
SD
OEB_GPIO35
GPIO35
OEB_GPIO33
GPIO33
OEB_GPIO30
GPIO30
OEB_GPIO34
GPIO34
OEB_GPIO31
GPIO31
HOP_N
OEB_GPIO32
GPIO32
OEB_GPIO29
GPIO29
SCS_N
OEB_VREF_Q1
VREF_Q1
SCLK
OEB_VREF_Q2
VREF_Q2
OEB_VREF_Q0
VREF_Q0
OEB_VREF_Q3
VREF_Q3
OEB_VREF_Q4
VREF_Q4
OEB_VREF_Q6
VREF_Q6
OEB_VREF_Q5
VREF_Q5
OEB_VREF_Q7
VREF_Q7
OEB_VREF_Q8
VREF_Q8
OEB_VREF_Q9
VREF_Q9
OEB_VREF_Q10
VREF_Q10
OEB_VREF_Q11
VREF_Q11
OEB_VREF_Q12
VREF_Q12
OEB_VREF_Q13
VREF_Q13
OEB_VREF_Q15
VREF_Q15
OEB_VREF_Q14
VREF_Q14
REFCLK
OEB_VREF_I2
VREF_I2
OEB_VREF_I1
VREF_I1
OEB_VREF_I0
VREF_I0
OEB_VREF_I5
VREF_I5
OEB_VREF_I4
Digital Correction Signal Processor
PM
ISSUE 4
PMC-2001646
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PMC-Sierra, Inc.
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Digital Correction Signal Processor
PM7800 PALADIN-10
Data Sheet
ef
:26
:49
11
02
20
r,
tem
be
ep
9S
,1
ay
rsd
-
io
nT
hu
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
IN_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
ett
liv
fo
uo
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
inv
yV
db
de
loa
wn
Do
VREF_I4
OEB_VREF_I8
VREF_I8
OEB_VREF_I3
VREF_I3
OEB_VREF_I7
VREF_I7
OEB_VREF_I6
VREF_I6
OEB_VREF_I11
VREF_I11
OEB_VREF_I10
VREF_I10
OEB_VREF_I15
VREF_I15
OEB_VREF_I14
VREF_I14
OEB_VREF_I9
VREF_I9
OEB_VREF_I13
VREF_I13
OEB_GPIO28
GPIO28
OEB_VREF_I12
VREF_I12
RESET_N
OEB_GPIO27
GPIO27
OEB_GPIO25
GPIO25
OEB_GPIO26
GPIO26
OEB_GPIO23
GPIO23
OEB_GPIO22
GPIO22
OEB_GPIO24
GPIO24
OEB_GPIO21
GPIO21
OEB_GPIO19
GPIO19
OEB_GPIO18
GPIO18
OEB_GPIO20
GPIO20
OEB_GPIO17
GPIO17
OEB_GPIO16
GPIO16
OEB_GPIO15
GPIO15
VOBS_Q15
VOBS_Q13
VOBS_Q9
VOBS_Q14
VOBS_Q10
VOBS_Q6
VOBS_Q11
VOBS_Q7
VOBS_Q12
VOBS_Q8
VOBS_Q3
VOBS_Q4
VOBS_Q5
VOBS_Q0
VOBS_Q1
VOBS_Q2
VOBS_I12
VOBS_I13
VOBS_I14
VOBS_I15
VOBS_I11
VOBS_I10
VOBS_I9
VOBS_I8
VOBS_I7
Digital Correction Signal Processor
PM
ISSUE 4
PMC-2001646
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PMC-Sierra, Inc.
Released
Digital Correction Signal Processor
PM7800 PALADIN-10
Data Sheet
tem
be
r,
20
02
11
:49
:26
-
ep
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
IN_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
OUT_CELL
IO_CELL
IN_CELL
9S
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
,1
VOBS_I6
VOBS_I5
VOBS_I4
VOBS_I3
VOBS_I2
VOBS_I1
VOBS_I0
SCANSEL
SCANEN
OE_N
OEB_GPIO14
GPIO14
OEB_GPIO13
GPIO13
OEB_GPIO12
GPIO12
OEB_GPIO11
GPIO11
OEB_GPIO10
GPIO10
OEB_GPIO9
GPIO9
OEB_GPIO8
GPIO8
VD_FMT
Digital Correction Signal Processor
PM
ISSUE 4
PMC-2001646
rsd
ay
6.4.3 Instructions
nT
hu
The following is an description of the standard instructions. Each instruction selects an serial test
data register path between input, TDI and output, TDO.
ett
io
BYPASS
uo
fo
liv
The bypass instruction shifts data from input, TDI to output, TDO with one TCK clock period
delay. The instruction is used to bypass the device.
ef
EXTEST
wn
Do
SAMPLE
loa
de
db
yV
inv
The external test instruction allows testing of the interconnection to other devices. When the
current instruction is the EXTEST instruction, the boundary scan register is place between input,
TDI and output, TDO. Primary device inputs can be sampled by loading the boundary scan register
using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan
register using the Shift-DR state. Primary device outputs can be controlled by loading patterns
shifted in through input TDI into the boundary scan register using the Update-DR state.
The sample instruction samples all the device inputs and outputs. For this instruction, the boundary
scan register is placed between TDI and TDO. Primary device inputs and outputs can be sampled
by loading the boundary scan register using the Capture-DR state. The sampled values can then be
viewed by shifting the boundary scan register using the Shift-DR state.
IDCODE
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ISSUE 4
Digital Correction Signal Processor
PM
PMC-2001646
:49
:26
The identification instruction is used to connect the identification register between TDI and TDO.
The device's identification code can then be shifted out using the Shift-DR state.
11
STCTEST
tem
be
r,
20
02
The single transport chain instruction is used to test out the TAP controller and the boundary scan
register during production test. When this instruction is the current instruction, the boundary scan
register is connected between TDI and TDO. During the Capture-DR state, the device
identification code is loaded into the boundary scan register. The code can then be shifted out
output, TDO using the Shift-DR state.
,1
9S
ep
6.4.4 Boundary Scan Cells
IDCODE
ay
Scan Chain Out
rsd
Input
Pad
hu
G1
G2
SHIFT-DR
io
nT
12
1 2 MUX
12
I.D. Code bit
D
C
ett
12
INPUT
to internal
logic
CLOCK-DR
fo
liv
Scan Chain In
Input Observation Cell (IN_CELL)
Do
wn
loa
de
db
yV
inv
ef
uo
Table 6-4
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PMC-Sierra, Inc.
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PM7800 PALADIN-10
Data Sheet
ISSUE 4
Digital Correction Signal Processor
:49
:26
PM
PMC-2001646
Scan Chain Out
1
1
I.D. code bit
r,
1
1
1
1
2
2 MUX
2
2
D
D
C
C
ep
CLOCK-DR
tem
be
SHIFT-DR
OUTPUT
or Enable
MUX
20
G1
G2
IDOODE
02
Output or Enable
from system logic
11
G1
EXTEST
UPDATE-DR
9S
Scan Chain In
Output Cell (OUT_CELL)
inv
ef
uo
IDCODE
yV
I.D. code bit
1
fo
OUTPUT from
internal logic
INPUT
from pin
G1
liv
EXTEST
SHIFT-DR
Scan Chain Out
ett
io
nT
hu
rsd
ay
,1
Figure 6-3
MUX
1
G1
G2
12
1 2 MUX
12
12
D
C
INPUT
to internal
logic
OUTPUT
to pin
D
C
CLOCK-DR
Scan Chain In
Figure 6-4
Bi-directional Cell (IO_CELL)
Do
wn
loa
de
db
UPDATE-DR
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
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PM7800 PALADIN-10
Data Sheet
ISSUE 4
Digital Correction Signal Processor
:49
:26
PM
PMC-2001646
OUTPUT ENABLE
from internal
logic (0 = drive)
11
Scan Chain Out
INPUT to
internal logic
OUTPUT from
internal logic
20
02
OUT_CELL
IO_CELL
tem
be
r,
I/O
PAD
Scan Chain In
ep
Layout of Output Enable and Bidirectional Cells
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
Figure 6-5
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC-Sierra, Inc.
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PM7800 PALADIN-10
Data Sheet
Digital Correction Signal Processor
PM
ISSUE 4
PMC-2001646
:26
7 Absolute Maximum Ratings
11
:49
Maximum rating are the worst case limits that the device can withstand without sustaining
permanent damage. They are not indicative of normal mode operation conditions.
Symbol
Value
r,
Parameter
20
02
Absolute Maximum Ratings
Units
TJ (Absolute)
+150
Junction Temperature under Bias (Operation) 1
TJ (Operation)
-40 to +125
°C
Junction Temperature under Bias (Long-Term) 2
TJ (Long-Term)
-40 to +105
°C
Storage Temperature
TST
Supply Voltage 3,4
VVDDI
Supply Voltage 3,4
VVDD
Voltage on Any Pin
VIN
IIN
liv
ett
DC Input Current
°C
-0.3 to + 3.6
VDC
-0.3 to + 6.0
VDC
-0.3 to 6.0
VDC
±1000
V
±100
mA
±20
mA
+230
°C
uo
fo
Lead Temperature
-40 to +125
9S
,1
ay
rsd
hu
nT
io
Latch-Up Current
°C
ep
Junction Temperature
Static Discharge Voltage
tem
be
Table 7-1
ef
Notes on Power Supplies:
inv
1. Correct operation is not guaranteed outside these limits.
yV
2. Long-term operation outside these limits will reduce reliability.
db
3. VDD must power up before VDDI.
Do
wn
loa
de
4. VDD must not drop below VDDI except when VDDI is not powered.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
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Data Sheet
Digital Correction Signal Processor
PM
ISSUE 4
PMC-2001646
:26
8 DC Characteristics
11
:49
TJ = -40°C to +125°C, VVDD = 3.3 V ± 5%, VVDDI = 1.8V ± 5%
Parameter
Min
Typ
Max
Units
r,
Symbol
20
D.C.Characteristics
Conditions
tem
be
Table 8-1
02
(Typical Conditions: TJ = 25°C, VVDD = 3.3 V, VVDDI = 1.8V)
Pin Power Supply
3.15
3.3
3.45
Volts
Tj = -40°C to 125°C
VDDI
Core Power Supply
1.71
1.8
1.89
Volts
Tj = -40°C to 125°C
VIL
Input Low Voltage
0
0.8
Volts
VIH
Input High Voltage
2.0
VOL
Output or Bidirec-
0
9S
ep
VDD
0.4
ay
0.1
,1
Volts
Volts
hu
nT
uo
fo
liv
ett
io
• IRQ_N
• VD_I[15:0], VD_Q[15:0]
• SD
• TDO
• GPIO[47:0]
IOL = 15mA for
• DAT[15:0]
• WAIT_N
Output or Bidirec-
Volts
yV
loa
de
db
• IRQ_N
• VD_I[15:0], VD_Q[15:0]
• SD
• TDO
• GPIO[47:0]
IOH = -15mA for
• DAT[15:0]
• WAIT_N
wn
Do
VT+
Schmitt Input High
VDD = min
IOH = -4mA for
• VREF_I[15:0], VREF_Q[15:0]
(outputs in scan test mode only)
IOH = -12mA for
inv
tional High Voltage
2.4
ef
VOH
VDD = min
IOL = 4mA for
• VREF_I[15:0], VREF_Q[15:0]
(outputs in scan test mode only)
IOL = 12mA for
rsd
tional Low Voltage
2.2
Volts
Threshold Voltage
VT-
Schmitt Input Low
0.8
Volts
Threshold Voltage
VTH
Schmitt Input Hyster-
0.87
Volts
esis Voltage
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
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Digital Correction Signal Processor
PM7800 PALADIN-10
Data Sheet
ISSUE 4
Symbol
Min
Input Low Leak Cur-
Typ
Max
Units
Conditions
-10
+10
µA
VIL = GND. Note 1
-10
+10
µA
VIH = VDD. Note 1
-10
+10
µA
VIL = GND. Note 1
+50
+400
µA
-300
-10
11
IIL
Parameter
:26
D.C.Characteristics
:49
Table 8-1
Digital Correction Signal Processor
PM
PMC-2001646
IIH
Input High Leak Cur-
02
rent
rent for input with
IIHPD
Input High Leak Cur-
ep
pull-down.
µA
VIL = GND. Note 1
µA
VIH = VDD. Note 1
ay
Input Low Leak Cur-
,1
pull-down.
rent for input with
rsd
pull-up.
-10
Input High Leak Cur-
+10
hu
IIHPU
VIH = VDD. Note 1
9S
rent for input with
IILPU
r,
Input Low Leak Cur-
tem
be
IILPD
20
rent
nT
rent for input with
Output Capacitance
CIO
Bidirectional Capaci-
rent for PM7800
ef
(VDDI)
yV
inv
Core Operating Cur-
uo
tance
IDDOP
Nominal IO Operating
(VDDO)
Current for PM7800
8
pF
8
pF
230
560
(VDDI =
(VDDI =
1.80V)
1.89V)
132
mA
DCLK = 80MHz
mA
VDDO = 3.3V
DCLK = 80MHz
CL = 20pF
loa
de
db
IDDOP
pF
ett
COUT
8
liv
Input Capacitance
fo
CIN
io
pull-up.
Do
wn
Notes on D.C. Characteristics:
1. Positive currents flow into the device (sinking), negative currents flow out of the device
(sourcing).
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Data Sheet
ISSUE 4
Digital Correction Signal Processor
PM
PMC-2001646
:26
9 AC Timing
11
:49
TJ = -40°C to +125°C, VVDD = 3.3 V ± 5%, VVDDI = 1.8V ± 5%
02
Notes on Input Timing:
r,
20
1. When a set-up time is specified between an input and a clock, the set-up time is the time
in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
tem
be
2. When a hold time is specified between an input and a clock, the hold time is the time in
nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input.
9S
ep
3. It is recommended that the transition time on all clock inputs is less than 15 ns.
,1
Notes on Output Timing:
rsd
ay
1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the
reference signal to the 1.4 Volt point of the output.
liv
ett
io
nT
hu
1. Output tristate delay is the time in nanoseconds from the 1.4 Volt point of the reference
signal to the point where the total current delivered through the output is less than or
equal to the leakage current.
uo
Figure 9-1
fo
9.1 RESET_N
RESET_N
20ns
ef
0ns
60ns
80ns
100ns
12
inv
tw
de
db
yV
RESET_N
40ns
RESET_N
loa
Table 9-1
100
max
units
ns
description
notes
RESET_N pulse width.
Do
tw
min
wn
parameter
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ISSUE 4
Digital Correction Signal Processor
PM
PMC-2001646
CPU Interface - DCLK Timing
0ns
5ns
10ns
15ns
20ns
25ns
tch
toz
tah
tem
be
ADR[17:0]
toe
ep
tdp
tdh
,1
9S
DAT[15:0]
tds
r,
tas
20
STRBx,CSx
3
02
tcs
30ns
11
DCLK
:49
Figure 9-2
:26
9.2 CPU Interface
min
units
ns
tcs
3
ns
tch
2
tas
5
tah
0
tds
5
tdh
trp
de
loa
wn
Do
toz
description
notes
DCLK Period.
1
ns
STRB1_N, STRB2_N, CS0_N, CS1_N, CS2 hold time from
DCLK.
1
ns
ADR setup time to DCLK.
1
ns
ADR hold time from DCLK.
1
ns
DAT input-setup time to DCLK.
1
ns
DAT input-hold time from DCLK.
1
12
ns
DAT driven delay from DCLK, 30pF load.
12
ns
DAT propagation delay from DCLK, 30pF load.
12
ns
DAT released delay from STRBx, CSx, 30pF load.
12
ns
IRQ_N propagation delay from DCLK, 30pF load.
yV
inv
ef
uo
fo
STRB1_N, STRB2_N, CS0_N, CS1_N, CS2 setup time to
DCLK.
0
toe
tdp
liv
12.5
db
TDCLK
max
nT
parameter
io
CPU Interface - DCLK Timing
ett
Table 9-2
hu
rsd
ay
IRQ_N
trp
1. The system designer need not worry about violating setup and hold times - all inputs
are treated as asynchronous signals. Setup and hold times are specified here to identify
the clock edge on which the signal is sampled.
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Data Sheet
ISSUE 4
Digital Correction Signal Processor
CPU Interface - CPUCLK Timing
5ns
10ns
15ns
20ns
25ns
30ns
3
11
0ns
:49
Figure 9-3
:26
PM
PMC-2001646
CPUCLK
t ch
02
t cs
20
STRBx,CSx
t chx
t wp
parameter
min
max
ay
CPU Interface - CPUCLK Timing
units
description
notes
rsd
Table 9-3
,1
9S
ep
WAIT_N
tem
be
r,
t csx
STRBx,CSx
8
ns
CPUCLK Period.
tcs
3
ns
STRB1_N, STRB2_N, CS0_N, CS1_N, CS2 setup time to positive edge CPUCLK.
tch
2
ns
tcsx
3
ns
tchx
2
twp
2 (15pF)
5 (15pF)
io
nT
hu
TCPUCLK
ett
liv
fo
ns
STRB1_N, STRB2_N, CS0_N, CS1_N, CS2 hold time from
negative edge CPUCLK (for reads operation with CPUMODE3
= 1).
ns
ns
WAIT_N propagation delay from CPUCLK (CPUMODE4 = 0).
WAIT_N propagation delay from CPUCLK (CPUMODE4 = 1).
uo
ef
STRB1_N, STRB2_N, CS0_N, CS1_N, CS2 setup time to negative edge CPUCLK (for reads operation with CPUMODE3 = 1).
Do
wn
loa
de
db
yV
inv
10 (30pF)
16 (30pF)
STRB1_N, STRB2_N, CS0_N, CS1_N, CS2 hold time from
posedge CPUCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
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9.3 VREF, VOBS, VD Interfaces
:49
9.3.1 Dual-Clock System
Dual-Clock System timing
0ns
5ns
tem
be
Figure 9-4
r,
20
02
11
Use the dual-clock system when VREF is synchronous to REFCLK (usually when VREF is
upsampled internally to the DCLK rate). In this case, a FIFO and interpolator are used to upsample
VREF to the DCLK rate. REFCLK must be created from DCLK such that there is no varying phase
shift that may cause under-run or over-run.
10ns
15ns
T DCLK
25ns
ep
DCLK
20ns
thvobs
9S
tsvobs
,1
VOBS
top
nT
REFCLK
12.5
ett
REFCLK period.
1
ns
DCLK to REFCLK skew.
2
ns
VOBS setup time to DCLK.
ns
VOBS hold time from DCLK.
ns
Output delay from DCLK.
2
ns
VREF setup time to REFCLK.
0
ns
VREF hold time from REFCLK.
3
TDCLK
db
tsvobs
0
de
wn
loa
1.8 (15pF)
Do
notes
ns
0
thref
description
DCLK period.
tskew
tsref
thref
ns
ef
TREFCLK
units
inv
12.5
yV
TDCLK
top
fo
max
uo
min
thvobs
tsref
liv
Dual-Clock System timing
parameter
tskew
io
VREF
Table 9-4
T REFCLK
hu
rsd
ay
VD
7.8 (30pF)
Note:
1. TREFCLK must be an exact integer multiple of TDCLK, i.e. TREFCLK = nTDCLK, where
n = 1,2,...,10. REFCLK must be created from DCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
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:49
:26
2. Skew may exist between DCLK and REFCLK, but this skew must not vary over time
by more than one DCLK period.
11
9.3.2 Single-Clock System
Single-Clock System timing
0ns
5ns
10ns
tem
be
Figure 9-5
r,
20
02
Use the single-clock system when all signals are synchronous to DCLK and the data-rate of VREF
is the same as the output data-rate of VD. In this case, connect the REFCLK pin to VSS, and bypass
the FIFO and interpolator to reduce latency through the chip.
15ns
ep
TDCLK
20ns
tsvref
thvref
ay
,1
VREF
9S
DCLK
rsd
tsvobs
top
nT
hu
VOBS
thvobs
parameter
min
max
3
thvref
0
tsvobs
3
thvobs
yV
inv
ef
tsvref
0
de
1.8 (15pF)
7.8 (30pF)
description
ns
DCLK period.
ns
VREF setup time to DCLK.
ns
VREF hold time from DCLK.
ns
VOBS setup time to DCLK.
ns
VOBS hold time from DCLK.
ns
VD propagation delay from DCLK.
notes
Do
wn
loa
top
units
uo
12.5
db
TDCLK
liv
Single-Clock System timing
fo
Table 9-5
ett
io
VD
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
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:26
9.4 Serial Interface
11
:49
9.4.1 Serial Interface AC Timing
0ns
10ns
20ns
30ns
40ns
50ns
60ns
70ns
r,
AC Timing for Serial Inputs (SCLK, SCS_N, SD, HOP_N)
80ns
90ns
100n
tem
be
Figure 9-6
20
02
All serial inputs are debounced and synchronized to dclk. The minimum pulse width for all serial
input signals is 2TDCLK + setup and hold.
dclk
ep
tw
tnx
9S
tih
tis
tw
,1
PIN
tis
nT
hu
rsd
ay
Debounced_PIN
min
max
units
0
ns
tih
3
tw
2TD + tis + tih
Hold time from DCLK.
1
ns
Pulse width for input.
2
ns
Noise exclusion period.
3
uo
ef
TD - tis - tih
notes
1
ns
yV
inv
tnx
description
Setup time to DCLK.
liv
tis
ett
parameter
io
AC Timing for Serial Inputs (SCLK, SCS_N, SD, HOP_N)
fo
Table 9-6
db
Note:
wn
loa
de
1. The system designer need not worry about violating tis and tih - all inputs are treated as
asynchronous signals. Setup and hold times are specified here to identify the clock edge
on which the signal is sampled.
Do
2. The input signal must be stable for at least two rising edges of DCLK.
3. All serial inputs are debounced on rising and falling edges. The period of noise
(bounce) must be smaller than TD - tis - tih.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
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GPIO
0ns
10ns
20ns
30ns
tis
DAT[15:0]
tih
tw
data_in
ep
tem
be
data_out
max
units
description
3
ns
GPIO input-setup time to DCLK.
tih
2
ns
GPIO input-hold time from DCLK.
tw
2TDCLK + tis + tih
ns
GPIO[31:24] signal width.
top
2 (15pF)
14 (30pF)
ns
toz
2 (15pF)
14 (30pF)
hu
2
GPIO output-driven delay from DCLK.
GPIO output-propagation delay from DCLK.
GPIO output-released delay from DCLK.
uo
fo
liv
ns
1
nT
ns
io
14 (30pF)
ett
2 (15pF)
1
rsd
tis
toe
notes
ay
min
,1
9S
GPIO
parameter
20
toz
r,
toe
02
top
Table 9-7
40ns
11
DCLK
:49
Figure 9-7
:26
9.5 GPIO
inv
ef
1. The system designer need not worry about violating tis and tih - all inputs are treated as
asynchronous signals. Setup and hold times are specified here to identify the clock edge
on which the signal is sampled.
Do
wn
loa
de
db
yV
2. GPIO[31:24] are debounced. The input signal must be stable for at least two rising
edges of DCLK. The period of noise (bounce) must be smaller than TD - tis - tih.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
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JTAG Interface
:49
Figure 9-8
:26
9.6 JTAG Interface
tS
TMS
tH
TMS
tS
TDI
tH
TDI
tem
be
r,
20
TMS
02
11
TCK
9S
ep
TDI
tP
,1
TCK
ay
TDO
nT
hu
rsd
TDO
TRSTB
units
description
5
MHz
TCK Frequency
60
%
TCK Duty Cycle
ns
TMS Set-up time to TCK
ns
TMS Hold time to TCK
ns
TDI Set-up time to TCK
50
ns
TDI Hold time to TCK
ns
TCK Low to TDO Valid
ns
TRSTB Pulse Width
50
tSTDI
50
de
tHTMS
loa
50
Do
tSTMS
db
40
tHTDI
max
inv
min
wn
parameter
ef
JTAG Interface
yV
Table 9-8
uo
fo
liv
ett
io
TRSTB
tV
tPTDO
2
tVTRSTB
100
50
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
notes
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Data Sheet
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Digital Correction Signal Processor
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PMC-2001646
:49
:26
10 Thermal
100
200
Dense Board
23.4
20.7
18.9
JEDEC Board
15.7
14.0
400
500
17.8
17.3
17.1
12.0
11.4
10.9
300
9S
ep
tem
be
r,
Conv
20
Theta JA @1.6W
02
11
Forced Air (Linear Feet per Minute)
ay
,1
12.8
rsd
Notes:
ett
io
nT
hu
1. Dense Board is defined as a 3S3P board and consists of a 3x3 array of device PM7800
located as close to each other as board design rules allow. All PM7800 devices are
assumed to be dissipating 1.6Watts. Theta-JA listed is for the device in the middle of the
array.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
2. JEDEC Board: Theta-JA is the measured value for a single thermal device in the same
package on a 2S2P board following EIA/JESD 51-3.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
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Data Sheet
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Digital Correction Signal Processor
PM
PMC-2001646
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
tem
be
r,
20
02
11
:49
:26
11 Mechanical
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
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Data Sheet
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:26
CONTACTING PMC-SIERRA, INC.
+1 (604) 415-6000
Fax:
+1 (604) 415-6200
Web Site:
http://www.pmc-sierra.com
ep
[email protected]
[email protected]
[email protected]
(604) 415-4533
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
Document Information:
Corporation Information:
Application Information:
tem
be
r,
Tel:
20
02
11
:49
PMC-Sierra, Inc.
8555 Baxter Place,
Burnaby, BC
Canada V5A 4V7
Do
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability
for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other
parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all
representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties
of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement.
In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits,
lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility
of such damage.
© 2002 PMC-Sierra, Inc.
PMC-2001646 (R4)
Issue date: May, 2002
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
63