RDC-19200 MONOBRID® SERIES 10-, 12-, 14-, OR 16-BIT INDUSTRIAL RESOLVER-TO-DIGITAL CONVERTERS FEATURES DESCRIPTION The RDC-19200 Monobrid Series are versatile state-of-the-art resolver-todigital converters featuring programmable resolution and bandwidth and a velocity output voltage. Resolution programming allows selection of 10-, 12-, 14- or 16-bits and are available with commensurate accuracies up to 2 minutes +1 LSB. Resolution programming combines the high tracking rate of a 10-bit converter with the precision of a 16-bit device in one package. The velocity output (VEL) from the RDC-19200 is a ground-based voltage of 0 to ±10 VDC with a linearity of 2.0%. VEL may be scaled up by a sin- • Low Cost gle external resistor to provide up to ±10 VDC for the required maximum tracking rate. • Ideal for Motor Control • Built-In-Test (BIT) and Loss-of- APPLICATIONS Signal (LOS) Outputs The RDC-19200 Series converters are designed for use in modern high performance commercial and industrial control systems. Applications include motor control, theodolite, radar antenna position information, CNC machine tooling, robot axis control, and process control. With their low cost and superior performance, the RDC-19200 Series converters are ideal for motion control and position monitoring applications. • Velocity Output Eliminates Tachometer • Programmable Resolution • Programmable Bandwidth • Accuracy to ±2.3 ARC Min. CONVERTER E SIN θ SIGNAL INPUT RESOLVER 1-4 INPUT HIGH ACCURACY CONTROL TRANSFORMER COS θ ANALOG CONDITIONER e 39 VEL PROG 37 VEL 38 -15 V 36 10k 1 LSB ANTIJITTER FEEDBACK SIN (θ-φ) D DEMODULATOR e GAIN VEL VCO BW BW U T DIFF GAIN OF 2 REFERENCE CONDITIONER DIFF GAIN OF 2.2 + 16 BIT UP/DOWN COUNTER MC U T U/D +15 LOSS OF SIGNAL DETECTOR POWER SUPPLY CONDITIONER EDGE TRIGGERED LATCH DIGITAL INTERFACE 50 ns DELAY 16 BIT CT TRANSPARENT LATCH +11 V INTERNAL DC REF (+5.5 V) V ERROR PROCESSOR DIGITAL ANGLE φ INH 16 BIT OUTPUT TRANSPARENT LATCH 0.4 - 0.7 µs Q +15 3 STATE TTL BUFFER 3 STATE TTL BUFFER TTL BUFFER BIT DETECT INHIBIT TRANSPARENT LATCH T 34 A -15 V Note: A “/” through input or output lines indicates additional functions not shown. See text. +5V OPTIONAL 28 10 LOS EM 12-19 20-27 BITS 1-8 BITS 9-16 11 7 B 8 6 32 31 30 40 29 5 9 35 33 EL S RESOLUTION CONTROL MC U CB REF BIT BW INH GND +5V FIGURE 1. RDC-19200 BLOCK DIAGRAM © 1985, 1999 Data Device Corporation ® Monobrid is a registered trademark of Data Device Corporation. TABLE 1. RDC-19200 SPECIFICATIONS These specifications apply over temperature range, power supply range, reference frequency and amplitude range; ±10% signal amplitude variation and up to10% harmonic distortion in the reference PARAMETER VALUE RESOLUTION 10, 12, 14 or 16 bits ACCURACY GRADES DIFFERENTIAL LINEARITY REPEATABILITY REF INPUT CHARACTERISTICS Voltage Range Single Ended Input Impedance Frequency Range SIGNAL INPUT CHARACTERISTICS Resolver Zin Single Ended Zin Differential Zin Each line-ground Common Mode Range Max Voltage w/o damage Direct Input Signal Type Sin / Cos Voltage Range Max Voltage w/o Damage Zin DIGITAL INPUT/OUTPUT Logic Type Inputs Max Voltage w/o Damage Loading INH (Inhibit) EM (Enable bits1-8) EL (Enable bits 9-16) S (Control Transformer) BW (Bandwidth) DESCRIPTION Programmable 8(1), 4, 3, 2(1) minutes Max +1 LSB of selected resolution, see Ordering Information. 12, 8 or 4 LSBs in the 16th bit, see Ordering Information. 1 LSB max 4-50 Vrms 100k Ohm min, 110k Ohm nom 360 Hz to 6k Hz Voltage options and minimum input impedance, balanced. 11.8 Vrms L-L 70k Ohm 140k Ohm 80k Ohm 26 V peak 100 V transient 2.0 Vrms L-L Sin and Cos resolver signal referenced to converter’s internal DC ref voltage of +5.5 V. 2 Vrms nom, 2.3 Vrms max 15 V continuous, 110 V peak transient >20M Ohm//10 pf voltage follower TTL / CMOS compatible. Logic 0 = 0.8 V max Logic 1 = 2.0 V min -0.3 to 11 V -10 µA max Pull-up current source to +5 V // 5 pf max CMOS transient protected. Logic 0 inhibits, Logic 1 enables, Data stable within 0.3 µs. Logic 0 enables, data valid within 150 ns. Logic 1 high Z within 100 ns. Logic 0 for control Transformer, Logic 1 for normal tracking. Logic 1 = High BW (530 Hz); Logic 0 = Low BW (130 Hz). A (pin 7) B (pin 8) 0 0 0 1 1 0 1 1 Unused outputs bits are at logic 0 Resolution Control 10-Bit 12-Bit 14-Bit 16-Bit OUTPUTS Parallel Data CB (Converter Busy) U (Direction) MC (Major Carry) BIT (Built-in-Test) LOS ( Loss-of-Signal) Drive Capability ANALOG OUTPUTS V (Internal DC ref) VEL (Velocity) e (AC error) See TABLE 4, Dynamic Characteristics. 10, 12, 14, or 16 bits Natural binary angle, positive logic. 0.4 µs to 0.7 µs positive pulse; leading edge initiates counter update. Logic 1 counts up, Logic 0 counts down. Logic 0 at MC. Logic 0 for BIT condition. Logic 1 for LOS (1-3 µA pull-up to +5 V). -1.6 mA at 0.4 V max 0.4 mA at 2.8 V min. Logic 0: 1 TTL Load Logic 1: 10 TTL Loads High Z: 10 µA / 5 pf max +5.5 V nom 50 mVrms per LSB of error 25 mVrms per LSB of error 12.5 mVrms per LSB of error 6.3 mVrms per LSB of error Dynamic Characteristics 2 See TABLE 5, Velocity Characteristics. 10-bit mode. 12-bit mode. 14-bit mode. 16-bit mode. See TABLE 4, Dynamic Characteristics. TABLE 1. RDC-19200 SPECIFICATIONS (CONTINUED) PARAMETER VALUE POWER SUPPLY CHARACTERISTICS Nominal Voltage and Range Max Voltage w/o Damage Max Current DESCRIPTION +15 VDC ± 5% +5V DC ± 10% +18 V 25 mA +8 V 10 mA TEMPERATURE RANGES Operating Storage -15 VDC ±5% Note: When analog outputs are not required, ground -15 V (pin 36). -18 V 15 mA 0°C to +70°C -40°C to +120°C PHYSICAL CHARACTERISTICS Size 1.14 x 2.02 x 0.23 inches (28.96 x 51.3 x 5.84 mm) 0.6 oz (13 g) Weight 40-pin TDIP Note 1: Available for RDC-19202 (2V unit) only. INTRODUCTION The RDC-19200 Series are small, 40-pin TDIP resolver-to-digital hybrid converters. As shown in the block diagram (FIGURE 1), the RDC-19200 can be broken down into the following functional parts: Signal Input Option, Converter, Analog Conditioner, Power Supply Conditioner, and Digital Interface. This lowers oscillator cost and allows a lower power reference oscillator. INTERNAL DC REFERENCE VOLTAGE (V). This internal voltage is not required externally for normal operation of the converter. It is used as the internal DC reference common with the direct input option. It is nominally +5.5 V and is proportional to the +15 VDC supply. SIGNAL INPUT OPTIONS In a resolver, shaft angle data is transmitted as the ratio of carrier amplitudes across the terminals. The converter terminal to the RDC-19200 operates with the signals in the resolver format, SinθCosωt. FIGURE 2 shows the resolver signals as a function of the angle θ. The RDC-19200 accepts solid state resolver (11.8 Vrms) and direct (2 Vrms) inputs. The reference is a singleended input with 100k ohm impedance. 11.8 V RESOLVER INPUT OPTION (RDC-19200) The 11.8 V resolver inputs are true differential inputs with high AC and DC common mode rejection (see FIGURE 4). Input impedance is maintained with power off. The recurrent AC peak + DC common mode voltage should not exceed 26 V peak; maximum transient peak voltage should not exceed 100 V. 2 V DIRECT INPUT OPTION (RDC-19202) The direct inputs are transient protected voltage followers which accept 2 Vrms resolver inputs. as shown in FIGURE 3. A 2 V input from a resolver allows use of a lower reference voltage. RDC-19202 VOLTAGE FOLLOWER BUFFER +V S2-S4 = V MAX MAX - COSθ In Phase with REF of Converter and R2-R1 of CX. +SIN 60 0 30 120 240 150 300 210 θ 330 CCW +S + (DEGREES) CONVERTER 2 V RMS 360 +COS -V 3 2 +C + MAX S1-S3 = -V MAX SIN θ V 1 Standard Resolver Control Transmitter (RX) outputs as a function of CCW Rotation from Electrical Zero (EZ) with R2-R4 excited. FIGURE 2. RESOLVER SIGNALS FIGURE 3. RDC-19202 DIRECT INPUT OPTION -(2 V) 3 RESISTOR PROGRAMMING FOR NON-STANDARD INPUT VOLTAGES CONVERTER OPERATION As shown in FIGURE 1, the converter section of the RDC-19200 contains a high accuracy control transformer, demodulator, error processor, voltage-controlled oscillator (VCO), up-down counter, zero-set timing, and reference conditioner. The converter produces a digital angle φ which tracks the analog input angle θ to within the specified accuracy of the converter. When applying voltages greater than 2 Vrms, a simple voltage divider can be used to attenuate both the sin and the cos inputs. Since the converter inputs are voltage followers, there will be no loading on the resistor dividers (see FIGURE 5). The 11.8 V resolver input conditioner consists of two differential amplifiers. The 11.8 V input is scaled down to 2 V. When applying resolver inputs greater than 11.8 V, four resistors, one in series with each input line, can be used to scale down the voltage (see FIGURE 6). The control transformer performs the following trigonometric computation: sin(θ − φ) = sin θcosφ − cos θsinφ where: θ is angle theta, representing the resolver shaft position φ is digital angle phi, contained in the up/down counter. The tracking process consists of continually adjusting φ to make (θ − φ) → 0, so that φ will repeat the shaft position θ. RDC-19200 RESOLVER CONDITIONER 12k S1 S3 1 The output of the demodulator is an analog DC level proportional to sin(θ − φ). The error processor receives its input from the demodulator and integrates this sin(θ − φ) error signal which then drives the VCO. The VCOs clock pulses are accumulated by the up/down counter. The velocity voltage accuracy, linearity and offset are determined by the quality of the VCO. Functionally, there are two stages of integration which makes the converter a Type II tracking servo. 70.8k - 3 +S + 70.8k V 12k CONVERTER 11.8 V RMS In a Type II servo, the VCO always settles to a counting rate which makes the dφ/dt equal to dθ/dt without lag. The output data will always be fresh and available as long as the maximum tracking rate of the converter is not exceeded. 12k S4 S2 4 70.8k - 2 +C + The reference conditioner is a comparator that produces the square wave reference voltage which drives the demodulator. It is single-ended ground-based with an input of Z of 100k ohms min, 110k ohms nom, resistive. 70.8k V 12k FIGURE 4. RESOLVER INPUT OPTION - (11.8 V) R1 3 S3 R1 SIN S3 R2 R3 S1 R2 2 S2 S1 COS RDC-19202 R3 S2 R4 S4 R4 1 S4 V 3 1 2 4 S3 S1 RDC-19200 S2 S4 R + 70.8k Input Voltage L-L = 70.8k 11.8 V Notes: (1) Input Voltage L-L is greater than 11.8 V. (2) R = R1 = R2 = R3 = R4 to 0.1% match. Input Voltage L-L R1 + R3 = 2V R3 Notes: (1) R1 = R2; R3 = R4 to 0.1% match. (2) R1 + R3 and R2 + R4 should be as high as possible to minimize resolver loading. FIGURE 6. INPUT RESISTOR SCALING - (11.8 V) FIGURE 5. INPUT RESISTOR SCALING - (2 V) 4 Speed Voltage = (rotational speed/carrier freq) * F.S. signal Where: Speed Voltage is the quadrature due to rotation. Rotational speed is the RPS (rotations per second) of the resolver. Carrier Frequency is the REF in Hz. MINIMIZING ERRORS DUE TO QUADRATURE In those applications where highest accuracy is needed, the REF input can be phase shifted by adding a capacitor in series with the REF input (pin 40) to add a phase lead equal to the nominal phase lead of the resolver input. To determine the capacitor’s value, see FIGURE 7. ANALOG CONDITIONER The Analog Conditioner section performs three functions. It converts analog ground from 5.5 V to 0 V, provides a gain of 2 for AC Error (e) and a gain of 2.2 for Velocity (VEL) The velocity scaling sensitivity can be increased with an external resistor. Refer to VEL PROGRAMMING section for more information. RDC-19200 POWER SUPPLY CONDITIONER C REF 40 100k The power supply conditioner lowers the internal power supply voltage to the custom CMOS chip to +11 V from the +15 V supply. The +11 V will track the +15 V. Internal analog ground is one half of 11 V or +5.5 V, nom. Va 10k 100 pf V DIGITAL INTERFACE Note: Choose C such that the Va to REF phase lead is equal to the resolver to REF phase lead plus 9 µs. The digital Interface circuitry performs three main functions: 1. Latches the output bits during an Inhibit (INH) command allowing stable data to be read out of the RDC-19200. 2. Furnishes parallel tri-state data formats. 3. Acts as a buffer between the internal CMOS logic and the external TTL logic. FIGURE 7. PHASE SHIFTING THE REF INPUT In the RDC-19200, applying an inhibit (INH) command will lock the data in the output transparent latch without interfering with the continuous tracking of the converter’s feedback loop. Therefore, the digital angle φ is always updated, and the INH can be applied for an arbitrary amount of time. The Inhibit Transparent Latch and the 50 ns delay are part of the inhibit circuitry. For further information, see the INHIBIT (INH, pin 9) paragraph. QUADRATURE VOLTAGES In a resolver, quadrature voltages are by definition the resulting 90° fundamental signal in the nulled out error voltage (e) in the converter. A digital position error will result due to the interaction of this quadrature voltage and a reference phase shift between the converter signal and reference inputs. The magnitude of this error is given by the following formula: The BIT detect circuitry monitors the error level (D) from the demodulator and the LOS (loss-of-signal) detector senses disconnected resolver inputs. Magnitude of Error = (Quadrature Voltage/F.S. signal) * tan (α) Where: LOGIC INPUT/OUTPUT Magnitude of Error is in radians. Quadrature Voltage is in volts. Full Scale signal is in volts. α = signal to REF phase shift. The digital angle outputs are buffered and provided in a two-byte format. The first byte contains the MSBs bits (1-8) and is enabled by placing EM (pin 10) to a logic 0. Depending on the user-programmed resolution, the second byte contains the LSBs and is enabled by placing EL (pin 11) to a logic 0. The second byte will contain either bits 9-10 (10-bit resolution), bits 9-12 (12-bit resolution), bits 9-14 (14-bit resolution) or bits 9-16 (16-bit resolution). All unused LSBs will be at logic 0. TABLE 2 lists the angular weight for the digital angle outputs. An example of the magnitude of error is as follows: Let: Quadrature Voltage = 11.8 mV Let: F.S. signal = 11.8 mV Let: a = 6° Then: Magnitude of Error = 0.35 min • 1 LSB in the 16 bit. Note: Quadrature is composed of static quadrature which is specified by the resolver supplier plus the speed voltage which is determined by the following formula: The digital angle outputs are valid 150 ns after EM or EL are activated with a logic 0, and are high impedance within 100 ns, max, 5 TABLE 2. DIGITAL ANGLE OUTPUTS BIT DEG/BIT MIN/BIT 180 90 45 22.5 11.25 5.625 2.813 1.405 0.7031 0.3516 0.1758 0.879 0.439 0.0220 0.0110 0.0055 1 (MSB ALL MODES) 2 3 4 5 6 7 8 9 10 (LSB 10-BIT MODE) 11 12 (LSB 12-BIT MODE) 13 14 (LSB 14-BIT MODE) 15 16 (LSB 16-BIT MODE) the latch will not lock until the CB pulse is over. The purpose of the 50 ns delay is to prevent a race condition between CB and INH where the up-down counter begins to change as an INH is applied. 10,800 5,400 2,700 1,350 675 387.5 168.5 84.38 42.19 21.09 10.55 5.27 2.64 1.32 0.66 0.33 An INH input, regardless of its duration, does not affect the converter update. A simple method of interfacing to a computer asynchronous to CB is: (1) (2) (3) (4) Apply INH Wait 0.3 µs, min Transfer the data Release INH As long as the converter maximum tracking rate is not exceeded there will be no velocity lag in the converter output, although momentary acceleration errors remain. If a step input occurs, as when the power is initially applied, the response will be critically damped. FIGURE 10 shows the response to a step input. After initial slewing at the maximum tracking rate of the converter, there is one overshoot (which is inherent in a Type II servo). The overshoot settling to a final value is a function of the small signal settling time. Note: EM enables the 8 MSBs and EL enables the LSBs. after EL and EM are set to logic 1. Both enables are internally pulled up to +5 V by -10 µA max current sources. DIGITAL ANGLE OUTPUT TIMING DATA TRANSFERS The digital angle output is 10, 12, 14 or 16 parallel data bits. All logic outputs are short-circuit proof to ground and +5 V. The CB output is a positive, 0.4 to 0.7 µs pulse. Digital output data from the RDC-19200 can be transferred to 8bit and 16-bit bus systems. For 8-bit systems, the MSB and LSB bytes are transferred sequentially (see FIGURES 11 and 12). For 16-bit systems, all bits are transferred at the same time ( see FIGURES 13 and 14). The digital output data changes approximately 50 ns after the leading edge of the CB pulse because of an internal delay (shown in FIGURE 1). Data is valid 0.2 µs after the leading edge of CB (see FIGURE 8). The angle is determined by the sum of the bits at logic 1. 1.22 µs MIN ASYNCHRONOUS TO CB DEPENDS ON dφ/dt 0.4-0.7µs INH CB 0.2 µs MAX DATA ,, 0.3 µs MAX , , DATA VALID VALID ,, FIGURE 9. INHIBIT TIMING FIGURE 8. CB TIMING INHIBIT (INH, PIN 9) OVERSHOOT When an Inhibit (INH) input is applied to the RDC-19200, the Output Transparent Latch is locked, causing the output data bits to remain stable while data is being transferred (see FIGURE 9). The output data bits are stable 0.3 µs after the INH is driven to logic 0. θ2 A logic 0 at the T input of the Inhibit Transparent Latch latches the data, and a logic 1 applied to T allows the bits to change. This latch also prevents the transmission of invalid data when there is an overlap between CB and INH. While the counter is not being updated, CB is at logic 0 and the INH latch is transparent; when CB goes to logic 1, the INH latch is locked. If CB occurs after INH has been applied, the latch will remain locked and its data will not change until CB returns to logic 0; if INH is applied during CB, θ1 SMALL SIGNAL SETTLING TIME MAX SLOPE EQUALS TRACKING RATE (SLEW RATE) FIGURE 10. RESPONSE TO STEP INPUT 6 EL EL EM (MSB) BIT 1 D15 D6 BIT 2 D14 BIT 3 D5 BIT 3 D13 BIT 4 D4 BIT 4 D12 BIT 5 D3 BIT 5 D11 BIT 6 D2 BIT 6 D10 BIT 7 D1 BIT 7 D9 BIT 8 D0 BIT 8 D8 BIT 9 D7 BIT 10 BIT 10 D6 BIT 11 BIT 11 D5 BIT 12 BIT 12 D4 BIT 13 D3 BIT 14 D2 BIT 15 D1 (LSB) BIT 16 D0 (MSB) BIT 1 D7 BIT 2 EM RC-19200 8-BIT BUS RDC-19200 BIT 9 BIT 13 BIT 14 BIT 15 (LSB) BIT 16 INH 16-BIT BUS INH FIGURE 11. 8-BIT DATA TRANSFER FIGURE 13. 16-BIT DATA TRANSFER INH 300 ns MIN EM INH 150 ns MIN 300 ns MIN DATA 1-8 VALID EL 100 ns MAX EM, EL DATA 1-8 VALID 150 ns MIN 150 ns MIN 100 ns MAX DATA 9-16 VALID 100 ns MAX FIGURE 14. 16-BIT DATA TRANSFER TIMING FIGURE 12. 8-BIT DATA TRANSFER TIMING 7 TURNS COUNTING PROGRAMMABLE RESOLUTION CB Resolution is controlled by two logic inputs, A and B (see TABLE 3). The resolution can be changed during converter operations so the appropriate resolution and velocity dynamics can be changed as needed. To ensure that a race condition does not exist between counting and changing the resolution, inputs A and B are transferred through the latch internally on the trailing edge of CB (see FIGURE 15). RDC-19200 U U T MC C1 UP/DOWN COUNTER C0 4 BITS TABLE 3. RESOLUTION CONTROL Notes: (1) For the 4 bit up/down counter, use 74LS169B (TTL) or 4516 (CMOS). (2) U = up/down line, logic 1 counts up. (3) T = toggle line, counts on positive edge. B (PIN 8) A (PIN 7) RESOLUTION 0 0 10-BIT 0 1 12-BIT 1 0 14-BIT 1 1 16-BIT Note: All unused digital output data bits are at logic 0 FIGURE 16. TURNS COUNTING CONNECTION DIAGRAM CB FASTER SETTLING TIME USING BIT TO REDUCE RESOLUTION 0.5 µs MIN MAJOR CARRY MC Since the RDC-19200 has higher precision in the higher resolution mode and faster settling in the lower resolution modes, the BIT output can be used to program the RDC-19200 for lower resolution, allowing the converter to settle faster for step inputs. High precision, faster settling can therefore be obtained simultaneously and automatically in one unit. 20 ns MIN ,,,,,, , 0.5 µs MIN DIRECTION (U) When the resolution is changed, the VEL scaling is also changed. Since the VEL output is from an integrator with a capacitor feedback, the VEL voltage cannot change instantaneously. Therefore, when changing resolution while moving, there will be a transient with a magnitude proportional to the velocity and a duration determined by the converter bandwidth (see FIGURE 22.) UP COUNT 0.5 µs MIN 0.5 µs MIN DOWN COUNT 0.5 µs MIN DON'T CARE FIGURE 17. DIRECTION OUTPUT (U) TIMING SYSTEM SELF-TEST The RDC-19200 provides two useful logic outputs for systems self-test, BIT and LOS. CB ,,, ,, 0 µs MIN BUILT-IN-TEST (BIT, PIN 29) 0.1 µs MIN A,B The Built-in-Test output (BIT) monitors the level of error from the demodulator (D). D represents the difference in the input and output angles and ideally should be zero. If it exceeds approximately 65 LSBs ( of the selected resolution), the logic level at BIT will change from a logic 1 to logic 0. This condition will occur during a large step and reset after the converter settles out. BIT will also change to logic 0 for an over-velocity condition because the converter loop cannot maintain input-output sync, or if the converter malfunctions where it cannot maintain the loop at a null. VALID FIGURE 15. RESOLUTION CONTROL TIMING MAJOR CARRY (MC, PIN 32) Major Carry is used with Direction Output (U) for multi-turn applications. This signal is similar to the popular MSI four bit up-down counter CO (Carry Out), that is, it is normally high and goes low for all 1’s when counting up or all 0’s when counting down. See FIGURE 16 for a typical interconnection. LOSS OF SIGNAL (LOS, PIN 28) The Loss of Signal (LOS) output is used for system safety. The LOS output changes from logic 0 to 1 if both resolver inputs are disconnected. With disconnected resolver inputs unpredictable converter performance occurs. DIRECTION OUTPUT (U, PIN 31) Direction Output (U) timing is shown in FIGURE 17. It is a logic 1 to count up and logic 0 for down. The logic level at (U) is valid at least 0.5 µs before and at least 20 ns after leading edge of CB. If the LOS signal is used with the 2 V Direct Input option, connect a 10M ohm resistor from +S to V and from +C to V. This will insure that if the input resolver signal opens, the input pin will go to V volts. 8 PROGRAMMABLE BANDWIDTH (BW, PIN 5) CONTROL TRANSFORMER MODE (S, PIN 6) Either low or high bandwidth can be selected by using the BW logic input. A logic 0 applied to BW selects low bandwidth (130 Hz nom), while a logic 1 selects high bandwidth (530 Hz nom). Bandwidth can be changed during converter operation. The converter will function as a Control Transformer (CT) by placing S (pin 6) to logic 0. In the CT mode the digital inputs are double buffered, EM is redefined as LM, EL is redefined as LL and INH becomes LA (see FIGURES 19 and 28). FIGURE 18 shows CT mode timing for a two byte transfer. Bandwidth and the acceleration constant (Ka) can be determined from the following formulas: The CT mode is used when the AC error (e) is needed to drive an external control loop by the difference angle of the resolver input and the digital input. It is also used for presettling the converter to a specific angle to reduce the step response time. Closed Loop Bandwidth (Hz) = √2 A/π Ka = A2 See Dynamic Characteristics TABLE 4 and FIGURES 25 to 27 (LA) INH for values. tsui S=0 TABLE 4. DYNAMIC CHARACTERISTICS PARAMETER UNITS RESOLUTION BITS Input Frequency Tracking Rate Bandwidth, CL Ka A1** A2** A** B** acc-1 LSB lag Settling Time HIGH 12 LOW 14 kHz 1-6 * 2-6 RPS† 800 200 50 Hz 530 * * 1/sec2 1.4M * * 1/sec 8 * * 1/sec 178 * * 1/sec 1200 * * 1/sec 600 * * °/sec2 512k 128k 32k msec 10 15 30 16 10 NR 12.5 * * * * * * 8k 75 ,, ,, tsu BANDWIDTH 10 thui 12 14 DATA IN 16 th .36-6 * * 2-6 200 50 12.5 3.2 130 * * * 90k * * * 2 * * * 45k * * * 300 * * * 150 * * * 32k 500 2k 500 40 300 120 300 (LM) EM th tsu tw tw (LL) EL Notes: (1) tw = 100 ns min (pulse width) th = 50 ns min (hold time) thui = 0 ns min (hold time inhibit) tsu = 0 ns min (setup time) tsui = 300 ns min (setup inhibit) (2) When S is low: (LM) EM is latch control for MSB byte, (LL) EL is latch control for LSB byte, †RPS (Revolutions per Second) maximum * Same as value to left ** See Figure 25 for definition of A1, A2, A, and B 1 - data held in latch 0 - latch is transparent (3) (LA) INH is latch control for CT latch, 1 - latch is transparent 0 - data held in latch. FIGURE 18. CT MODE TIMING - TWO BYTE TRANSFER, DOUBLE BUFFERED LOS 28 LOSS OF SIGNAL DETECTOR SIN θ RESOLVER 1-4 INPUT SIGNAL INPUT COS θ HIGH ACCURACY CONTROL TRANSFORMER SIN (θ-φ) GAIN e D DEMODULATOR REFERENCE CONDITIONER 40 REF BIT DETECT 29 BIT +15 V LA(INH) 9 16 BIT CT TRANSPARENT LATCH DIFF GAIN OF 2 DIGITAL ANGLE φ -15 V 16 BIT U-D COUNTER (SET MODE) +11 V +5.5 V 7 A LM(EM) 10 11 LL(EL) 12-19 20-27 1-8 39 e 8 B RESOLUTION CONTROL 9-16 FIGURE 19. CONTROL TRANSFORMER BLOCK DIAGRAM 9 POWER SUPPLY CONDITIONER 34 +15 V , ANALOG OUTPUTS TABLE 5. VELOCITY OUTPUT CHARACTERISTICS PARAMETER TYP MAX UNIT Polarity Positive for increasing angle RPS/V Voltage scaling See Table 6 % 10 15 Scale factor PPM/°C 100 200 Scale factor TC 5 1 2 Reversal error The analog outputs are AC error (e) and velocity (VEL). If the analog outputs are not required, ground -15 V (pin 36). AC ERROR (e, PIN 39) AC Error Out (e) is used in CT mode. The AC error is proportional to the difference between the resolver input angle θ and the digital angle φ, (θ - φ), with a scaling of: 50 mVrms/LSB (10-bit mode) 25 mVrms/LSB (12-bit mode) 12.5 mVrms/LSB (14-bit mode) 6.3 mVrms/LSB (16-bit mode) The error is positive if it is in phase with the reference and negative if it is out of phase with the reference. Linearity % output 1 2 Zero offset Zero Offset TC Load Output voltage mV µV/°C k Ohms V 15 25 ±13 40 50 3 ±10 TABLE 6. VELOCITY OUTPUT VOLTAGE SCALING (RPS/VOLT) The e output can swing ±10 V peak min with respect to ground when the voltage level of the ±15 V power supplies are 15 V. The output level range changes proportionally with the power supply level. BW 10-BIT 12-BIT 14-BIT 16-BIT HIGH 80 20 5 1.25 LOW 20 5 1.25 0.32 VELOCITY (VEL, PIN 38) The velocity output (VEL, pin 38) is a DC voltage proportional to angular velocity dθ/dt. The velocity is the input to the voltagecontrolled oscillator (VCO), as shown in FIGURE 1. Its linearity and accuracy is dependent solely on the linearity and accuracy of the VCO. DYNAMIC PERFORMANCE A Type II servo loop (Kv = ¥) and very high acceleration constants give the RDC-19200 superior dynamic performance as listed in TABLE 1. The maximum VEL output can swing ±10 V min with respect to ground when the voltage level of the ±15 V power supplies are 15 V. The output level range changes proportionally with the power supply level. The analog output VEL characteristics are listed in TABLE 5. SMALL SIGNAL STEP RESPONSE FIGURE 20 illustrates the Small Signal Step Response (100 LSB step) for low and high bandwidth for the four resolutions. The VEL output has the DC tachometer quality specifications such that it can be used as the velocity feedback in servo applications. LARGE SIGNAL STEP RESPONSE FIGURE 21 illustrates the Large Signal Step Response (179° step) for low and high bandwidth for the four resolutions. VELOCITY PROGRAMMING (VEL PROG, PIN 37) BIT OUTPUT REDUCES SETTLING TIME The velocity output scale factor can be increased by connecting an external resistor (R) from VEL PROG, pin 37, to ground. By scaling up the output, the noise and offset will increase proportionally. The value of R can be determined by the following formula: R = 10 x B/A 1 - B/A Where: R = external resistor in k Ohms A = specified voltage scaling (RPS/VOLT) B = desired voltage scaling (RPS/VOLT) To determine A refer to TABLE 6, Voltage Scaling. By using the BIT output together with the A and B inputs, the Large Signal Settling Time may be significantly reduced. FIGURE 22 shows the connections required for BIT, A, and B and the resultant settling for the different resolution modes. VELOCITY RESPONSE A filter on the VEL output will, for a step input in velocity, eliminate the velocity overshoot (normally critically damped) and filter carrier frequency ripple. FIGURE 23 shows the VEL output with and without a filter for low and high bandwidths. The VEL filter is shown in FIGURE 24. RDC-19200 37 VEL PROG R 10 100 Output (LSBs) Output (LSBs) 100 0 0 10 20 30 40 2 50 4 6 8 10 Time (ms) Time (ms) LOW BANDWIDTH - 10-BIT MODE HIGH BANDWIDTH - 10-BIT MODE 100 Output (LSBs) Output (LSBs) 100 0 0 10 20 30 40 4 50 8 12 16 20 Time (ms) Time (ms) HIGH BANDWIDTH - 12-BIT MODE LOW BANDWIDTH - 12-BIT MODE 100 Output (LSBs) Output (LSBs) 100 0 0 10 20 30 40 2 50 4 6 8 10 Time (ms) Time (ms) HIGH BANDWIDTH - 14-BIT MODE LOW BANDWIDTH - 14-BIT MODE 100 Output (LSBs) Output (LSBs) 100 0 0 10 20 30 40 20 50 40 60 80 100 Time (ms) Time (ms) HIGH BANDWIDTH - 16-BIT MODE LOW BANDWIDTH - 16-BIT MODE FIGURE 20. SMALL SIGNAL STEP RESPONSE (100 LSB STEP) 11 180 Output Angle (degrees) Output Angle (degrees) 180 120 60 120 60 0 0 10 20 30 40 1 50 LOW BANDWIDTH - 10-BIT MODE Output Angle (degrees) Output Angle (degrees) 4 5 180 120 60 0 120 60 0 10 20 30 40 50 2 Time (ms) 4 6 8 10 Time (ms) LOW BANDWIDTH - 12-BIT MODE HIGH BANDWIDTH - 12-BIT MODE 180 180 Output Angle (degrees) Output Angle (degrees) 3 HIGH BANDWIDTH - 10-BIT MODE 180 120 60 0 120 60 0 20 40 60 80 100 10 Time (ms) 20 30 40 50 Time (ms) LOW BANDWIDTH - 14-BIT MODE HIGH BANDWIDTH - 14-BIT MODE 180 Output Angle (degrees) 180 Output Angle (degrees) 2 Time (ms) Time (ms) 120 60 120 60 0 0 20 40 60 80 20 100 40 60 80 100 Time (ms) Time (ms) LOW BANDWIDTH - 16-BIT MODE HIGH BANDWIDTH - 16-BIT MODE FIGURE 21. LARGE SIGNAL STEP RESPONSE (179° STEP) 12 180 Output Angle (degrees) Output Angle (degrees) 180 120 BIT A B 60 0 120 BIT B 60 0 10 20 30 40 50 2 Time (ms) 6 8 10 HIGH BANDWIDTH - 12- TO 10-BIT MODE 180 180 Output Angle (degrees) Output Angle (degrees) 4 Time (ms) LOW BANDWIDTH - 12- TO 10-BIT MODE 120 A BIT 60 B 0 120 A 60 BIT B BIT A 0 10 20 30 40 50 2 Time (ms) 4 6 8 10 Time (ms) HIGH BANDWIDTH - 14-TO 10-BIT MODE LOW BANDWIDTH - 14-TO 10-BIT MODE 180 Output Angle (degrees) 180 Output Angle (degrees) A 120 BIT A B 60 120 B 60 0 0 10 20 30 40 2 50 4 6 8 10 Time (ms) Time (ms) HIGH BANDWIDTH - 16- TO 10-BIT MODE LOW BANDWIDTH - 16- TO 10-BIT MODE FIGURE 22. USING BIT TO REDUCE SETTLING TIME (179° STEP) 13 BEFORE FILTER Voltage (1 V/div) Voltage (1 V/div) BEFORE FILTER AFTER FILTER 0 10 20 30 40 50 AFTER FILTER 0 4 8 Time (ms) 10 12 16 Time (ms) LOW BANDWIDTH - 12-10-BIT MODE HIGH BANDWIDTH - 12-10-BIT MODE BEFORE FILTER Voltage (1 V/div) Voltage (1 V/div) BEFORE FILTER AFTER FILTER 0 10 20 30 40 50 AFTER FILTER 0 4 Time (ms) 8 10 12 16 Time (ms) LOW BANDWIDTH - 14-10-BIT MODE HIGH BANDWIDTH - 14-10-BIT MODE BEFORE FILTER Voltage (1 V/div) Voltage (1 V/div) BEFORE FILTER AFTER FILTER 0 10 20 30 40 50 AFTER FILTER 0 4 8 Time (ms) 10 12 16 Time (ms) LOW BANDWIDTH - 16-10-BIT MODE HIGH BANDWIDTH - 16-10-BIT MODE FIGURE 23. VEL OUTPUT WITH AND WITHOUT FILTER R=100k VEL C = 0.033 µF R=100k VEL FILTERED (LOW BW) VEL C = 0.0082 µF τ = RC = 1/A τ = RC = 1/A FIGURE 24. VEL OUTPUT FILTERS 14 VEL FILTERED (HIGH BW) TRANSFER FUNCTIONS RDC-19200 APPLICATIONS The dynamic performance of the converter can be determined from its transfer function block diagram (FIGURE 25) and open and closed loop Bode plots (FIGURES 26 and 27). TABLE 4 lists the parameters relating to the RDC-19200’s dynamic characteristics for different resolution and bandwidth modes. USING THE RDC-19200 IN THE CT MODE ACCURACY AND RESOLUTION MULTI-TURN APPLICATIONS - USE OF MAJOR CARRY (MC, PIN 32) The CT mode can be applied in servo systems, as shown in FIGURE 28. In this application, changes in position are commanded by the computer through signals fed to the CT. The CT then drives the motors through DC power amplifiers. TABLE 7 lists the total accuracy including quantization for the various resolution and accuracy grades. Refer to Major Carry paragraph on page 8 for details. USING THE RDC-19200 AS AN R/D WITH VEL TO STABILIZE POSITION LOOP TABLE RDC-19200 SERIES MODEL NO. RDC-19202-304 RDC-1920X-303 RDC-1920X-302 RDC-19202-301 7. ACCURACY/RESOLUTION ACCURACY 10 12 BIT BIT 2’ + 1 LSB 23.1 7.3 3’ + 1 LSB 24.1 8.3 4’ + 1 LSB 25.1 9.3 8’ + 1 LSB 29.1 13.3 14 BIT 3.3 4.3 5.3 9.3 FIGURE 29 illustrates a typical use of an RDC-19200 connected as an R/D using the VEL output to stabilize the position loop. 16 BIT 2.3 3.3 4.3 8.3 VELOCITY OUT ERROR PROCESSOR CT + RESOLVER INPUT e VCO A2 S A1 S + 1 B S S +1 10B - DIGITAL POSITION OUT (φ) H=1 CONVERTER TRANSFER FUNCTION G= A2 S + 1 B S2 S +1 10B WHERE: A 2 = A1 A 2 Note: See TABLE 4 for values of A1, A2, and B. FIGURE 25. TRANSFER FUNCTION BLOCK DIAGRAM 2 -1 ct /o db 4 2A B A 2A -6 db ω (rad/sec) 10B /oc 2 2A ω (rad/sec) CLOSED LOOP BW (Hz) = t FIGURE 27. CLOSED LOOP BODE PLOT FIGURE 26. OPEN LOOP BODE PLOT 15 2A π INTERFACING THE RDC-19200 WITH AN IBM PC/XT/AT® RDC-19200 TO IBM PC/XT/AT THEORY OF OPERATION The RDC-19200 can be connected to an IBM PC/XT/AT through the IBM PC Bus located at address HEX 300 through 303. This location is reserved by the PC for prototype cards. FIGURE 31 illustrates the connection to the IBM PC Bus; FIGURE 30 illustrates the timing considerations for the interface. 1. The port address where the RDC-19200 is located is hard wired with jumpers into the 74LS688 address decoder. This address is HEX 300 through 303 and is reserved for prototype cards. 2. Address line A1 selects the upper or lower of the RDC-19200 to be placed on the Bus. When A1 is high, bits 1-8 are selected. 3. Address line A0 sets and resets the RDC-19200 INHIBIT line. When A0 is low, the INHIBIT command INH is invoked. RESOLVER 4. To read the output of the RDC-19200, perform the following: a. Send address HEX 302 to INHIBIT the RDC-19200 (hold data stable) and place bits 1-8 on the Bus. Read and store data on D0 to D7. AMP DEMODULATOR e RDC-19200 as a CT b. Send address 300 HEX to keep the RDC-19200 in the INHIBIT mode and place bits 9-14 on the Bus. Read and store data on D0 and D7. REF S c. Read address 301 HEX or 303 HEX to release the RDC-19200 from the INHIBIT mode and prepare for the next measurement. No valid data will be on the bus during this command. µ COMPUTER FIGURE 28. CT MODE APPLICATION 5. Since the output data is not valid until 0.5 µs after the INHIBIT command is invoked, the I/O READY line is held low for this period of time. When I/O READY returns to the high level, the data on the bus reads on the next negative clock edge. LATCH READ DATA RESOLVER REF SOURCE AMP D/A COMPUTER CLK OUT ALE OUT ADDR R/D CONVERTER VALID ADDRESS OUT 500 nsec MIN PULSE I/O READY IN VEL OUT I/O R FIGURE 30. PC APPLICATION - I/O READ CYCLE TIMING FIGURE 29. R/D WITH VEL TO STABILIZE POSITION 16 BIT 16(LSB) BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 500 nSEC MIN PULSE BIT 10 74LS121 BIT 9 D7 Y1 D6 Y2 D5 Y3 D4 Y4 D3 Y5 D2 Y6 D1 Y7 D0 Y8 Q BIT 8 RDC-19200 BIT 7 BIT 6 A2 BIT 5 BUS DRIVER 74LS465 BIT 4 BIT 3 74LS467 INH BIT 2 Q BIT 1 (LSB) EM G CLK D EL IBM BUS Y1 I/O READ Y2 G Y3 Y4 A3 A4 74LS374 ALE A1 G P=Q A9 P0 Q0 A8 P1 Q1 A7 A5 P2P Q2 ADDRESS P3 DECODER Q3 74LS688 P4 Q4 A4 P5 Q5 A3 P6 Q6 A2 P7 Q7 A6 A2 3 STATE BUFFER ADDRESS SELECTION JUMPERS A1 A0 I/O READY FIGURE 31. RDC-19200 TO PC CONNECTION DIAGRAM 17 TABLE 8. RDC-19200 PIN FUNCTIONS PIN NO TITLE I/O 1 S1(R)V(X) I (R) = 11.8 V Resolver input; (X) = V Return (DO NOT GND). 2 S2(R)+C(X) I (R) = 11.8 V Resolver input; (X) = 2 V cos input. 3 S3(R)+S(X) I (R) = 11.8 V Resolver input; (X) = 2 V sin input. 4 S4(R) I (R) = 11.8 V Resolver input. 5 BW I Bandwidth. Logic 1 for high BW (530 Hz); logic 0 for low BW (130 Hz). I Control Transformer Set. Logic 1 for normal tracking; logic 0 for CT operation. Used when AC error (e) is needed to drive external control loop by the difference angle of the resolver input and the digital input and for presetting the converter to a specific angle to reduce the step response time. 6 S 7 8 A B I 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 INH EM EL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 I I I O O O O O O O O O O O O O O O O 28 LOS O 29 BIT O 30 31 CB U O O 32 MC O 33 34 35 36 +5 V +15 V GND -15 V I I I 37 VEL PROG I 38 VEL O 39 e O 40 REF I FUNCTION Resolution Control. Changes resolution during converter operation to 10, 12, 14 or 16 bit, depending on logic level. A Resolution B 0 0 10-bit 0 1 12-bit 1 0 14-bit 1 1 16-bit Inhibit. Logic 0 prevents digital output bits from changing. Enable MSB’s Logic 0 enables digital output bits 1-8. Logic 1 disables these bits. Enable LSB’s Logic 0 enables digital output bits 9-16. Logic 1 disables these bits. Digital Output Bit 1 (MSB all modes). Digital Output Bit 2. Digital Output Bit 3. Digital Output Bit 4. Digital Output Bit 5. Digital Output Bit 6. Digital Output Bit 7. Digital Output Bit 8. Digital Output Bit 9. Digital output Bit 10 (LSB- 10-bit MODE). Digital output Bit 11. Digital output Bit 12 (LSB - 12-bit MODE). Digital output Bit 13. Digital output Bit 14 (LSB - 14-BIT MODE). Digital output Bit 15. Digital output Bit 16 (LSB - 16-BIT MODE). Loss of signal. Used for system safety, the LOS output changes from logic 0 to 1 if both resolver inputs are disconnected. Built-in-Test. Monitors level of error (D) and will change to logic if it exceeds 65 bits, approx. Also logic 0 for an over velocity condition. Converter Busy Indicates digital output update. Direction. Logic 1 to count up; logic 0 to count down. Major Carry. Used for turns counting applications; normally high; goes low for all 1’s when counting up or all 0’s when counting down. Supply Voltage. Supply Voltage. Ground. Supply Voltage. Velocity Programming. Increases output scale factor with external resistor (R) from VEL PROG, pin 37 to ground. Velocity. DC voltage proportional to angular velocity. AC Error. Used in CT mode; e is proportional to the difference between the resolver input angle θ and the digital output angle φ ( θ - φ ). AC Reference Input. Used to drive internal demodulator. 18 REFERENCE OSCILLATOR STATOR LO HI R2 R1 CB REF S3 S1 S2 S2 VEL S3 S1 RDC-19200 S2 PARALLEL DATA CAN INTERFACE WITH 8 OR 16 BIT MICROPROCESSOR S2 INH ROTOR EL EM FIGURE 32. RDC-19200 RESOLVER CONNECTION - (11.8 V) REFERENCE OSCILLATOR STATOR LO HI R2 R1 CB REF S3 VEL SIN S1 S2 S4 COS RDC-19202 PARALLEL DATA CAN INTERFACE WITH 8 OR 16 BIT MICROPROCESSOR V INH ROTOR EL EM FIGURE 33. RDC-19202 DIRECT CONNECTION - (2 V) 19 SOURCES OF SOCKETS FOR THE RDC-19200 Dimensions are in inches (mm). 1.14 MAX (28.96) The following companies are sources of sockets for use with the RDC-19200 Series. Consult them for more information. Aries Electronics, Inc. P.O. Box 130 Trenton Avenue Frenchtown, NJ 08825-0130 Tel: 1-908-996-6841 http://www.arieselec.com Single In-Line Socket Strip-Line Socket Part No. 20-05511-11 Circuit Assembly Corp. 18 Thomas Street Irvine, CA 92618-2777 Tel: 714-855-7887 http://www.ca-online.com Part No. CA-20-STL-XXXX-X 1 60/40 TIN LEAD PLATED PHOSPHOR BRONZE 0.050 TYP (1.27) 40 0.018 TYP (0.46) PIN 1 DENOTED BY ORIENTATION MARK 19 EQ. SP. @0.100=1.900 TOL. NON CUM TYP (@2.54=48.26) 2.02 MAX (51.3) PIN NUMBERS FOR REF. ONLY 20 21 0.23 MAX (5.84) ORDERING INFORMATION RDC-1920X-30X 0.11 TYP (2.79) Accuracy: 1 = 8 min + 1 LSB(1) (12 LSB’s Differential Linearity) 0.010 TYP (0.25) 0.90 TYP (22.86) 0.100 TYP (2.54) 0.50 TYP (1.27) 0.160 ±0.040 (4.06 ±1.02) FIGURE 34.RDC-19200 MECHANICAL OUTLINE 2 = 4 min + 1 LSB (8 LSB’s Differential Linearity) 3 = 3 min + 1 LSB (4 LSB’s Differential Linearity) CONNECTING THE RDC-19200 4 = 2 min + 1 LSB(1) (4 LSB’s Differential Linearity) The RDC-19200 can be attached to a PC Board using hand solder or wave soldering techniques. Limit exposure to 300° C (572° F) max, for 10 seconds maximum. Do not use vapor phase soldering as this product contains SN60 or SN62 solder which melts at 180° C (356° F). Since the RDC-19200 Series converters contain a CMOS device, standard CMOS handling procedures should be followed. Configuration: 0 = 11.8 V, 2% Linearity 2 = 2 V, 2% Linearity Note 1. Available for RDC-19202 only. Note 2. Differential Linearity is x LSB in the 16th bit. The information in this data sheet is believed to be accurate; however, no responsibility is assumed by Data Device Corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. Specifications are subject to change without notice. 105 Wilbur Place, Bohemia, New York 11716-2482 For Technical Support - 1-800-DDC-5757 ext. 7389 or 7413 Headquarters - Tel: (631) 567-5600 ext. 7389 or 7413, Fax: (631) 567-7358 Southeast - Tel: (703) 450-7900, Fax: (703) 450-6610 West Coast - Tel: (714) 895-9777, Fax: (714) 895-4988 Europe - Tel: +44-(0)1635-811140, Fax: +44-(0)1635-32264 Asia/Pacific - Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689 World Wide Web - http://www.ddc-web.com K-08/99-500 ILC DATA DEVICE CORPORATION REGISTERED TO ISO 9001 FILE NO. A5976 PRINTED IN THE U.S.A. 20