ETC RM7000A?

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RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet
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RM7000A™
Data Sheet
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Microprocessor with
On-Chip Secondary Cache
Preliminary
Issue No. 5: August 2002
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2002227, Issue 5
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Legal Information
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Copyright
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Copyright 2002 PMC-Sierra, Inc. All rights reserved.
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The information in this document is proprietary and confidential to PMC-Sierra, Inc., and for its
customers’ internal use. In any event, no part of this document may be reproduced or
redistributed in any form without the express written consent of PMC-Sierra, Inc.
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PMC-2002227 (R5)
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Disclaimer
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None of the information contained in this document constitutes an express or implied warranty
by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any
such information or the fitness, or suitability for a particular purpose, merchantability,
performance, compatibility with other parts or systems, of any of the products of PMC-Sierra,
Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims
all representations and warranties of any kind regarding the contents or use of the information,
including, but not limited to, express and implied warranties of accuracy, completeness,
merchantability, fitness for a particular use, or non-infringement.
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In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or
consequential damages, including, but not limited to, lost profits, lost business or lost data
resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has
been advised of the possibility of such damage.
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Trademarks
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Patents
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PMC-Sierra and RM7000C and Fast Packet Cache are trademarks of PMC-Sierra, Inc. Other
product and company names mentioned herein may be the trademarks of their respective
owners.
Granted
The technology discussed is protected by one or more of the following patent grants.
U.S. Patent Numbers 5 953 748, 5 606 683, 5 760 620
Relevant patent applications and other patents may also exist.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2002227, Issue 5
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Contacting PMC-Sierra
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PMC-Sierra
8555 Baxter Place
Burnaby, BC
Canada V5A 4V7
20
02
Tel: +1 (604) 415-6000
Fax: +1 (604) 415-6200
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Document Information: [email protected]
Corporate Information: [email protected]
Technical Support: [email protected]
Web Site: http://www.pmc-sierra.com
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
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Revision History
Issue Date
Details of Change
5
August 2002
Updated pin AA2 from VCCInt to VSSInt.
4
March 2002
Updated Dhrystone value from 600 to 720, page 9.
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02
Modified Mode Bit 11 descriptions on page 35 and Table 16, page 38.
20
Modified SysClk values for 300 and 350 MHz CPU frequencies, Section
10.2, Clock Parameters, page 47.
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Modified (Figure 5) CP0 Register Diagram, (Figure 8) Typical Embedded
Block Diagram, (Figure 6) Kernal Mode Virtual Addressing.
Changed references from external controller to external agent, F-type to F
pipe, SysAD I/F to System I/F.
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Various formatting and editing changes.
September
2001
Updated power consumption values.
2
May 2001
Changed pin AC13 SysCmd[2] from active low to high.
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Added industrial values to Recommended Operating Instructions
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Added industrial and commercial values to Absolute Maximum Ratings
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Changed Timer Interrupt Enable/Disable information in Boot Time Mode
Stream table
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Added paragraph to Interrupt Handling section
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Clarification added to System Interface Parameters
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Additional information added to Clock Parameter table
January 2001
Applied PMC-Sierra template to existing MPD (QED) FrameMaker
document.
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In the Pinout Table, changed all references from IP to INT
Changed QED references to PMC-Sierra or MIPS.
Updated Section 7, Recommended Operating Conditions and Section 9
Power Consumption.
Added System Interface Parameter values, Section 10.3, for 350 MHz and
400 MHz CPU speeds.
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Section 1, Features, changed High-performance system interface, 133
MHz maximum frequency, multiplexed address/data to 125 MHz.
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Document Conventions
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The following conventions are used in this data sheet:
All signal, pin, and bus names described in the text, such as ExtRqst*, are in boldface
typeface.
·
All register bit and field names described in the text, such as Interrupt Mask, are in an
italic-bold typeface.
·
All instruction names, such as MFHI, are in san serif typeface.
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Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
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Table of Contents
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Legal Information........................................................................................................................... 2
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Copyright................................................................................................................................. 2
10
Disclaimer ............................................................................................................................... 2
02
Trademarks ............................................................................................................................. 2
20
Patents .................................................................................................................................... 2
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Contacting PMC-Sierra.................................................................................................................. 3
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Revision History............................................................................................................................. 4
Document Conventions ................................................................................................................. 5
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Table of Contents........................................................................................................................... 6
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List of Figures ................................................................................................................................ 9
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List of Tables................................................................................................................................ 10
Features ................................................................................................................................ 11
2
Block Diagram....................................................................................................................... 13
3
Description ............................................................................................................................ 14
4
Hardware Overview .............................................................................................................. 15
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CPU Registers............................................................................................................. 15
4.2
Superscalar Dispatch .................................................................................................. 15
4.3
Pipeline........................................................................................................................ 16
4.4
Integer Unit.................................................................................................................. 17
4.5
ALU ............................................................................................................................. 18
4.6
Integer Multiply/Divide................................................................................................. 18
4.7
Floating-Point Coprocessor......................................................................................... 19
4.8
Floating-Point Unit....................................................................................................... 19
4.9
Floating-Point General Register File ........................................................................... 20
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4.1
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4.10 System Control Coprocessor (CP0)............................................................................ 21
4.11 System Control Coprocessor Registers ...................................................................... 21
4.12 Virtual to Physical Address Mapping........................................................................... 22
4.13 Joint TLB 23
4.14 Instruction TLB ............................................................................................................ 25
4.15 Data TLB 25
4.16 Cache Memory............................................................................................................ 25
4.17 Instruction Cache ........................................................................................................ 25
4.18 Data Cache ................................................................................................................. 26
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4.19 Secondary Cache........................................................................................................ 28
4.20 Secondary Caching Protocols..................................................................................... 29
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4.21 Tertiary Cache ............................................................................................................. 29
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4.22 Cache Locking............................................................................................................. 31
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4.23 Cache Management.................................................................................................... 31
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4.24 Primary Write Buffer .................................................................................................... 32
20
4.25 System Interface ......................................................................................................... 32
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4.26 System Address/Data Bus .......................................................................................... 33
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4.27 System Command Bus ............................................................................................... 33
4.28 Handshake Signals ..................................................................................................... 34
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4.29 System Interface Operation ........................................................................................ 34
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4.30 Data Prefetch .............................................................................................................. 37
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4.31 Enhanced Write Modes ............................................................................................... 37
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4.32 External Requests ....................................................................................................... 37
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4.33 Test/Breakpoint Registers ........................................................................................... 38
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4.34 Performance Counters ................................................................................................ 38
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4.35 Interrupt Handling........................................................................................................ 40
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4.36 Standby Mode ............................................................................................................. 42
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4.37 JTAG Interface ............................................................................................................ 42
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4.38 Boot-Time Options ...................................................................................................... 43
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4.39 Boot-Time Modes ........................................................................................................ 43
Pin Descriptions .................................................................................................................... 46
6
Absolute Maximum Ratings ................................................................................................. 50
7
Recommended Operating Conditions................................................................................... 51
8
DC Electrical Characteristics ................................................................................................ 52
9
Power Consumption.............................................................................................................. 53
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10 AC Electrical Characteristics................................................................................................. 54
10.1 Capacitive Load Deration............................................................................................ 54
10.2 Clock Parameters........................................................................................................ 54
10.3 System Interface Parameters...................................................................................... 55
10.4 Boot-Time Interface Parameters ................................................................................. 55
11 Timing Diagrams ................................................................................................................... 56
11.1 Clock Timing................................................................................................................ 56
11.2 System Interface Timing.............................................................................................. 56
12 Packaging Information .......................................................................................................... 57
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13 RM7000A Pinout ................................................................................................................... 58
14 Ordering Information ............................................................................................................. 60
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Notes ........................................................................................................................................... 61
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List of Figures
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Figure 1 Block Diagram ............................................................................................................. 13
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Figure 2 CPU Registers............................................................................................................. 15
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Figure 3 Instruction Issue Paradigm.......................................................................................... 16
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Figure 4 Pipeline........................................................................................................................ 17
20
Figure 5 CP0 Registers ............................................................................................................. 22
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Figure 6 Kernel Mode Virtual Addressing (32-bit) ..................................................................... 23
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Figure 7 Tertiary Cache Hit and Miss........................................................................................ 30
Figure 8 Typical Embedded System Block Diagram................................................................. 33
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Figure 9 Processor Block Read................................................................................................. 35
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Figure 10 Processor Block Write............................................................................................... 36
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Figure 11 Multiple Outstanding Reads ...................................................................................... 36
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Figure 12 Clock Timing.............................................................................................................. 56
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Figure 13 Input Timing............................................................................................................... 56
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Figure 14 Output Timing............................................................................................................ 56
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Figure 15 304-TBGA Drawing ................................................................................................... 57
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List of Tables
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Table 1 Instruction Issue Rules ................................................................................................. 16
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Table 2 Dual Issue Instruction Classes ..................................................................................... 16
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Table 3 ALU Operations ............................................................................................................ 18
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Table 4 Integer Multiply/Divide Operations ............................................................................... 18
20
Table 5 Floating Point Latencies and Repeat Rates................................................................. 20
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Table 6 Cache Attributes ........................................................................................................... 30
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Table 7 Cache Locking Control ................................................................................................. 31
Table 8 Penalty Cycles.............................................................................................................. 32
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Table 9 Watch Control Register ................................................................................................ 38
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Table 10 Performance Counter Control .................................................................................... 39
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Table 11 Cause Register........................................................................................................... 41
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Table 12 Interrupt Control Register ........................................................................................... 41
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Table 13 IPLLO Register ........................................................................................................... 41
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Table 14 IPLHI Register ............................................................................................................ 41
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Table 15 Interrupt Vector Spacing............................................................................................. 42
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Table 16 Boot Time Mode Stream ............................................................................................ 44
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Table 17 System Interface ........................................................................................................... 46
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Table 18 Clock/Control Interface .................................................................................................. 47
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Table 19 Tertiary Cache Interface ................................................................................................ 47
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Table 20 Interrupt Interface .......................................................................................................... 48
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Table 21 JTAG Interface .............................................................................................................. 48
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Table 22 Initialization Interface ..................................................................................................... 49
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Table 23 (VCCIO = 3.15 V – 3.45 V)........................................................................................... 52
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Table 24 (VCCIO = 2.3 V – 2.7 V).............................................................................................. 52
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Features
Dual issue symmetric superscalar microprocessor with instruction prefetch optimized for
system level price/performance
o 300, 350, 400 MHz operating frequency
o >720 Dhrystone 2.1 MIPS @ 400 MHz
·
High-performance system interface
o 1000 MB per second peak throughput
o 125 MHz max. freq., multiplexed address/data
o Supports two outstanding reads with out-of-order return
o Processor clock multipliers 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9
·
Integrated primary and secondary caches
o All are 4-way set associative with 32 byte line size
o 16 KB instruction, 16 KB data, 256 KB on-chip secondary
o Per line cache locking in primaries and secondary
o Fast Packet Cache™ increases system efficiency in
networking applications
·
Integrated external cache controller (up to 8 MB)
·
High-performance floating-point unit — 800 MFLOPS maximum
o Single cycle repeat rate for common single-precision operations and some doubleprecision operations
o Single cycle repeat rate for single-precision combined multiply-add operations
o Two cycle repeat rate for double-precision multiply and double-precision combined
multiply-add operations
·
MIPS IV superset instruction set architecture
o Data PREFETCH instruction allows the processor to overlap cache miss latency and
instruction execution
o Single-cycle floating-point multiply-add
·
Integrated memory management unit
o Fully associative joint TLB (shared by I and D translations)
o 64/48 dual entries map 128/96 pages
o Variable page size
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·
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Embedded application enhancements
o Specialized DSP integer Multiply-Accumulate instructions, (MAD/MADU) and threeoperand multiply instruction (MUL)
o I&D Test/Break-point (Watch) registers for emulation & debug
o Performance counter for system and software tuning & debug
o Fourteen fully prioritized vectored interrupts — 10 external, 2 internal, 2 software
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Document No.: PMC-2002227, Issue 5
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Fully static CMOS design with dynamic power down logic
·
RM5271 pin compatible, 304 pin TBGA package, 31x31 mm
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RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet
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Block Diagram
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Figure 1 Block Diagram
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Description
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PMC-Sierra’s RM7000A™ Microprocessor is a highly integrated symmetric superscalar
microprocessor capable of issuing two instructions each processor cycle. It has two highperformance 64-bit integer units as well as a high-throughput, fully pipelined 64-bit floating
point unit.
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The RM7000A integrates 16 KB 4-way set associative instruction and data caches along with an
integrated 256 KB 4-way set associative secondary. The primary data and secondary caches are
write-back and non-blocking. An optional external tertiary cache provides high-performance
capability even in applications with very large data sets.
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The memory management unit contains a 64/48-entry fully associative TLB and a 64-bit system
interface supporting multiple outstanding reads with out-of-order return and hardware
prioritized and vectored interrupts.
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The RM7000A ideally suits high-end embedded control applications such as internetworking,
high-performance image manipulation, high-speed printing, and 3-D visualization. The
RM7000A is also applicable to the low-end workstation market where its balanced integer and
floating-point performance and direct support for a large tertiary cache (up to 8 MB) provide
outstanding price/performance.
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Hardware Overview
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CPU Registers
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4.1
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The RM7000A offers a high-level of integration targeted at high-performance embedded
applications. The key elements of the RM7000A are described throughout this section.
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The RM7000A CPU contains 32 general purpose registers (GPR), two special purpose registers
for integer multiplication and division, and a program counter; there are no condition code bits.
Figure 2 shows these processor registers. The RM7000A also contains two sets of CP0 registers.
These CP0 register sets contain both 32 and 64-bit registers. Only 29 of the 32 registers
specified in CP0, Set 0 are implemented, and only 5 of the 32 registers in CP0, Set 1 are
implemented.
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Figure 2 CPU Registers
Multiply/Divide Registers
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63
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General Purpose Registers
63
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0
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Program Counter
63
0
PC
Superscalar Dispatch
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HI
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0
The RM7000A incorporates a superscalar dispatch unit that allows it to issue up to two
instructions per cycle. For purposes of instruction issue, the RM7000A defines four classes of
instructions: integer, load/store, branches, and floating-point. There are two logical pipelines,
the function, or F, pipeline and the memory, or M, pipeline. Note however that the M pipe can
execute integer as well as memory type instructions.
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M Pipe
one of:
one of:
integer, branch, floating-point, integer mul, div
integer, load/store
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F Pipe
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Table 1 Instruction Issue Rules
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Figure 3 is a simplification of the pipeline section and illustrates the basics of the instruction
issue mechanism.
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Figure 3 Instruction Issue Paradigm
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Instruction
Cache
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Dispatch
Unit
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F Pipe IBus
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M Pipe IBus
FP
M Pipe
Integer
F Pipe
Integer
M Pipe
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FP
F Pipe
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The figure illustrates that one F pipe instruction and one M pipe instruction can be issued
concurrently but that two M pipe or two F pipe instructions cannot be issued. Table 2 specifies
more completely the instructions within each class.
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Integer
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Table 2 Dual Issue Instruction Classes
add, sub, or, xor, shift,
etc.
4.3
Load/Store
Floating-point
Branch
lw, sw, ld, sd, ldc1,
sdc1, mov, movc, fmov,
etc.
fadd, fsub, fmult,
fmadd, fdiv, fcmp, fsqrt,
etc.
beq, bne, bCzT, bCzF,
j, etc.
Pipeline
The logical length of both the F and M pipelines is five stages with state committing (result of
instruction written back into register file) in the register write or W pipe stage. The physical
length of the floating-point execution pipeline is actually seven stages but this is completely
transparent to the user.
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Figure 4 shows instruction execution within the RM7000A when instructions are issuing
simultaneously down both pipelines. As illustrated in the figure, up to ten instructions can be
executing simultaneously. This figure presents a somewhat simplistic view of the processors
operation since the out-of-order completion of loads, stores, and long latency floating-point
operations can result in there being even more instructions in process than what is shown.
1A
1A
2A
2A
1D
1D
2D
2D
1W
1W
2W
2W
1I
1I
2I
2I
1R
1R
2R
2R
1A
1A
2A
2A
1D
1D
2D
2D
1W
1W
1I
1I
2I
2I
1R
1R
2R
2R
1A
1A
2A
2A
1D
1D
1I
1I
2I
2I
1R
1R
2R
2R
1A
1A
1I
1I
2I
2I
1R
1R
I4
I5
I6
I7
I8
I9
2D
2D
1W
1W
2W
2W
2A
2A
1D
1D
2D
2D
1W
1W
2W
2W
2R
2R
1A
1A
2A
2A
1D
1D
2D
2D
1W
1W
2W
2W
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one cycle
Instruction cache access
Instruction virtual to physical address translation
Register file read, Bypass calculation, Instruction decode, Branch address calculation
Issue or slip decision, Branch decision
Data virtual address calculation
Integer add, logical, shift
Store Align
Data cache access and load align
Data virtual to physical address translation
Register file write
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1I-1R:
2I:
2R:
1A:
1A:
1A-2A:
2A:
2A-2D:
1D:
2W:
2W
2W
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2R
2R
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I3
1R
1R
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2I
2I
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1I
1I
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I0
I1
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Figure 4 Pipeline
Integer Unit
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Note that instruction dependencies, resource conflicts, and branches may result in some of the
instruction slots being occupied by NOPs.
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The RM7000A implements the MIPS IV™ Instruction Set Architecture. Additionally, the
RM7000A includes two implementation specific instructions not found in the baseline MIPS IV
ISA, but that are useful in the embedded market place. These instructions are integer multiplyaccumulate (MAD) and three-operand integer multiply (MUL).
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The RM7000A integer unit includes thirty-two general purpose 64-bit registers, the HI/LO
result registers for two-operand integer multiply/divide operations, and the program counter, or
PC. There are two separate execution units, one of which can execute F pipe instructions and
one which can execute M pipe instructions. Refer to Table 1 for the instruction issue rules.
Note that integer multiply/divide instructions, as well as their corresponding MFHi and MFLo
instructions, can only be executed in the F pipe execution unit. Within each execution unit the
operational characteristics are the same as on previous MIPS designs with single cycle ALU
operations (add, sub, logical, shift), one cycle load delay, and an autonomous multiply/divide
unit.
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Register File
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The RM7000A has thirty-two general purpose registers with register location 0 (r0) hard wired
to a zero value. These registers are used for scalar integer operations and address calculation. In
order to service the two integer execution units, the register file has four read ports and two
write ports and is fully bypassed both within and between the two execution units to minimize
operation latency in the pipeline.
02
ALU
20
4.5
tem
be
r,
The RM7000A has two complete integer ALUs each consisting of an integer adder/subtractor, a
logic unit, and a shifter. Table 3 shows the functions performed by the ALUs for each execution
unit. Each of these units is optimized to perform all operations in a single processor cycle.
F Pipe
M Pipe
Adder
add, sub
add, sub, data address add
Logic
logic, moves, zero shifts (nop)
logic, moves, zero shifts (nop)
Shifter
non-zero shift
non-zero shift, store align
rsd
ay
,1
9S
Unit
hu
Integer Multiply/Divide
nT
4.6
ep
Table 3 ALU Operations
liv
ett
io
The RM7000A has a single dedicated integer multiply/divide unit optimized for high-speed
multiply and multiply-accumulate operations. The multiply/divide unit resides in the F pipe
execution unit. Table 4 shows the performance of the multiply/divide unit on each operation.
fo
Table 4 Integer Multiply/Divide Operations
Operand Size
Latency
Repeat Rate
Stall Cycles
MULT/U, MAD/U
16 bit
4
3
0
32 bit
5
4
0
16 bit
inv
ef
uo
Opcode
4
3
2
32 bit
5
4
3
any
9
8
0
DIV, DIVD
any
36
36
0
DDIV, DDIVU
any
68
68
0
db
Do
wn
loa
de
DMULT,
DMULTU
yV
MUL
The baseline MIPS IV ISA specifies that the results of a multiply or divide operation be placed
in the Hi and Lo registers. These values can then be transferred to the general purpose register
file using the Move-from-Hi and Move-from-Lo (MFHI/MFLO) instructions.
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:03
:57
PM
In addition to the baseline MIPS IV integer multiply instructions, the RM7000A also
implements the 3-operand multiply instruction, MUL. This instruction specifies that the multiply
result go directly to the integer register file rather than the Lo register. The portion of the
multiply that would have normally gone into the Hi register is discarded. For applications where
it is known that the upper half of the multiply result is not required, using the MUL instruction
eliminates the necessity of executing an explicit MFLO instruction.
4.7
tem
be
r,
20
02
The multiply-add instructions, MAD and MADU, multiply two operands and add the resulting
product to the current contents of the Hi and Lo registers. The multiply-accumulate operation is
the core primitive of almost all signal processing algorithms. Therefore, using the RM7000A
eliminates the need for a separate DSP engine in many embedded applications.
Floating-Point Coprocessor
Floating-Point Unit
nT
4.8
hu
rsd
ay
,1
9S
ep
The RM7000A incorporates a high-performance fully pipelined floating-point co-processor that
includes a floating-point register file and autonomous execution units for multiply/add/ convert
and divide/square root. The floating-point coprocessor is a tightly coupled execution unit,
decoding and executing instructions in parallel with, and in the case of floating-point loads and
stores, in cooperation with the M pipe of the integer unit. The superscalar capabilities of the
RM7000A allow floating-point computation instructions to issue concurrently with integer
instructions.
fo
liv
ett
io
The RM7000A floating-point execution unit supports single and double precision arithmetic, as
specified in the IEEE Standard 754. The execution unit is broken into a separate divide/square
root unit and a pipelined multiply/add unit. Overlap of divide/square root and multiply/add is
supported.
inv
ef
uo
The RM7000A maintains fully precise floating-point exceptions while allowing both overlapped
and pipelined operations. Precise exceptions are extremely important in object-oriented
programming environments and highly desirable for debugging in any environment.
yV
Floating-point operations include:
add
·
subtract
·
multiply
·
divide
·
square root
·
reciprocal
·
reciprocal square root
·
conditional moves
·
conversion between fixed-point and floating-point format
Do
wn
loa
de
db
·
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2002227, Issue 5
19
conversion between floating-point formats
·
floating-point compare
:57
·
PM
RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet
Released
:03
Table 5 gives the latencies of the floating-point instructions in internal processor cycles.
Repeat Rate
single/double
fadd
4
1
4
1
fmult
4/5
1/2
fmadd
4/5
1/2
fmsub
4/5
1/2
fdiv
21/36
19/34
fsqrt
21/36
19/34
frecip
21/36
19/34
fcvt.s.w
6
3
4
fcvt.l.s
4
4
fcmp
1
inv
fcvt.l.d
yV
1
1
9S
1
1
1
1
1
1
1
1
db
fabs, fneg
hu
4
fcvt.w.d
nT
fcvt.w.s
io
4
ett
fcvt.d.l
1
liv
4
fo
fcvt.d.w
3
1
uo
4
ef
6
fcvt.d.s
ep
tem
be
1
,1
36/66
4
ay
38/68
fcvt.s.d
rsd
frsqrt
fmov, fmovc
Floating-Point General Register File
Do
wn
loa
de
4.9
r,
fsub
fcvt.s.l
02
Latency
single/double
20
Operation
10
Table 5 Floating Point Latencies and Repeat Rates
The floating-point general register file (FGR) is made up of thirty-two 64-bit registers. With the
floating-point load and store double instructions, LDC1 and SDC1, the floating-point unit can
take advantage of the 64-bit wide data cache and issue a floating-point coprocessor load or store
doubleword instruction in every cycle.
The floating-point control register file contains two registers; one for determining configuration
and revision information for the coprocessor, and one for control and status information. These
registers are primarily used for diagnostic software, exception handling, state saving and
restoring, and control of rounding modes.
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RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet
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To support superscalar operations the FGR has four read ports and two write ports and is fully
bypassed to minimize operation latency in the pipeline. Three of the read ports and one write
port are used to support the combined multiply-add instruction while the fourth read and second
write port allows for concurrent floating-point load or store and conditional move operations.
10
4.10 System Control Coprocessor (CP0)
20
02
The system control coprocessor (CP0) is responsible for the virtual memory sub-system, the
exception control system, and the diagnostics capability of the processor.
ep
tem
be
r,
For memory management support, the RM7000A CP0 is logically identical to the RM5200
Family. For interrupt exceptions and diagnostics, the RM7000A is a superset of the RM5200
Family, implementing additional features described in the following sections on Interrupts, Test/
Breakpoint registers, and Performance Counters.
ay
,1
9S
The memory management unit controls the virtual memory system page mapping. It consists of
an instruction address translation buffer (ITLB) a data address translation buffer (DTLB), a
Joint TLB (JTLB), and coprocessor registers used by the virtual memory mapping sub-system.
rsd
4.11 System Control Coprocessor Registers
liv
ett
io
nT
hu
The RM7000A incorporates all CP0 registers internally. These registers provide the path
through which the virtual memory system’s page mapping is examined and modified,
exceptions are handled, and operating modes are controlled (kernel vs. user mode, interrupts
enabled or disabled, cache features). In addition, the RM7000A includes registers to implement
a real-time cycle counting facility, to aid in cache and system diagnostics, and to assist in data
error detection.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
To support the non-blocking caches and enhanced interrupt handling capabilities of the
RM7000A, both the data and control register spaces of CP0 are supported. In the data register
space, which is accessed using the MFC0 and MTC0 instructions, the RM7000A supports the
same registers as found in previous RM7000 processors. In the control space, which is accessed
by the previously unused CTC0 and CFC0 instructions, the RM7000A supports five additional
registers. The first three of these new 32-bit registers support the enhanced interrupt handling
capabilities; Interrupt Control, Interrupt Priority Level Lo (IPLLO), and Interrupt Priority
Level Hi (IPLHI). These registers are described further in the section on interrupt handling. Two
other registers, Imprecise Error 1 and Imprecise Error 2, have been added to help diagnose bus
errors that occur on non-blocking memory references.
Figure 5 shows the CP0 registers.
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RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet
Released
Count
9*
Comp are
11*
Perf Ctr Cntrl
22*
Info
7*
Status
12*
Cause
13*
Index
0*
EPC
14*
Watch1
18*
Random
1*
Watch2
19*
XContext
20*
Wired
6*
ECC
26*
CacheErr
27*
47/63
Watch Mask
24*
Ta gHi
29*
tem
be
IntControl
20*
Imp Error 1
26*
Imp Error 2
27*
ErrorEPC
30*
9S
Ta gLo
28*
IPLHI
19*
Config
16*
ay
,1
LLAddr
17*
IPLLO
18*
ep
PRId
15*
0
r,
TLB
(entries protected
from TLBWR)
:57
Perf Counter
25*
:03
EntryLo1
3*
BadVAddr
8*
10
EntryHi
10*
Context
4*
02
EntryLo0
2*
20
PageMask
5*
PM
Figure 5 CP0 Registers
rsd
Used for memory
management
Used for exception
processing
Control Space Registers
hu
* Register number
io
nT
4.12 Virtual to Physical Address Mapping
ett
The RM7000A provides three modes of virtual addressing:
user mode
·
kernel mode
·
supervisor mode
ef
uo
fo
liv
·
yV
inv
These modes allow system software to provide a secure environment for user processes. Bits in
the CP0 Status register determine which virtual addressing mode is used. In user mode, the
RM7000A provides a single, uniform virtual address space of 256 GB (2 GB in 32-bit mode).
Do
wn
loa
de
db
When operating in the kernel mode, four distinct virtual address spaces, totaling 1024 GB
(4 GB in 32-bit mode), are simultaneously available and are differentiated by the high-order bits
of the virtual address.
The RM7000A processor also supports a supervisor mode in which the virtual address space is
256.5 GB (2.5 GB in 32-bit mode), divided into three regions based on the high-order bits of the
virtual address. Figure 6 shows the address space layout for 32-bit operations.
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RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet
Released
0xFFFFFFFF
PM
Figure 6 Kernel Mode Virtual Addressing (32-bit)
:57
Kernel virtual address space
:03
(kseg3)
Mapped, 0.5GB
0xDFFFFFFF
Supervisor virtual address space
r,
20
02
10
0xE0000000
tem
be
(ksseg)
Mapped, 0.5GB
0xBFFFFFFF
Uncached kernel physical address space
,1
9S
ep
0xC0000000
rsd
ay
(kseg1)
Unmapped, 0.5GB
0x9FFFFFFF
Cached kernel physical address space
ett
io
nT
hu
0xA0000000
liv
(kseg0)
Unmapped, 0.5GB
0x7FFFFFFF
User virtual address space
inv
ef
uo
fo
0x80000000
Mapped, 2.0GB
Do
wn
loa
de
db
0x00000000
yV
(kuseg)
When the RM7000A is configured for 64-bit addressing, the virtual address space layout is an
upward compatible extension of the 32-bit virtual address space layout.
4.13 Joint TLB
For fast virtual-to-physical address translation, the RM7000A uses a large, fully associative
TLB that maps virtual pages to their corresponding physical addresses. As indicated by its
name, the JTLB is used for both instruction and data translations. The JTLB is organized as
pairs of even/ odd entries, and maps a virtual address and address space identifier (ASID) into
the large, 64 GB physical address space. By default, the JTLB is configured as 48 pairs of
even/odd entries. The optional 64 even/odd entry configuration is set at boot time.
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RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet
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10
:03
:57
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Two mechanisms are provided to assist in controlling the amount of mapped space and the
replacement characteristics of various memory regions. First, the page size can be configured,
on a per-entry basis, to use page sizes in the range of 4 KB to 16 MB (in 4x multiples). The CP0
PageMask register is loaded with the desired page size of a mapping, and that size is stored into
the TLB, along with the virtual address, when a new entry is written. Thus, operating systems
can create special purpose maps; for example, an entire frame buffer can be memory mapped
using only one TLB entry.
9S
ep
tem
be
r,
20
The second mechanism controls the replacement algorithm when a TLB miss occurs. The
RM7000A provides a random replacement algorithm to select a TLB entry to be written with a
new mapping. However, the processor also provides a mechanism whereby a system specific
number of mappings can be locked into the TLB, thereby avoiding random replacement. This
mechanism uses the CP0 Wired register and allows the operating system to guarantee that
certain pages are always mapped for performance reasons and to avoid a deadlock condition.
This mechanism also facilitates the design of real-time systems by allowing deterministic access
to critical software.
ay
,1
The JTLB also contains information that controls the cache coherency protocol for each page.
Specifically, each page has attribute bits to determine whether the coherency algorithm is:
uncached
·
write-back
·
write-through with write-allocate
·
write-through without write-allocate
·
write-back with secondary and tertiary bypass
liv
ett
io
nT
hu
rsd
·
uo
fo
Note that both of the write-through protocols bypass both the secondary and the tertiary caches
since neither of these caches support writes of less than a complete cache line.
Do
wn
loa
de
db
yV
inv
ef
These protocols are used for both code and data on the RM7000A with data using write-back or
write-through depending on the application. The write-through modes support the same efficient
frame buffer handling as the RM5200 Family.
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RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet
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4.14 Instruction TLB
:03
:57
The RM7000A uses a 4-entry instruction TLB (ITLB). The ITLB offers the following
advantages;
Minimizes contention for the JTLB
·
Eliminates the critical path of translating through a large associative array
·
Allows instruction address and data address translations to occur in parallel
·
Saves power
tem
be
r,
20
02
10
·
9S
ep
Each ITLB entry maps a 4 KB page. The ITLB improves performance by allowing instruction
address translation to occur in parallel with data address translation. When a miss occurs on an
instruction address translation by the ITLB, the least-recently used ITLB entry is filled from the
JTLB. The operation of the ITLB is completely transparent to the user.
ay
,1
4.15 Data TLB
ett
io
nT
hu
rsd
The RM7000A uses a 4-entry data TLB (DTLB) for the same reasons cited above for the ITLB.
Each DTLB entry maps a 4 KB page. The DTLB improves performance by allowing data
address translation to occur in parallel with instruction address translation. When a miss occurs
on a data address translation, the DTLB is filled from the JTLB. The DTLB refill is pseudoLRU; the least recently used entry of the least recently used pair of entries is filled. The
operation of the DTLB is completely transparent to the user.
liv
4.16 Cache Memory
Do
wn
loa
de
db
yV
inv
ef
uo
fo
The RM7000A contains integrated primary instruction and data caches that support single cycle
access, as well as a large unified secondary cache with a three cycle miss penalty from the
primary caches. Each primary cache has a 64-bit read path and a 128-bit write path. Both caches
can be accessed simultaneously. The primary caches provide the integer and floating-point units
with an aggregate bandwidth of 6.4 GB per second at an internal clock frequency of 400 MHz.
During an instruction or data primary cache refill, the secondary cache can provide a 64-bit
datum every cycle following the initial three cycle latency for a peak bandwidth of 3.6 GB per
second. For applications requiring even higher performance, the RM7000A also has a direct
interface to a large external tertiary cache.
4.17 Instruction Cache
The RM7000A has an integrated 16 KB, four-way set associative instruction cache that is
virtually indexed and physically tagged. The effective physical index eliminates the potential for
virtual aliases in the cache.
The data array portion of the instruction cache is 64 bits wide and protected by word parity
while the tag array holds a 24-bit physical address, 14 control bits, a valid bit, and a single
parity bit.
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10
:03
:57
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By accessing 64 bits per cycle, the instruction cache is able to supply two instructions per cycle
to the superscalar dispatch unit. For signal processing, graphics, and other numerical code
sequences where a floating-point load or store and a floating-point computation instruction are
being issued together in a loop, the entire bandwidth available from the instruction cache is
consumed by instruction issue. For typical integer code mixes, where instruction dependencies
and other resource constraints restrict the level of parallelism that can be achieved, the extra
instruction cache bandwidth is used to fetch both the taken and non-taken branch paths to
minimize the overall penalty for branches.
tem
be
r,
20
A 32-byte (eight instruction) line size is used to maximize the communication efficiency
between the instruction cache and the secondary cache, tertiary cache, or memory system.
,1
9S
ep
The RM7000A supports cache locking on a per line basis. The contents of each line of the cache
can be locked by setting a bit in the Tag RAM. Locking the line prevents its contents from being
overwritten by a subsequent cache miss. Refills occur only into unlocked cache lines. This
mechanism allows the programmer to lock critical code into the cache, thereby guaranteeing
deterministic behavior for the locked code sequence.
ay
4.18 Data Cache
nT
hu
rsd
The RM7000A has an integrated 16 KB, four-way set associative data cache that is virtually
indexed and physically tagged. Line size is 32 bytes (8 words). The effective physical index
eliminates the potential for virtual aliases in the cache.
fo
liv
ett
io
The data cache is non-blocking; that is, a miss in the data cache does not necessarily stall the
processor pipeline. As long as no instruction is encountered that is dependent on the data
reference that caused the miss, the pipeline continues to advance. Once there are two cache
misses outstanding, the processor stalls if it encounters another load or store instruction.
inv
ef
uo
The data array portion of the data cache is 64 bits wide and protected by byte parity while the
tag array holds a 24-bit physical address, 3 control bits, a two-bit cache state field, and two
parity bits.
Do
wn
loa
de
db
yV
The most commonly used write policy is write-back, which means that a store to a cache line
does not immediately cause memory to be updated. This increases system performance by
reducing bus traffic and eliminating the bottleneck of waiting for each store operation to finish
before issuing a subsequent memory operation. Software can, however, select write-through on
a per-page basis when appropriate, such as for frame buffers. Cache protocols supported for the
data cache are as follows:
1. Uncached
Reads to addresses in a memory area identified as uncached do not access the cache. Writes
to such addresses are written directly to main memory without updating the cache.
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2. Write-back
20
02
10
:03
:57
Loads and instruction fetches first search the cache, reading the next memory hierarchy
level only if the desired data is not cache resident. On data store operations, the cache is
first searched to determine if the target address is cache resident. If it is resident, the cache
contents are updated and the cache line is marked for later write-back. If the cache lookup
misses, the target line is first brought into the cache, after which the write is performed as
above.
r,
3. Write-through with write allocate
rsd
4. Write-through without write allocate
ay
,1
9S
ep
tem
be
Loads and instruction fetches first search the cache, reading from memory only if the
desired data is not cache resident; write-through data is never cached in the secondary or
tertiary caches. On data store operations, the cache is first searched to determine if the target
address is cache resident. If it is resident, the primary cache contents are updated and main
memory is written, leaving the write-back bit of the cache line unchanged; no writes occur
to the secondary or tertiary caches. If the cache lookup misses, the target line is first brought
into the cache, after which the write is performed as above.
fo
liv
ett
io
nT
hu
Loads and instruction fetches first search the cache, reading from memory only if the
desired data is not cache resident; write-through data is never cached in the secondary or
tertiary caches. On data store operations, the cache is first searched to determine if the target
address is cache resident. If it is resident, the cache contents are updated and main memory
is written, leaving the write-back bit of the cache line unchanged; no writes occur to the
secondary or tertiary caches. If the cache lookup misses, only main memory is written.
uo
5. Fast Packet Cache™ (Write-back with secondary and tertiary bypass)
Do
wn
loa
de
db
yV
inv
ef
Loads and instruction fetches first search the primary cache, reading from memory only if
the desired data is not resident; the secondary and tertiary caches are not searched. On data
store operations, the primary cache is first searched to determine if the target address is
resident. If it is resident, the cache contents are updated, and the cache line marked for later
write-back. If the cache lookup misses, the target line is first brought into the cache, after
which the write is performed as above.
Associated with the data cache is the store buffer. When the RM7000A executes a Store
instruction, this single-entry buffer is written with the store data while the tag comparison is
performed. If the tag matches, then the data is written into the data cache in the next cycle that
the data cache is not accessed (the next non-load cycle). The store buffer allows the RM7000A
to execute a store every processor cycle and to perform back-to-back stores without penalty. In
the event of a store immediately followed by a load to the same address, a combined merge and
cache write occurs such that no penalty is incurred.
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4.19 Secondary Cache
02
10
:03
:57
The RM7000A has an integrated 256 KB, four-way set associative, block write-back secondary
cache. The secondary cache has a 32-byte line size, a 64-bit bus width to match the system
interface and primary cache bus widths, and is protected with doubleword parity. The secondary
cache tag array holds a 20-bit physical address, 2 control bits, a 3-bit cache state field, and two
parity bits.
ep
tem
be
r,
20
By integrating a secondary cache, the RM7000A is able to decrease the latency of a primary
cache miss without significantly increasing the number of pins and the amount of power
required by the processor. From a technology point of view, integrating a secondary cache
leverages CMOS technology by using silicon to build the structures that are most amenable to
silicon technology; building very dense, low power memory arrays rather than large power
hungry I/O buffers.
ay
,1
9S
Further benefits of an integrated secondary cache are flexibility in the cache organization and
management policies that are not practical with an external cache. Two previously mentioned
examples are the 4-way associativity and write-back cache protocol.
nT
hu
rsd
A third management policy for which integration affords flexibility is cache hierarchy
management. With multiple levels of cache, it is necessary to specify a policy for dealing with
cases where two cache lines at level n of the hierarchy could possibly be sharing an entry in
level n+1 of the hierarchy.
yV
inv
ef
uo
fo
liv
ett
io
The RM7000A allows entries to be stored in the primary caches that do not necessarily have a
corresponding entry in the secondary; the RM7000A does not force the primaries to be a subset
of the secondary. For example, if primary cache line A is being filled and a cache line already
exists in the secondary for primary cache line B at the location where primary A’s line would
reside, then that secondary entry is replaced by an entry corresponding to primary cache line A
and no action occurs in the primary for cache line B. This operation creates the aforementioned
scenario where the primary cache line, which initially had a corresponding secondary entry, no
longer has such an entry. Such a primary line is called an orphan. In general, cache lines at level
n+1 of the hierarchy are called parents of level n’s children.
Do
wn
loa
de
db
Another RM7000A cache management optimization occurs for the case of a secondary cache
line replacement where the secondary line is dirty and has a corresponding dirty line in the
primary. In this case, since it is permissible to leave the dirty line in the primary, it is not
necessary to write the secondary line back to main memory. Taking this scenario one step
further, a final optimization occurs when the aforementioned dirty primary line is replaced by
another line and must be written back. In this case it is written directly to memory, bypassing
the secondary cache.
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4.20 Secondary Caching Protocols
02
10
:03
:57
Unlike the primary data cache, the secondary cache supports only block write-back. As noted
earlier, cache lines managed with either of the write-through protocols are not placed in the
secondary cache. A new caching attribute, write-back with secondary and tertiary bypass,
allows the secondary, and tertiary caches to be bypassed entirely. When this attribute is selected,
the secondary and tertiary caches are not filled on load misses and are not written on dirty writebacks from the primary cache.
r,
20
4.21 Tertiary Cache
9S
ep
tem
be
The RM7000A has direct support for an external tertiary cache. The tertiary cache is direct
mapped and block write-through with byte parity protection for data. The RM7000A tertiary
cache operates identical to the secondary cache of the RM527x while supporting additional size
increments to support 4 MB and 8 MB caches.
ay
,1
The tertiary interface uses the SysAD bus for data and tags while providing a separate bus,
TcLine[17:0], for addresses, along with a number of tertiary cache specific control signals.
liv
ett
io
nT
hu
rsd
A tertiary read looks nearly identical to a standard processor read except that the tag chip enable
signal, TcTCE*, is asserted concurrently with ValidOut* and Release*, initiating a tag probe
and indicating to the external agent that a tertiary cache access is being performed. As a result,
the external agent monitors the tertiary hit signal, TcMatch. If a hit is indicated the external
agent aborts the memory read and refrains from acquiring control of the system interface. Along
with TcTCE*, the processor also asserts the tag data enable signal, TcTDE*, which causes the
tag RAMs to latch the SysAD address internally for use as the replacement tag if a cache miss
occurs.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
On a tertiary cache miss, a refill is accomplished with a two signal handshake between the data
output enable signal, TcDOE*, which is deasserted by the external agent, and the tag and data
write enable signal, TcCWE*, asserted by the processor. Figure 7 illustrates a tertiary cache hit
followed by a miss.
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Tertiary (Hit)
Processor
:57
Processor
System
Tertiary (Miss)
SysClock
Index
TcWord[1:0]
I0
Data1
Data2
Data3
Addr
Data0
Index
I2
I3
Data0
Data1
I0
I1
I2
I3
I0
I1
r,
I1
Data1
10
TcLine[17:0]
Data0
02
Addr
20
SysAD
:03
Master
PM
Figure 7 Tertiary Cache Hit and Miss
tem
be
TcTCE*
TcMatch
9S
ep
TcDCE*
,1
TcCWE*
rsd
ay
TcDOE*
io
nT
hu
Other capabilities of the tertiary interface include block write, tag invalidate, and tag probe. For
details of these transactions as well as detailed timing waveforms for all the tertiary cache
transactions, refer to the RM7000 Family User Manual. The tertiary cache tag can easily be
implemented with standard components such as the Motorola MCM69T618.
uo
Table 6 Cache Attributes
fo
liv
ett
The RM7000A cache attributes for the instruction, data, internal secondary, and optional
external tertiary caches are summarized in Table 6.
Primary
Instruction
Primary
Data
On-chip
Secondary
Tertiary
Cache
16KB
256KB
512K, 1M, 2M,
4M, or 8M
4-way
4-way
4-way
direct mapped
Replacement
Algorithm
cyclic
cyclic
cyclic
direct replacement
Line size
32 byte
32 byte
32 byte
32 byte
inv
ef
Attribute
16KB
Do
wn
loa
de
db
Associativity
yV
Size
Index
vAddr11..0
vAddr11..0
pAddr15..0
pAddr22..0
Tag
pAddr35..12
pAddr35..12
pAddr35..16
pAddr35..19
Write policy
n.a.
write-back, writethrough
block write-back,
bypass
block writethrough, bypass
read policy
n.a.
non-blocking (2
outstanding)
non-blocking (data
only, 2
outstanding)
non-blocking (data
only, 2
outstanding)
read order
critical word first
critical word first
critical word first
critical word first
write order
NA
sequential
sequential
sequential
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RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet
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Primary
Instruction
Primary
Data
On-chip
Secondary
Tertiary
Cache
miss restart
following:
complete line
first double (if
waiting for data)
n.a.
n.a.
Parity
per word
per byte
per doubleword
per byte
:57
:03
02
10
4.22 Cache Locking
PM
Attribute
tem
be
r,
20
The RM7000A allows critical code or data fragments to be locked into the primary and
secondary caches. The user has complete control over the locking function. For instruction and
data fragments in the primary caches, locking is accomplished by setting either or both of the
cache lock enable bits and specifying the set in the CP0 ECC register, then executing either a
load instruction for data, or a Fill_I cache operation for instructions.
ay
,1
9S
ep
Only cache lines within sets A and B of each cache can be locked. Locking within the secondary
works identically to the primaries using a separate secondary lock enable bit and the same set
selection field. As with the primaries, only sets A and B can be locked. Table 7 summarizes the
cache locking capabilities.
Set Select
Primary I
ECC[27]
ECC[28]=0A
ECC[26]
ECC[28]=0A
ett
Primary D
io
ECC[28]=1B
Activate
hu
Lock
Enable
nT
Cache
rsd
Table 7 Cache Locking Control
Fill_I
Load/Store
ECC[28]=0A
Fill_I or
ECC[28]=1B
Load/Store
fo
ECC[25]
uo
Secondary
liv
ECC[28]=1B
inv
ef
4.23 Cache Management
Do
wn
loa
de
db
yV
To improve the performance of critical data movement operations in the embedded
environment, the RM7000A significantly improves the speed of operation of certain critical
cache management operations. In particular, the speed of the Hit-Writeback-Invalidate and HitInvalidate cache operations has been improved, in some cases by an order of magnitude, over
that of other MIPS processors. For example, Table 8 compares the RM7000A with the R4000
processor.
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RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet
Released
Hit-Invalidate
R4000
Miss
0
7
Hit-Clean
3
12
Hit-Dirty
3+n
14+n
Miss
0
7
Hit
2
9
10
:03
RM7000A
02
Hit-WritebackInvalidate
Penalty
:57
Condition
20
Operation
PM
Table 8 Penalty Cycles
tem
be
r,
For the Hit-Dirty case of Hit-Writeback-Invalidate in Table 8 above, if the writeback buffer is
full from some previous cache eviction, then n is the number of cycles required to empty the
writeback buffer. If the buffer is empty then n is zero.
9S
ep
The penalty value in Table 8 is the number of processor cycles beyond the one cycle required to
issue the instruction that is required to implement the operation.
ay
,1
4.24 Primary Write Buffer
ett
io
nT
hu
rsd
Writes to secondary cache or external memory, whether cache miss write-backs or stores to
uncached or write-through addresses, use the integrated primary write buffer. The write buffer
holds up to four 64-bit address and data pairs. The entire buffer is used for a data cache writeback and allows the processor to proceed in parallel with memory update. For uncached and
write-through stores, the write buffer significantly increases performance by decoupling the
SysAD bus transfers from the instruction execution stream.
fo
liv
4.25 System Interface
inv
ef
uo
The RM7000A provides a high-performance 64-bit system interface that is compatible with the
RM5200 Family. As an enhancement to the system interface, the RM7000A allows halfintegral clock multipliers, thereby providing greater granularity when selecting pipeline and
system interface frequencies.
Do
wn
loa
de
db
yV
The system interface consists of a 64-bit Address/Data bus with 8 check bits and a 9-bit
command bus. In addition, there are ten handshake signals and ten interrupt inputs. The
interface is capable of transferring data between the processor and memory at a peak rate of
1000 MB/sec with a 125 MHz SysClock.
Figure 8 shows a typical embedded system using the RM7000A. This example shows a system
with a bank of DRAMs, an optional tertiary cache, and an interface ASIC which provides
DRAM control as well as an I/O port.
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RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet
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Address
Control
x
PCI Bus
tem
be
25
72
ep
Tertiary Cache
(optional)
,1
9S
TcLine, etc.
External
Agent
72
SysCmd
r,
SysAD Bus
20
02
64
RM7000A
x
10
8
:03
Flash/
Boot
ROM
DRAM
PM
Figure 8 Typical Embedded System Block Diagram
ay
4.26 System Address/Data Bus
nT
hu
rsd
The 64-bit System Address Data (SysAD) bus is used to transfer addresses and data between the
RM7000A and the rest of the system. It is protected with an 8-bit parity check bus,
SysADC[7:0].
uo
fo
liv
ett
io
The system interface is configurable to allow easy interfacing to memory and I/O systems of
varying frequencies. The data rate and the bus frequency at which the RM7000A transmits data
to the system interface are programmable at boot time via mode control bits. In addition, the
rate at which the processor receives data is fully controlled by the external agent. Therefore,
either a low cost interface requiring no read or write buffering, or a faster, high-performance
interface can be designed to communicate with the RM7000A.
inv
ef
4.27 System Command Bus
Do
wn
loa
de
db
yV
The RM7000A interface has a 9-bit System Command bus, SysCmd[8:0]. The command bus
indicates whether the SysAD bus carries address or data information on a per-clock basis. If the
SysAD bus carries address, the SysCmd bus indicates the transaction type (for example, a read
or write). If the SysAD bus carries data, then the SysCmd bus contains information about the
data (for example, this is the last data word transmitted, or the data contains an error). The
SysCmd bus is bidirectional to support both processor requests and external requests to the
RM7000A. Processor requests are initiated by the RM7000A and responded to by an external
agent. External requests are issued by an external agent and require the RM7000A to respond.
The RM7000A supports one- to eight-byte transfers as well as 32-byte block transfers on the
SysAD bus. In the case of a sub-doubleword transfer, the 3 low-order address bits give the byte
address of the transfer, and the SysCmd bus indicates the number of bytes being transferred.
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4.28 Handshake Signals
10
:03
:57
There are ten handshake signals on the system interface. Two of these, RdRdy* and WrRdy*,
are driven by an external agent to indicate to the RM7000A whether it can accept a new read or
write transaction. The RM7000A samples these signals before deasserting the address on read
and write requests.
tem
be
r,
20
02
ExtRqst* and Release* are used to transfer control of the SysAD and SysCmd buses from the
processor to an external agent. When an external agent requires control of the bus, it asserts
ExtRqst*. The RM7000A responds by asserting Release* to release the system interface to
slave state.
,1
9S
ep
PRqst* and PAck* are used to transfer control of the SysAD and SysCmd buses from the
external agent to the processor. These two pins have been added to the system interface to
support multiple outstanding reads and facilitate non-blocking cache operations. When the
processor needs to reacquire control of the interface, it asserts PRqst*. The external agent
responds by asserting PAck* to return control of the interface to the processor.
io
nT
hu
rsd
ay
RspSwap* is used by the external agent to indicate to the processor when it is returning
multiple data out of order. For example, when there are two outstanding reads, the external
agent asserts RspSwap* when it is going to return the data for the second read before it returns
the data for the first read. RspSwap* must be asserted by the external agent two cycles ahead of
when it presents data so that the processor has time to switch to the correct address for writes
into the tertiary cache.
fo
liv
ett
RdType is another new pin on the interface that indicates whether a read is an instruction read
or a data read. When asserted, the reference is an instruction read. When deasserted it is a data
read. RdType is only valid during valid address cycles.
yV
inv
ef
uo
ValidOut* and ValidIn* are used by the RM7000A and the external agent respectively to
indicate that there is a valid command and data on the SysAD and SysCmd buses. The
RM7000A asserts ValidOut* when it is driving these buses with a valid command and data, and
the external agent drives ValidIn* when it has control of the system interface and is driving a
valid command and data.
db
4.29 System Interface Operation
Do
wn
loa
de
To support non-blocking caches and data prefetch instructions, the RM7000A allows two
outstanding reads. An external agent may respond to read requests in whatever order it chooses
by using the response order indicator pin RspSwap*. No more than two read requests are
submitted to the external agent. Support for multiple outstanding reads can be enabled or
disabled via a boot-time mode bit. Refer to Table 16 for a complete list of mode bits.
The RM7000A can issue read and write requests to an external agent, while an external agent
can issue null and read responses to the RM7000A.
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RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet
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:57
PM
For processor reads, the RM7000A asserts ValidOut* and simultaneously drives the address
and read command on the SysAD and SysCmd buses. If the system interface has RdRdy*
asserted, then the processor tristates its drivers and releases the system interface to slave state by
asserting Release*. The external agent can then begin sending data to the RM7000A.
02
10
Figure 9 shows a processor block read request and the external agent read response for a system
with either no tertiary cache or a transaction where the tertiary is being bypassed.
r,
20
Figure 9 Processor Block Read
Addr
Data0
Data1
SysCmd
Read
NData
NData
Data2
Data3
NData
NEOD
9S
ValidOut*
ep
SysAD
tem
be
SysClock
,1
ValidIn*
rsd
ay
RdRdy*
hu
WrRdy*
nT
Release*
fo
liv
ett
io
In Figure 9 the read latency is 4 cycles (ValidOut* to ValidIn*), and the response data pattern
is DDxxDD. Figure 10 shows a processor block write where the processor was programmed
with write-back data rate boot code 2, or DDxxDDxx.
ef
uo
Figure 11 shows a typical sequence resulting in two outstanding reads both with initial tertiary
cache accesses, as explained in the following sequence.
inv
1. The processor issues a read that misses in the tertiary cache.
yV
2. The external agent takes control of the bus in preparation for returning data to the processor.
Do
wn
loa
de
db
3. The processor encounters another internal cache miss and therefore asserts PRqst* in order
to regain control of the bus.
4. The external agent pulses PAck*, returning control of the bus to the processor.
5. The processor issues a read for the second miss.
6. The second cycle also misses in the tertiary.
7. The RspSwap* pin is asserted to denote the out of order response. Not shown in the figure
is the completion of the data transfer for the second miss, or any of the data transfer for the
first miss.
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RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet
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:57
PM
8. The external agent retakes control of the bus and begins returning data (out of order) for the
second miss to the processor
10
:03
Figure 10 Processor Block Write
Data0
Data1
Data2
Data3
SysCmd
Write
NData
NData
NData
NEOD
20
Addr
r,
SysAD
02
SysClock
tem
be
ValidOut*
ValidIn*
ep
RdRdy*
9S
WrRdy*
ay
,1
Release*
hu
Tertiary(Miss)
System
nT
Processor
SysClock
Read1
System
Data0
Data1
Read2
Data02
Data12
NData
NData
7
8
inv
ValidIn*
yV
Release*
3
db
Do
wn
loa
de
TcMatch
Addr2
ef
ValidOut*
PAck*
Tertiary(Miss)
5
uo
RspSwap*
PRqst*
Data1
ett
SysCmd
Data0
liv
Addr1
Processor
2
fo
SysAD
io
Master
rsd
Figure 11 Multiple Outstanding Reads
4
1
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RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet
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4.30 Data Prefetch
20
02
10
:03
:57
The RM7000A supports the MIPS IV integer data prefetch (PREF) and floating-point data
prefetch (PREFX) instructions. These instructions are used by the compiler or by an assembly
language programmer when it is known or suspected that an upcoming data reference is going
to miss in the cache. By appropriately placing a prefetch instruction, the memory latency can be
hidden under the execution of other instructions. In cases where the execution of a prefetch
instruction would cause a memory management or address error exception the prefetch is
treated as a NOP.
tem
be
r,
The “Hint” field of the data prefetch instruction is used to specify the action taken by the
instruction. The instruction can operate normally (that is, fetching data as if for a load operation)
or it can allocate and fill a cache line with zeroes on a primary data cache miss.
9S
ep
4.31 Enhanced Write Modes
rsd
ay
,1
The RM7000A implements two enhancements to the original R4000 write mechanism: Write
Reissue and Pipeline Writes. The original R4000 allowed a write on the SysAD bus every four
SysClock cycles. Hence for a non-block write, this meant that two out of every four cycles were
wait states.
liv
ett
io
nT
hu
Pipelined write mode eliminates these two wait states by allowing the processor to drive a new
write address onto the bus immediately after the previous data cycle. This allows for higher
SysAD bus utilization. However, at high frequencies the processor may drive a subsequent write
onto the bus prior to the time the external agent deasserts WrRdy*, indicating that it can not
accept another write cycle. This can cause the cycle to be missed.
ef
uo
fo
Write reissue mode is an enhancement to pipelined write mode and allows the processor to
reissue missed write cycles. If WrRdy* is deasserted during the issue phase of a write
operation, the cycle is aborted by the processor and reissued at a later time.
yV
inv
In write reissue mode, a rate of one write every 2 bus cycles can be achieved. Pipelined writes
have the same two bus cycle write repeat rate, but can issue one additional write following the
deassertion of WrRdy*.
Do
wn
loa
de
db
4.32 External Requests
The RM7000A can respond to certain requests issued by an external agent. These requests take
one of two forms: Write requests and Null requests. An external agent executes a write request
when it wishes to update one of the processors writable resources such as the internal interrupt
register. A null request is executed when the external agent wishes the processor to reassert
ownership of the processor external interface. Once the external agent has acquired control of
the processor interface via ExtRqst*, it can execute a null request after completing an
independent transaction between itself and system memory in a system where memory is
connected directly to the SysAD bus. Normally this transaction would be a DMA read or write
from the I/O system.
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RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet
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4.33 Test/Breakpoint Registers
02
10
:03
:57
To facilitate hardware and software debugging, the RM7000A incorporates a pair of Test/Breakpoint, or Watch registers, called Watch1 and Watch2. Each Watch register can be separately
enabled to watch for a load address, a store address, or an instruction address. All address
comparisons are done on physical addresses. An associated register, Watch Mask, has also been
added so that either or both of the Watch registers can compare against an address range rather
than a specific address. The range granularity is limited to a power of two.
ep
tem
be
r,
20
When enabled, a match of either Watch register results in an exception. If the Watch is enabled
for a load or store address then the exception is the Watch exception as defined for the R4000 by
Cause exception code 23. If the Watch is enabled for instruction addresses then a newly defined
Instruction Watch exception is taken and the Cause code is 16. The Watch register which caused
the exception is indicated by Cause[25:24]. Table 9 summarizes a Watch operation.
62
61
Store
Load
Instr
[35:2]
[1:0]
0
Addr
0
nT
Mask
1
0
Mask
Watch2
Mask
Watch1
io
Note
ett
The W1 and W2 bits of the Cause register indicate which Watch register caused a particular Watch
exception.
liv
1.
[60:36]
hu
[31:2]
Watch
Mask
,1
63
ay
Watch1, 2
Bit Field/Function
rsd
Register
9S
Table 9 Watch Control Register
uo
fo
4.34 Performance Counters
Do
wn
loa
de
db
yV
inv
ef
To facilitate system tuning, the RM7000A implements a performance counter using two new
CP0 registers, PerfCount and PerfControl. The PerfCount register is a 32-bit writable counter
that causes an interrupt when bit 31 is set. The PerfControl register is a 32-bit register
containing a 5-bit field that selects one of twenty-two event types as well as a handful of bits
that control the overall counting function. Note that only one event type can be counted at a
time and that counting can occur for user code, kernel code, or both. The event types and
control bits are listed in Table 10.
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RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet
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Description
[4:0]
Event Type
:03
:57
PerfControl
Field
PM
Table 10 Performance Counter Control
10
00: Clock cycles
01: Total instructions issued
02
02: Floating-point instructions issued
20
03: Integer instructions issued
04: Load instructions issued
tem
be
r,
05: Store instructions issued
06: Dual issued pairs
07: Branch prefetches
ep
08: External Cache Misses
9S
09: Stall cycles
0A: Secondary cache misses
,1
0B: Instruction cache misses
0D: Data TLB misses
hu
0E: Instruction TLB misses
rsd
ay
0C: Data cache misses
0F: Joint TLB instruction misses
io
11: Branches taken
nT
10: Joint TLB data misses
ett
12: Branches issued
liv
13: Secondary cache writebacks
fo
14: Primary cache writebacks
uo
15: Dcache miss stall cycles (cycles where both cache miss tokens taken and a third
address is requested)
ef
16: Cache misses
inv
17: FP possible exception cycles
yV
18: Slip Cycles due to multiplier busy
19: Coprocessor 0 slip cycles
db
1A: Slip cycles doe to pending non-blocking loads
Do
wn
loa
de
1B: Write buffer full stall cycles
1C: Cache instruction stall cycles
1D: Multiplier stall cycles
1E: Stall cycles due to pending non-blocking loads - stall start of exception
[7:5]
Reserved (must be zero)
8
Count in Kernel Mode
0:
Disable
1:
Enable
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9
Count in User Mode
Disable
1:
Enable
[31:11]
Disable
Enable
02
0:
1:
10
Count Enable
20
10
0:
:57
Description
:03
PerfControl
Field
PM
RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet
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Reserved (must be zero)
tem
be
r,
The performance counter interrupt only occurs when interrupts are enabled in the Status.IE is 1,
and the Interrupt Mask bit 13 (IM13) of the coprocessor 0 interrupt control register is set.
ay
,1
9S
ep
Since the performance counter can be set up to count clock cycles, it can be used as either a
second timer, or a watchdog interrupt. A watchdog interrupt can be used as an aid in debugging
system or software “hangs.” Typically the software is setup to periodically update the count so
that no interrupt occurs. When a hang occurs the interrupt ultimately triggers, thereby breaking
free from the hang-up.
hu
rsd
4.35 Interrupt Handling
io
nT
In order to provide better real time interrupt handling, the RM7000A provides an extended set
of hardware interrupts, each of which can be separately prioritized and separately vectored.
liv
ett
In addition to the standard six external interrupt pins, the RM7000A provides four more
interrupt pins for a total of ten external interrupts.
inv
ef
uo
fo
As described above, the performance counter is also a hardware interrupt source using INT13.
Historically in the MIPS architecture, interrupt 7 (INT7) was used as the Timer Interrupt. The
RM7000A provides a separate interrupt, INT12, for this purpose, thereby releasing INT7 for
use as a pure external interrupt.
Do
wn
loa
de
db
yV
All interrupts (INT[13:0]), the Performance Counter, and the Timer, have corresponding
interrupt mask bits, IM[13:0], and interrupt pending bits, IP[13:0], in the Status, Interrupt
Control, and Cause registers. The bit assignments for the Interrupt Control and Cause registers
are shown in Table 11 and Table 12. The Status register has not changed from the RM5200
Family and is not shown.
The IV bit in the Cause register is the global enable bit for the enhanced interrupt features. If
this bit is clear then interrupt operation is compatible with the RM5200 Family.
In the Interrupt Control register, the interrupt vector spacing is controlled by the Spacing field
as described below. The Interrupt Mask field (IM[13:8]) contains the interrupt mask for
interrupts eight through thirteen. IM[15:14] are reserved for future use.
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The Timer Enable (TE) bit is used to gate the Timer Interrupt to the Cause Register. If TE is set
to 0, the Timer Interrupt is not gated to IP12. If TE is set to 1, the Timer Interrupt is gated to
IP12.
10
:03
The setting for Mode Bit 11 is used to determine if the Timer Interrupt replaces the external
interrupt (INT5*) as an input to IP7 in the Cause Register. If Mode Bit 11 is set to 0, the Timer
Interrupt is gated to IP7. If Mode Bit 11 is set to 1, external INT5* is gated to IP7.
tem
be
r,
20
02
In order to utilize both the external Interrupt (INT5*) and the internal Timer Interrupt, Mode Bit
11 must be set to 1, and TE must be set to 1. In this case, the Timer Interrupt will utilize IP12,
and INT5* will utilize IP7. Please also reference the logic diagram for interrupt signals in the
RM7000 User Manual.
ep
The Interrupt Control register uses IM13 to enable the Performance Counter Control.
Table 11 Cause Register
30
[29:28]
27
26
25
BD
0
CE
0
W2
W1
hu
rsd
31
[6:5]
0
IM[15:8]
TE
0
7
[6:2]
[1:0]
IV
IP[15:0]
0
EXC
0
[4:0]
Spacing
liv
fo
Table 13 IPLLO Register
[23:8]
io
7
ett
[15:8]
24
nT
Table 12 Interrupt Control Register
[31:16]
ay
,1
9S
Priority of the interrupts is set via two new coprocessor 0 registers called Interrupt Priority
Level Lo (IPLLO) and Interrupt Priority Level Hi (IPLHI).
[27:24]
[23:20]
[19:16]
[15:12]
[11:8]
[7:4]
[3:0]
IPL7
IPL6
IPL5
IPL4
IPL3
IPL2
IPL1
IPL0
inv
ef
uo
[31:28]
yV
Table 14 IPLHI Register
[27:24]
[23:20]
[19:16]
[15:12]
[11:8]
[7:4]
[3:0]
0
0
IPL13
IPL12
IPL11
IPL10
IPL9
IPL8
db
[31:28]
Do
wn
loa
de
In the IPLLO and IPLHI registers, each interrupt is represented by a four-bit field, thereby
allowing each interrupt to be programmed with a priority level from 0 to 15 inclusive. The
priorities can be set in any manner, including having all the priorities set exactly the same.
Priority 0 is the highest level and priority 15 the lowest. The format of the priority level
registers is shown in Table 13 and Table 14 above. The priority level registers are located in the
coprocessor 0 control register space.
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RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet
Released
02
10
:03
:57
PM
In addition to programmable priority levels, the RM7000A also permits the spacing between
interrupt vectors to be programmed. For example, the minimum spacing between two adjacent
vectors is 0x20 while the maximum is 0x200. This programmability allows the user to either set
up the vectors as jumps to the actual interrupt service routines or, if interrupt latency is not
paramount, to include the entire interrupt service routine at one vector. Table 15 illustrates the
complete set of vector spacing selections along with the coding as required in Interrupt
Control[4:0].
tem
be
r,
20
In general, the active interrupt priority, combined with the spacing setting, generates a vector
offset that is then added to the interrupt base address of 0x200 to generate the interrupt
exception offset. This offset is then added to the exception base to produce the final interrupt
vector address.
Spacing
0x0
0x000
0x1
0x020
0x2
0x040
0x4
0x080
0x8
0x100
0x200
others
reserved
io
0x10
nT
hu
rsd
ay
,1
9S
ICR[4:0]
ep
Table 15 Interrupt Vector Spacing
ett
4.36 Standby Mode
uo
fo
liv
The RM7000A provides a means to reduce the amount of power consumed by the internal core
when the CPU is not performing any useful operations. This state is known as Standby Mode.
db
yV
inv
ef
Executing the WAIT instruction enables interrupts and causes the processor to enter Standby
Mode. If the SysAD bus is currently idle when the WAIT instruction completes the W pipe
stage, the internal processor clock stops, thereby freezing the pipeline. The phase lock loop, or
PLL, internal timer/counter, and the "wake up" input pins: INT[9:0]*, NMI*, ExtReq*,
Reset*, and ColdReset* continue to operate in their normal fashion.
Do
wn
loa
de
If the SysAD bus is not idle when the WAIT instruction completes the W pipe stage, then the
WAIT is treated as a NOP. Once the processor is in Standby, any interrupt, including the
internally generated Timer Interrupt, causes the processor to exit Standby and resume operation
where it left off. The WAIT instruction is typically inserted in the idle loop of the operating
system or real time executive.
4.37 JTAG Interface
The RM7000A interface supports JTAG boundary scan in conformance with IEEE 1149.1. The
JTAG interface is useful for checking the integrity of the processor’s pin connections.
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RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet
Released
PM
4.38 Boot-Time Options
10
:03
:57
The RM7000A operating modes are initialized at power-up by the boot-time mode control
interface. The serial boot-time mode control interface operates at a very low frequency
(SysClock divided by 256), allowing the initialization information to be kept in a low cost
EPROM or system interface ASIC.
20
02
4.39 Boot-Time Modes
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
tem
be
r,
The boot-time serial mode stream is defined in Table 16. Bit 0 is presented to the processor as
the first bit in the stream following VCCOK being asserted. Bit 255 is the last bit transferred.
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Document No.: PMC-2002227, Issue 5
43
PM
RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet
Released
Table 16 Boot Time Mode Stream
Description
Mode
bit
Description
0
reserved (must be zero)
[17:16]
System configuration identifiers - software
visible in Config[21:20]
[4:1]
Write-back data rate
[19:18
Reserved: Must be zero
DDDD
1:
DDxDDx
2:
DDxxDDxx
3:
DxDxDxDx
4:
DDxxxDDxxx
5:
DDxxxxDDxxxx
6:
DxxDxxDxxDxx
7:
DDxxxxxxDDxxxxxx
8:
DxxxDxxxDxxxDxxx
Multiply by 6/x
5:
Multiply by 7/3.5
6:
Multiply by 8/x
7:
Multiply by 9/4.5
:03
nT
Multiply by 5/2.5
4:
Big endian
yV
Little endian
1:
[23:21]
Reserved: Must be zero
24
JTLB Size.
inv
ef
Specifies byte ordering. Logically ORed
with BigEndian input signal.
0:
Half integer multipliers (2.5,3.5,4.5)
io
3:
1:
ett
Multiply by 4/x
Integer multipliers (2,3,4,5,6,7,8,9)
liv
2:
Pclock to SysClock multipliers.
0:
fo
Multiply by 3/x
uo
Multiply by 2/x
1:
db
Non-Block Write Control
00: R4000 compatible non-block writes
0:
48 dual-entry
01: reserved
1:
64 dual-entry
Do
wn
loa
de
[10:9]
0:
hu
Mode bit 20 = 0 / Mode bit 20 = 1
8
10
20
r,
tem
be
ep
9S
,1
20
SysClock to Pclock Multiplier
rsd
[7:5]
reserved
ay
9-15:
02
0:
:57
Mode
bit
10: pipelined non-block writes
11: non-block write re-issue
11
12
Timer Interrupt Enable/Disable
25
On-chip secondary cache control.
0:
Internal Timer Interrupt gated to IP7
0:
Disable
1:
External INT5* gated to IP7
1:
Enable
0:
Disable
Enable two outstanding reads with out-oforder return
1:
Enable
0:
Disable
1:
Enable
Enable the external tertiary cache
26
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Document No.: PMC-2002227, Issue 5
44
Description
Mode
bit
Description
[14:13]
Output driver strength - 100% = fastest
[255:27]
Reserved: Must be zero
:57
Mode
bit
PM
RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet
Released
:03
00: 67% strength
01: 50% strength
10
10: 100% strength
02
11: 83% strength
Dual-cycle deselect (DCD)
1:
Single-cycle deselect (SCD)
r,
0:
20
External Tertiary cache RAM type:
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
tem
be
15
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RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet
Released
PM
Pin Descriptions
:57
5
10
:03
The following is a list of control, data, clock, tertiary cache, interrupt, and miscellaneous pins of
the RM7000A.
Type
Description
ExtRqst*
Input
External request
20
Pin Name
02
Table 17 System Interface
Output
Release interface
tem
be
Release*
r,
Signals that the external agent is submitting an external request.
Signals that the processor is releasing the system interface to slave
state
Input
WrRdy*
Input
Read Ready
ep
RdRdy*
9S
Signals that an external agent can now accept a processor read.
,1
Write Ready
Input
Valid Input
rsd
ValidIn*
ay
Signals that an external agent can now accept a processor write
request.
ValidOut*
nT
hu
Signals that an external agent is now driving a valid address or data
on the SysAD bus and a valid command or data identifier on the
SysCmd bus.
Valid output
io
Output
PRqst*
liv
ett
Signals that the processor is now driving a valid address or data on
the SysAD bus and a valid command or data identifier on the
SysCmd bus.
ef
uo
fo
Output
PAck*
inv
yV
Input
db
Do
wn
loa
de
RspSwap*
Input
Processor Request
When asserted this signal requests that control of the system
interface be returned to the processor. This is enabled by Mode Bit
26.
Processor Acknowledge
When asserted, in response to PRqst*, this signal indicates to the
processor that it has been granted control of the system interface.
Response Swap
RspSwap* is used by the external agent to signal the processor
when it is about to return a memory reference out of order; i.e., of two
outstanding memory references, the data for the second reference is
being returned ahead of the data for the first reference. In order that
the processor will have time to switch the address to the tertiary
cache, this signal must be asserted a minimum of two cycles prior to
the data itself being presented. Note that this signal works as a
toggle; i.e., for each cycle that it is held asserted the order of return is
reversed. By default, anytime the processor issues a second read it
is assumed that the reads will be returned in order; i.e., no action is
required if the reads are indeed returned in order. This is enabled by
Mode Bit 26.
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RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet
Released
Type
RdType
Output
Description
PM
Pin Name
Read Type
SysAD[63:0]
Input/Output
:03
:57
During the address cycle of a read request, RdType indicates
whether the read request is an instruction read or a data read.
System address/data bus
10
A 64-bit address and data bus for communication between the
processor and an external agent.
Input/Output
System address/data check bus
02
SysADC[7:0]
Input/Output
System command/data identifier bus
tem
be
SysCmd[8:0]
r,
20
An 8-bit bus containing parity check bits for the SysAD bus during
data cycles.
A 9-bit bus for command and data identifier transmission between
the processor and an external agent.
SysCmdP
System Command/Data Identifier Bus Parity
ep
Input/Output
9S
For the RM7000A, unused on input and zero on output.
SysClock
Input
Description
System clock
ay
Type
rsd
Pin Name
,1
Table 18 Clock/Control Interface
VCCP
nT
hu
Master clock input used as the system interface reference clock. All
output timings are relative to this input clock. Pipeline operation
frequency is derived by multiplying this clock up by the factor
selected during boot initialization
VCC for PLL
io
Input
VSSP
liv
ett
Quiet VccInt for the internal phase locked loop. Must be connected to
VCCInt through a filter circuit.
VSS for PLL
Quiet VSS for the internal phase locked loop. Must be connected to
VSSInt through a filter circuit.
ef
uo
fo
Input
inv
Table 19 Tertiary Cache Interface
Type
Description
Output
Tertiary Cache Block Clear
yV
Pin Name
Do
wn
loa
de
db
TcCLR*
TcCWE[1:0]*
TcDCE[1:0]*
Output
Requests that all valid bits be cleared in the Tag RAMs. Many RAMs
may not support a block clear therefore the block clear capability is
not required for the cache to operate.
Tertiary Cache Write Enable
Asserted to cause a write to the cache. Two identical signals are
provided to balance the capacitive load relative to the remaining
cache interface signals.
Output
Tertiary Cache Data RAM Chip Enable
When asserted this signal causes the data RAMs to read out their
contents. Two identical signals are provided to balance the capacitive
load relative to the remaining cache interface signals
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Document No.: PMC-2002227, Issue 5
47
Pin Name
Type
Description
TcDOE*
Input
Tertiary Cache Data RAM Output Enable
PM
RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet
Released
Output
Tertiary Cache Line Index
TcMatch
Input
Tertiary Cache Tag Match
02
TcLine[17:0]
10
:03
:57
When asserted this signal causes the data RAMs to drive data onto
their I/O pins. This signal is monitored by the processor to determine
when to drive the data RAM write enable in a tertiary cache miss refill
sequence.
TcTCE*
r,
20
This signal is asserted by the cache Tag RAMs when a match occurs
between the value on its data inputs and the contents of the
addressed location in the RAM.
Tertiary Cache Tag RAM Chip Enable
tem
be
Output
TcTDE*
9S
ep
When asserted this signal will cause either a probe or a write of the
Tag RAMs depending on the state of the Tag RAMs write enable
signal. This signal is monitored by the external agent and indicates to
it that a tertiary cache access is occurring.
Output
Tertiary Cache Tag RAM Data Enable
TcTOE*
hu
rsd
ay
,1
When asserted this signal causes the value on the data inputs of the
Tag RAM to be latched into the RAM. If a refill of the RAM is
necessary, this latched value will be written into the Tag RAM array.
Latching the Tag allows a shared address/data bus to be used
without incurring a penalty to re-present the Tag during the refill
sequence.
Tertiary Cache Tag RAM Output Enable
nT
Output
Tertiary Cache Double Word Index
ett
Input/Output
Driven by the processor on cache hits and by the external agent on
cache miss refills.
fo
liv
TcWord[1:0]
io
When asserted this signal causes the Tag RAMs to drive data onto
their I/O pins.
TcValid
Tertiary Cache Valid
This signal is driven by the processor as appropriate to make a
cache line valid or invalid. On Tag read operations the Tag RAM will
drive this signal to indicate the line state.
inv
ef
uo
Input/Output
Do
wn
loa
de
INT[9:0]*
NMI*
Type
Description
Input
Interrupt
db
Pin Name
yV
Table 20 Interrupt Interface
Ten general processor interrupts, bit-wise ORed with bits 9:0 of the
interrupt register.
Input
Non-maskable interrupt
Non-maskable interrupt, ORed with bit 15 of the interrupt register (bit
6 in R5000 compatibility mode).
Table 21 JTAG Interface
Pin Name
Type
Description
JTDI
Input
JTAG data in
JTAG serial data in.
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RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet
Released
Type
JTCK
Input
Description
PM
Pin Name
JTAG clock input
Output
JTAG data out
:03
JTDO
:57
JTAG serial clock input.
JTMS
Input
10
JTAG serial data out.
JTAG command
20
02
JTAG command signal, signals that the incoming serial data is
command data.
Type
Input
tem
be
Pin Name
BigEndian
r,
Table 22 Initialization Interface
Description
Big Endian / Little Endian Control
VCC is OK
Input
9S
VCCOK
ep
Allows the system to change the processor addressing mode without
rewriting the mode ROM.
Input
Cold Reset
hu
ColdReset*
rsd
ay
,1
When asserted, this signal indicates to the RM7000A that the VCCInt
power supply has been above the recommended value for more than
100 milliseconds and will remain stable. The assertion of VCCOK
initiates the reading of the boot-time mode control serial stream.
Reset*
nT
This signal must be asserted for a power on reset or a cold reset.
ColdReset must be de-asserted synchronously with SysClock.
Reset
io
Input
Output
ef
uo
ModeClock
fo
liv
ett
This signal must be asserted for any reset sequence. It may be
asserted synchronously or asynchronously for a cold reset, or
synchronously to initiate a warm reset. Reset must be de-asserted
synchronously with SysClock.
ModeIn
Serial boot-mode data clock output at the system clock frequency
divided by two hundred and fifty six.
Boot Mode Data In
Serial boot-mode data input.
Do
wn
loa
de
db
yV
inv
Input
Boot Mode Clock
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RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet
Released
Limits
2
Terminal Voltage with respect to VSS
VTERM
-0.5 to +3.9
Industrial
-40 to +85
TSTG
Storage Temperature
-55 to +125
IIN
DC Input Current
±20
IOUT
DC Output Current4
±20
r,
0 to +85
02
10
Operating Temperature
Commercial
20
TCASE
Unit
:57
Rating
:03
Symbol
PM
Absolute Maximum Ratings1
tem
be
6
Notes
V
°C
°C
°C
mA
mA
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2.
VIN minimum = -2.0 V for pulse width less than 15 ns. VIN should not exceed 3.9 V.
3.
When VIN < 0 V or VIN > VCCIO
4.
Not more than one output should be shorted at a time. Duration of the short should not exceed 30
seconds.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
1.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2002227, Issue 5
50
RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet
Released
Recommended Operating Conditions
PM
7
CPU Speed
Temperature
VSS
VCCInt
VCCIO
VCCP
Commercial
300 - 350 MHz
0°C to +85°C
(Case)
0V
1.65V ± 50 mV
3.3 V ± 150 mV
or
1.65 V ± 50 mV
0°C to +70°C
(Case)
0V
:03
10
2.5 V ± 200 mV
1.8V ± 50 mV
3.3 V ± 150 mV
or
02
400 MHz
:57
Grade
1.8 V ± 50 mV
0V
-40°C to +85°C
(Case)
1.65 ± 50 mV
3.3 V ± 150 mV
or
r,
350MHz
1.65 V ± 50 mV
tem
be
Industrial
20
2.5 V ± 200 mV
2.5 V ± 200 mV
ep
Notes
VCCIO should not exceed VCCInt by greater than 2.0 V during the power-up sequence.
2.
Applying a logic high state to any I/O pin before VCCInt becomes stable is not recommended.
3.
As specified in IEEE 1149.1 (JTAG), the JTMS pin must be held high during reset to avoid entering
JTAG test mode. Refer to the RM7000A Family Users Manual, Appendix E.
4.
VCCP must be connected to VCCInt through a passive filter circuit. See RM7000 Family User’s Manual
for recommended circuit.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
1.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
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RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet
Released
PM
DC Electrical Characteristics
:57
8
VOL
Maximum
Conditions
0.2 V
|IOUT|= 100 µA
0.4 V
|IOUT| = 2 mA
2.4 V
VIL
-0.3 V
0.8 V
VIH
2.0 V
VCCIO + 0.3 V
VIN = 0
±15 µA
VIN = VCCIO
ep
±15 µA
9S
IIN
r,
VOH
Maximum
0.2 V
VOH
2.1 V
0.4 V
2.0
nT
VOH
hu
VOL
rsd
VOL
ay
Minimum
,1
Table 24 (VCCIO = 2.3 V – 2.7 V)
Parameter
0.7 V
1.7
VIL
-0.3 V
VIH
1.7 V
fo
liv
VOH
ett
io
VOL
Conditions
|IOUT|= 100 µA
|IOUT| = 1 mA
|IOUT| = 2 mA
0.7 V
VCCIO + 0.3 V
±15 µA
VIN = 0
±15 µA
VIN = VCCIO
Do
wn
loa
de
db
yV
inv
ef
uo
IIN
tem
be
VOL
20
VCCIO - 0.2 V
VOH
10
Minimum
02
Parameter
:03
Table 23 (VCCIO = 3.15 V – 3.45 V)
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52
RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet
Released
standby
active
Maximum with no FPU operation
2
Maximum worst case instruction mix
:57
CPU Speed
350 MHz
1
1
:03
300 MHz
400 MHz
1
Max
Max
Max
865
865
925
2350
2750
3550
3000
4000
2500
r,
Notes
10
VCCInt
Power
(mWatts)
Conditions
02
Parameter
PM
Power Consumption
20
9
Worst case supply voltage (maximum VCCInt) with worst case temperature (maximum TCase).
2.
Dhrystone 2.1 instruction mix.
3.
I/O supply power is application dependant, but typically <20% of VCCInt.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
tem
be
1.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2002227, Issue 5
53
RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet
Released
PM
AC Electrical Characteristics
:57
10
Load Derate
CLD
Min
Max
Units
2
ns/25pF
300 MHz
Min
tSCHigh
Transition £ 5ns
3
SysClock Low
tSCLow
Transition £ 5ns
3
SysClock
Frequency
tJitterIn
SysClock
Rise Time
tSCRise
SysClock Fall
Time
tSCFall
ModeClock
Period
tModeCKP
JTAG Clock
Period
tJTAGCKP
ay
rsd
hu
nT
io
ett
liv
fo
uo
3
Max
3
ns
3
ns
33.3
125
33.1
3
125
MHz
30
8
30
8
30
ns
±150
±150
±150
ps
2
2
2
ns
2
2
2
ns
256
256
256
tSCP
4
4
tSCP
inv
Operation of the RM7000A is only guaranteed with the Phase Lock Loop Enabled.
Do
wn
loa
de
db
yV
1.
Min
Max
ef
Note:
4
Min
125
,1
Clock Jitter for
SysClock
8
400 MHz
3
33.3
tSCP
Max
Units
350 MHz
ep
SysClock
High
SysClock
Period
r,
CPU Speed
tem
be
Test
Conditions
9S
Symbol
20
10.2 Clock Parameters
Parameter
10
Symbol
02
Parameter
:03
10.1 Capacitive Load Deration
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
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RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet
Released
4
6
tDS
4
Data Hold
:57
Min
Min
Min
Max
Max
:03
400 MHz
Max
mode14..13 = 10
5,6
(fastest)
1.0
4.5
1.0
4.5
1.0
4.5
ns
mode14..13 = 01
5,6
(slowest)
1.0
5.5
1.0
5.5
1.0
5.5
ns
trise = see above table
tfall = see above table
tDH
350 MHz
Units
2.5
2.5
1.0
1.0
2.5
ns
1.0
ns
tem
be
Data Setup
300 MHz
02
tDO
Data
2,3
Output
CPU Speed
10
Test Conditions
20
Symbol
r,
1
Parameter
PM
10.3 System Interface Parameters
Notes
Timings are measured from 0.425 x VCCIO of clock to 0.425 x VCCIO of signal for 3.3 V I/O. Timings
are measured from 0.48 x VCCIO of clock to 0.48 x VCCIO of signal for 2.5 V I/O.
2.
Capacitive load for all maximum output timings is 50 pF. Minimum output timings are for theoretical no
load conditions - untested.
3.
Data Output timing applies to all signal pins whether tristate I/O or output only.
4.
Setup and Hold parameters apply to all signal pins whether tristate I/O or input only.
5.
Only mode 14:13 = 10 is tested and guaranteed.
6.
Data shown is for 3.3 V I/O. For 2.5 V I/O derate all times by 0.5 nS.
hu
rsd
ay
,1
9S
ep
1.
Mode Data Setup
tDS
Mode Data Hold
tDH
Min
io
Symbol
Max
Units
4
SysClock cycles
0
SysClock cycles
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
Parameter
nT
10.4 Boot-Time Interface Parameters
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2002227, Issue 5
55
RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet
Released
PM
Timing Diagrams
:57
11
:03
11.1 Clock Timing
02
10
Figure 12 Clock Timing
tHigh
tLow
±tJitterIn
tem
be
r,
tFall
tRise
20
SysClock
ep
11.2 System Interface Timing
9S
(SysAD, SysCmd, ValidIn*, ValidOut*, etc.)
rsd
ay
,1
Figure 13 Input Timing
nT
hu
SysClock
tDH
Data
yV
inv
fo
ef
SysClock
uo
Figure 14 Output Timing
liv
ett
io
Data
tDS
tDO
max
min
Data
Data
Do
wn
loa
de
db
Data
tDO
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2002227, Issue 5
56
RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet
Released
PM
Packaging Information
:57
12
1.27 mm
23 22 21 20 19 18 17 16 15 14 13 12 1 1 10 9 8 7 6 5 4 3 2 1
D
02
OO
A1 ball
corner
ink mark
20
1.27 mm
10
:03
Figure 15 304-TBGA Drawing
r,
E1, N
tem
be
E
e
ep
DETA IL B
e
D1, M
BOTTOM VIEW
9S
TOP VIEW
ay
A
b
,1
DETAIL A
SIDE VIEW
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
A2
hu
rsd
f
DETAIL B
aaa
nT
A1
P
ett
Body Size: 31.0 x 31.0 mm Package
io
DETAIL A
Min
Nominal
Max
Note
A
1.45
1.55
1.65
Overall Thickness
A1
0.60
0.65
0.70
Ball Height
A2
0.85
0.90
0.95
Body Thickness
D, E
30.80
31.00
31.20
Body Size
D1, E1
27.94
M,N
23 x 23
Ball Footprint
yV
inv
ef
uo
fo
liv
Symbol
M1
Ball Matrix
4
0.65
db
b
0.85
Ball Diameter
1.27
Ball Pitch
aaa
0.15
Coplanarity
bbb
0.15
Parallel
f
0.30
P
0.25
Encapsulation Height
Theta JC
0.3
Deg. C/Watt
Theta JA
13
Deg. C/Watt @ 0 cfm airflow.
Do
wn
loa
de
e
Number of Rows Deep
0.75
0.35
0.40
Seating Plan Clearance
Note:
1.
All dimensions in millimeters unless otherwise indicated.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2002227, Issue 5
57
RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet
Released
RM7000A Pinout
PM
13
Function
Pin
Function
Pin
Function
Pin
Function
A1
VCCIO
A2
VSSlO
A3
VSSlO
A4
TcLine11
A5
Do not connect
A6
VSSlO
A7
Do Not Connect
A8
:03
:57
Pin
10
VSSlO
SysAD32
A10
SysADC1
A11
Do Not Connect
A12
VSSlO
A13
VCClnt
A14
VCClnt
A15
SysAD63
A16
VSSlO
A17
SysAD61
A18
VSSlO
A19
Do Not Connect
A20
TcLine4
B1
VSSlnt
B5
TcLine10
B9
SysAD33
VSSlO
A22
VSSlO
A23
VCClO
B2
VCClO
B3
VSSlnt
B4
VSSlO
B6
SysAD35
B7
SysAD34
B8
VCClnt
B10
SysADC5
B11
SysADC0
B12
Do Not Connect
B13
SysADC7
B14
SysADC6
B15
Do Not Connect
B16
SysAD30
B17
SysAD29
B18
SysAD28
B19
TcLine5
B20
VSSlO
B21
VSSlnt
B22
VCClO
B23
VSSlO
C1
VSSlO
C2
VSSlnt
C3
VCClO
C4
VCClO
C5
C7
SysAD3
C8
SysAD2
C9
C11
SysADC4
C12
VCClnt
C15
SysAD62
C16
VCClnt
C19
Do Not Connect
C20
VCClO
C23
VSSlO
D1
TcLine13
D4
VCClO
D5
VCClO
D8
VCClnt
D9
VCClO
D10
SysAD1
D11
VCClnt
D12
VCClO
D13
VCClnt
D14
SysAD31
D15
VCClO
D16
VCClnt
D17
TcLine7
D18
VCClO
D19
VCClO
D20
VCClO
D21
E1
VCClnt
E2
E20
VCClO
F1
VsslO
G20
TcLine2
H1
H20
J1
J20
K1
TcLine9
C10
SysAD0
C13
SysADC3
C14
SysADC2
C17
SysAD60
C18
TcLine6
rsd
hu
nT
io
ett
liv
uo
tem
be
ep
9S
,1
C6
VCClnt
ay
Do Not Connect
C21
VCClO
C22
VSSlnt
D2
VSSlO
D3
VCClO
D6
VCClO
D7
TcLine8
D22
VSSlO
D23
Do Not Connect
TcLine14
E3
TcLine12
E4
VCClO
E21
Do Not Connect
E22
Do Not Connect
E23
TcLine1
F2
TcLine16
F3
TcLine15
F4
VCClO
F21
TcLine3
F22
TcLine0
F23
VSSlO
G2
SysAD4
G3
TcLine17
G4
VCClnt
G21
VCClnt
G22
SysAD59
G23
SysAD58
inv
ef
VCClO
yV
SysAD36
db
VCClO
G1
Do
wn
loa
de
F20
r,
A21
fo
20
02
A9
VSSlO
H2
SysAD37
H3
SysAD5
H4
Do Not Connect
VCClnt
H21
SysAD27
H22
SysAD26
H23
VSSlO
SysAD7
J2
SysAD6
J3
VCClnt
J4
VCClO
VCClO
J21
VCClnt
J22
SysAD57
J23
SysAD56
SysAD40
K2
SysAD8
K3
SysAD39
K4
SysAD38
K20
SysAD25
K21
SysAD24
K22
SysAD55
K23
SysAD23
L1
SysAD10
L2
SysAD41
L3
SysAD9
L4
VCClnt
L20
VCClnt
L21
SysAD54
L22
SysAD22
L23
SysAD53
M1
VSSlO
M2
SysAD11
M3
SysAD42
M4
VCClO
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2002227, Issue 5
58
RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet
Released
Pin
Function
Function
Pin
Function
M20
VCClO
M21
SysAD52
N1
SysAD43
N2
VCClnt
M22
SysAD21
M23
VSSlO
N3
SysAD12
N4
SysAD44
N20
SysAD19
N21
SysAD51
N22
VCClnt
N23
SysAD20
P1
SysAD13
P2
SysAD45
P3
SysAD14
P4
P20
VCClnt
P21
SysAD49
P22
SysAD18
P23
SysAD50
R1
SysAD46
R2
SysAD15
R3
SysAD47
R4
VCClO
R20
VCClO
R21
SysAD16
R22
SysAD48
R23
SysAD17
T4
VCClnt
T23
VSSlO
:57
:03
10
VCClnt
02
Pin
PM
Function
20
Pin
VSSlO
T2
RspSwap*
T3
PRqst*
T20
ExtRqst*
T21
VCCOK
T22
BigEndian
U1
PAck*
U2
VCClnt
U3
ModeClock
U4
JTCK
U20
VCClnt
U21
NMI*
U22
Reset*
U23
ColdReset*
V1
VSSlO
V2
JTDO
V3
JTMS
V4
VCClO
V20
VCClO
V21
INT9*
V22
VCClnt
V23
VSSlO
VCClO
W3
W21
INT6*
W22
Y1
Do Not Connect
Y2
VSSlO
Y3
Y5
VCClO
Y6
VCClO
Y9
VCClO
Y10
TcWord0
Y13
SysCmd5
Y14
VCClnt
Y17
INT2*
Y18
VCClO
Y21
VCClO
Y22
VSSlO
AA2
VSSlnt
AA3
VCClO
AA6
TcMatch
AA7
ValidOut*
AA10
Do Not Connect
AA11
Do Not Connect
AA14
SysCmd8
AA15
AA18
INT3*
AA19
AA22
VSSlnt
TcDCE0*
AB15
TcClr*
AB19
AB23
AC4
AC8
rsd
Y7
VCClO
W23
VCClnt
VCClO
Y4
VCClO
RdRdy*
Y8
Release*
Y11
VCClnt
Y12
VCClO
Y15
VCClO
Y16
VCClnt
Y19
VCClO
Y20
VCClO
Y23
INT7*
AA1
VSSlO
AA4
VCClO
AA5
Do Not Connect
AA8
SysClock
AA9
VCClnt
AA12
SysCmd0
AA13
SysCmd4
hu
nT
io
ett
liv
fo
uo
tem
be
ep
Do Not Connect
TcValid
AA17
VCClnt
AA20
VCClO
AA21
VCClO
AA23
VSSlO
AB1
VSSlO
AB2
VCClO
AB4
VSSlO
AB5
Modeln
AB6
Validin*
AB8
VCClnt
AB9
VCClnt
AB10
TcCWE0*
AB12
SysCmd1
AB13
SysCmd3
AB14
SysCmd7
AB16
TcTDE*
AB17
TcDOE*
AB18
INT0*
ef
AA16
Do Not Connect
inv
AB11
W4
INT8*
TcTCE*
yV
VccP
db
VSSlnt
AB7
Do
wn
loa
de
AB3
9S
W2
VCClO
,1
JTDI
W20
ay
W1
r,
T1
INT4*
AB20
VSSlO
AB21
VSSlnt
AB22
VCClO
VSSlnt
AC1
VCClO
AC2
VSSlnt
AC3
VSSlO
RdType
AC5
WrRdy*
AC6
VSSlO
AC7
VSSP
VSSlO
AC9
TcWord1
AC10
TcCWE1*
AC11
TcDCE1*
VSSlO
AC13
SysCmd2
AC14
SysCmd6
AC15
SysCmdP
AC16
VSSlO
AC17
TcTOE*
AC18
VSSlO
AC19
INT1*
AC20
INT5*
AC21
VSSlO
AC22
VSSlO
AC23
VCClO
AC12
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2002227, Issue 5
59
RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet
Released
:57
T
I
tem
be
T = TBGA
r,
Package Ty pe:
20
02
Temperature Grade:
(blank) = commercial
I = Industrial
:03
RM7000A -123
PM
Ordering Information
10
14
9S
ep
Device Maximum Speed
ay
,1
Device Type
A = 0.18 micron process geometry
rsd
Valid Combinations
hu
RM7000A-300T
RM7000A-350T
nT
RM7000A-400T
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
RM7000A-350TI
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2002227, Issue 5
60
RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet
Released
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
tem
be
r,
20
02
10
:03
:57
PM
Notes
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2002227, Issue 5
61