2 Megabit ROM + 256 Kilobit SRAM ROM/RAM Combo SST30VR023 Data Sheet FEATURES: • Organized as 256K x8 ROM + 32K x8 SRAM • Low Power Dissipation: – Standby 3.0V Operation: 3 µW (Typical) – Operating 3.0V Operation: 10 mW (Typical) • Fully Static Operation – No clock or refresh required • Three state Outputs • ROM/RAM combo on a monolithic chip • Equavalent ComboMemory (Flash + SRAM): product for code development and pre-production • Wide Operating Voltage Range: 2.7-3.3V • Chip Access Time – 2.7V Operation: 500 ns (Max.) • Packages Available – 32-Pin TSOP (8mm x 13.4mm) – 32-Pin TSOP (8mm x 14mm) 1 2 3 4 5 PRODUCT DESCRIPTION The SST30VR023 is a ROM/RAM combo chip consisting of 2 Mbit Read Only Memory organized as 256 KBytes and a 256 Kbit Static Random Access Memory organized as 32 KBytes. The SST30VR023 has an output enable input for precise control of the data outputs. It also has two separate chip enable inputs for selection of either ROM or RAM and for minimizing current drain during power-down mode. The device is fabricated using SST’s advanced CMOS low power processing technology. The SST30VR023 is particularly well suited for use with low voltage supplies (2.7-3.3V) such as pagers, organizers and other handheld applications. 6 7 8 9 10 FUNCTIONAL BLOCK DIAGRAM OF SST30VR023 ROM/RAM COMBO Control Circuit WE# OE# 12 WE# Address Buffer RAM Data Buffer OE# 11 RAMCS# RAMCS# ROMCS# DQ7-DQ0 ROMCS# OE# AMS-A0 13 14 ROM 15 Note: AMS = Most Significant Address 380 ILL B1.1 16 © 2000 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. ComboMemory is a trademark of 380-04 2/00 1 Silicon Storage Technology, Inc. These specifications are subject to change without notice. Powered by ICminer.com Electronic-Library Service CopyRight 2003 2 Megabit ROM + 256 Kilobit SRAM ROM/RAM Combo SST30VR023 Data Sheet A11 A9 A8 A13 A14 A17 RAMCS# VDD WE# A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Standard Pinout Top View Die Up OE# A10 ROMCS# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 380 ILL F01.0 FIGURE 1: PIN ASSIGNMENTS TABLE 1: PIN DESCRIPTION Symbol AMS-A0 WE# OE# RAMCS# ROMCS# DQ7-DQ0 VDD Vss Pin Name Address Inputs, AMS = A17 for ROM, A14 for RAM Write Enable Input Output Enable RAM Enable Input ROM Enable Input Data Inputs/Outputs Power Supply Ground 380 PGM T1.1 Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Voltage on Any Pin Relative to VSS ............................................................................................................................. -0.5V to VDD+ 0.5V Voltage on VDD Supply Relative to VSS ..................................................................................................................................... -0.5 to 4.0V Power Dissipation .............................................................................................................................................. 1.0W Storage Temperature ...................................................................................................................... -65°C to +150°C Operating Temperature ..................................................................................................................... -40°C to +85°C Soldering Temperature (10 Seconds Lead Only) ............................................................................................. 260°C OPERATING RANGE Range Ambient Temp Commercial 0 °C to +70 °C Extended -20 °C to +70 °C Industrial -40 °C to +85 °C AC CONDITIONS OF TEST Input Pulse Level ........................ 0-VDD VDD 2.7-3.3V 2.7-3.3V 2.7-3.3V Input & Output Timing Reference Levels .................. VDD/2 Input Rise/Fall Time .................... 5 ns Output Load ................................ CL = 100 pF © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 2 380-04 2/00 2 Megabit ROM + 256 Kilobit SRAM ROM/RAM Combo SST30VR023 Data Sheet TABLE 2: RECOMMENDED DC OPERATING CONDITIONS Symbol Parameter VDD VSS VIH VIL Supply Voltage Ground Input High Voltage Input Low Voltage Min Max Units 2.7 0 2.4 -0.3 3.3 0 VDD+0.5 0.3 V V V V 1 2 380 PGM T2.0 3 TABLE 3: DC OPERATING CHARACTERISTICS VDD = 3.0±0.3V Min Max Units Symbol Parameter ILI ILO Input Leakage Current Output Leakage Current IDD1 ISB ROM Operating Supply Current RAM Operating Supply Current Standby VDD Current VOL VOH Output Low Voltage Output High Voltage IDD2 -1 -1 1 1 µA µA 4.0+1.1(f) mA 2.5+1(f) mA 10 µA 0.4 V V 2.2 4 Test Conditions VIN =VSS to VDD ROMCS# = RAMCS# = VIH or OE# = VIH or WE# = VIL, VI/O = VSS to VDD ROMCS# = VIL, RAMCS# = VIH, VIN = VIH or VIL II/O = Opens ROMCS# = VIH, RAMCS# = VIL, II/O = Opens ROMCS# ³ VDD-0.2V VIN ³ VDD-0.2V or VIN £ 0.2V IOL = 1.0 mA IOH = -0.5 mA 6 7 8 380 PGM T3.1 Note: f = frequency of operation (MHz) = 1/cycle time 9 TABLE 4: CAPACITANCE (Ta = 25 °C, f=1 Mhz) Parameter Description CI/O CIN 5 Test Condition Maximum VI/O = 0V VIN = 0V 8 pF 6 pF I/O Capacitance Input Capacitance 10 380 PGM T4.0 11 12 VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT 13 VILT 380 ILL F08.0 14 AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Inputs rise and fall times (10% « 90%) are <5 ns. 15 FIGURE 2: AC INPUT/OUTPUT REFERENCE WAVEFORMS 16 © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 3 380-04 2/00 2 Megabit ROM + 256 Kilobit SRAM ROM/RAM Combo SST30VR023 Data Sheet TO TESTER TO DUT CL 380 ILL F09.0 FIGURE 3: A TEST LOAD EXAMPLE AC CHARACTERISTICS I. ROM Operation TABLE 5: READ CYCLE TIMING PARAMETERS VDD = 3.0 V ± 0.3 Symbol TRC TAA TCO TOE TLZ TOLZ THZ TOHZ TOH Parameter Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output Chip Select to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Min 500 Max Unit ns ns ns ns ns ns ns ns ns 500 500 250 25 25 30 30 15 380 PGM T5.0 TRC Address TAA TOH Data Out Data Valid Previous Data Valid 380 ILL F02.0 FIGURE 4: ROM READ CYCLE TIMING DIAGRAM (ADDRESS CONTROLLED) (ROMCS# = OE# = VIL) © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 4 380-04 2/00 2 Megabit ROM + 256 Kilobit SRAM ROM/RAM Combo SST30VR023 Data Sheet TRC 1 Address THZ(1,2) TAA 2 TCO ROMCS# TLZ(2) TOHZ(1) 3 TOE OE# TOLZ 4 TOH High-Z Data Valid Data Out 5 380 ILL F03.0 Notes: 1. THZ and TOHZ are defined as the time at which the outputs achieve the open circuit condition and are referenced to the VOH or VOL. 2. At any given temperature and voltage condition THZ(max) is less than TLZ(min) both for a given device and from device to device. 6 7 FIGURE 5: ROM READ CYCLE TIMING DIAGRAM (ROMCS# OR OE# CONTROLLED) II. SRAM Operation (ROMCS# = VIH) 8 TABLE 6: READ CYCLE TIMING PARAMETERS VDD=3.0 V ± 0.3 Symbol Parameter TRC Read Cycle Time TAA Address Access Time TCO Chip Select to Output TOE Output Enable to Valid Output TLZ Chip Select to Low-Z Output THZ Chip Disable to High-Z Output TOHZ Output Disable to High-Z Output TOH Output Hold from Address Change Min 500 Max 500 500 25 25 30 30 15 Unit ns ns ns ns ns ns ns ns 9 10 11 12 380 PGM T6.0 TABLE 7: WRITE CYCLE TIMING PARAMETERS VDD=3.0 V ± 0.3 Symbol Parameter TWC Write Cycle Time TCW Chip Select to End-of-Write TAW Address Valid to End-of-Write TAS Address Set-up Time TWP Write Pulse Width TWR Write Recovery Time TWHZ Write to Output High-Z TDW Data to Write Time Overlap TDH Data Hold from Write Time TOW End Write to Output Low-Z Min 500 365 375 0 375 0 Max 80 200 0 15 Unit ns ns ns ns ns ns ns ns ns ns 380 PGM T7.0 © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 5 380-04 2/00 13 14 15 16 2 Megabit ROM + 256 Kilobit SRAM ROM/RAM Combo SST30VR023 Data Sheet TRC Address TAA TOH Data Out Data Valid Previous Data Valid 380 ILL F04.0 FIGURE 6: SRAM READ CYCLE TIMING DIAGRAM (ADDRESS CONTROLLED) (OE# OR RAMCS# = VIL, WE# = VIH) TRC Address TAA TOHZ(1) TOE OE# THZ (1,2) TCO RAMCS# TLZ(2) TOH High-Z Data Valid Data Out Notes: 1. THZ and TOHZ are defined as the time at which the outputs achieve the open circuit condition and are referenced to the VOH or VOL. 2. At any given temperature and voltage condition THZ(max) is less than TLZ(min) both for a given device and from device to device. 3. WE# is high for Read cycle. 4. Address valid prior to coincidence with RAMCS# transition low. 380 ILL F05.0 FIGURE 7: SRAM READ CYCLE TIMING DIAGRAM (OE# OR RAMCS# CONTROLLED) © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 6 380-04 2/00 2 Megabit ROM + 256 Kilobit SRAM ROM/RAM Combo SST30VR023 Data Sheet TWC 1 Address 2 TWR(4) TAW TCW(2) OE# 3 RAMCS# 4 TAS(3) TWP(1) TOH 5 WE# TDH TDW High-Z 6 Data Valid Data In TWHZ(5) TOW High-Z (6) Data Out (7) 7 (8) 8 380 ILL F06.0 Notes: 1. A write occurs during the overlap (TWP) of a low RAMCS# and low WE#. A write begins at the latest transition among RAMCS# going low and WE# going low: A write end at the earliest transition among RAMCS# going high and WE# going high, TWP is measured from the beginning of write to the end of write. 2. TCW is measured from the later of RAMCS# going low to the end of write. 3. TAS is measured from the address valid to the beginning of write. 4. TWR is measured from the end of write to the address change. 5. If RAMCS#, WE# are in the read mode during this period, the I/O pins are in the outputs Low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 6. If RAMCS# goes low simultaneously with WE# going low or after WE# going low, the outputs remain high impedance state. 7. DOUT is the same phase of the latest written data in this write cycle. 8. DOUT is the read data of new address 9. ROMCS# = VIH 9 10 11 12 FIGURE 8: SRAM WRITE CYCLE TIMING DIAGRAM (OE# CLOCK) 13 14 15 16 © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 7 380-04 2/00 2 Megabit ROM + 256 Kilobit SRAM ROM/RAM Combo SST30VR023 Data Sheet TWC Address TAW TWR(4) TCW(2) RAMCS# TAS(3) TWP(1) TOH WE# TDH TDW High-Z Data Valid Data In TWHZ(5) TOW High-Z (6) (7) (8) Data Out 380 ILL F07.0 Notes: 1. A write occurs during the overlap (TWP) of a low RAMCS# and low WE#. A write begins at the latest transition among RAMCS# going low and WE# going low: A write end at the earliest transition among RAMCS# going high and WE# going high, TWP is measured from the beginning of write to the end of write. 2. TCW is measured from the later of RAMCS# going low to the end of write. 3. TAS is measured from the address valid to the beginning of write. 4. TWR is measured from the end of write to the address change. 5. If RAMCS#, WE# are in the read mode during this period, the I/O pins are in the outputs Low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 6. If RAMCS# goes low simultaneously with WE# going low or after WE# going low, the outputs remain high impedance state. 7. DOUT is the same phase of the latest written data in this write cycle. 8. DOUT is the read data of new address 9. ROMCS# = VIH FIGURE 9: SRAM WRITE CYCLE TIMING DIAGRAM (OE# FIXED) © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 8 380-04 2/00 2 Megabit ROM + 256 Kilobit SRAM ROM/RAM Combo SST30VR023 Data Sheet TABLE 8: FUNCTIONAL DESCRIPTION/TRUTH TABLE Address Inputs ROMCS# RAMCS# WE# OE# DQ7-DQ0 X H H X X Z Standby A17-A0 L H X H Z Output Floating A17-A0 L H X L Dout ROM Read Only A14-A0 are valid * H L H H Z Output Floating Only A14-A0 are valid * H L H L Dout RAM Read Only A14-A0 are valid * H L L H Din RAM Write * A17-A15 must be fixed to “L” or “H” 380 PGM T9.2 Note: (1) It is forbidden that ROMCS# pin and RAMCS# pin will be “0” at the same time. (2) X means Don’t Care. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 9 380-04 2/00 2 Megabit ROM + 256 Kilobit SRAM ROM/RAM Combo SST30VR023 Data Sheet Device SST30VR023 Speed Suffix1 Suffix2 - XXX X XX - RXXXX C-Spec Number Package Modifier H = 32 pins Numeric = Die modifier Package Type W = TSOP (die up) 8mm x 14mm K = TSOP (die up) 8mm x 13.4mm U = Die only Temperature Range C = Commercial = 0° to 70°C E = Extended = -20° to 70°C I = Industrial = -40° to 85°C Read Access Speed 500 = 500 ns Density 023 = 2 Mbit ROM + 256 Kbit SRAM Voltage Range V = 2.7-3.3V Device Family 30 = ROM/RAM Combo SST30VR023 Valid combinations SST30VR023-500-C-WH SST30VR023-500-C-KH SST30VR023-500-E-WH SST30VR023-500-E-KH SST30VR023-500-I-WH SST30VR023-500-I-KH SST30VR023-500-C-U1 Example: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 10 380-04 2/00 2 Megabit ROM + 256 Kilobit SRAM ROM/RAM Combo SST30VR023 Data Sheet PACKAGING DIAGRAMS PIN # 1 1 .91 1.05 ALTERNATE INDICATOR .50 BSC .16 .27 7.90 8.30 † 2 3 4 5 0.05 0.20 11.70 11.90 6 0.70 0.30 Note: 7 13.20 13.60 32.TSOP-KH-ILL.4 8 1. Complies with JEDEC publication 95 MO-142 BA dimensions (except as noted), although some dimensions may be more stringent. † = JEDEC max is 8.1; SST max is less stringent 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±.05) mm. 9 32-PIN THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 13.4MM SST PACKAGE CODE: KH 10 11 12 13 14 15 16 © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 11 380-04 2/00 2 Megabit ROM + 256 Kilobit SRAM ROM/RAM Combo SST30VR023 Data Sheet 1.05 0.95 PIN # 1 IDENTIFIER .50 BSC 8.10 7.90 0.15 0.05 12.50 12.30 0.70 0.50 Note: .270 .170 14.20 13.80 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±.05) mm. 32.TSOP-WH-ILL.3 32-PIN THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM SST PACKAGE CODE: WH Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 www.SuperFlash.com or www.ssti.com • Literature FaxBack 888-221-1178, International 732-544-2873 © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 12 380-04 2/00