4 Megabit ROM + 256 Kilobit SRAM ROM/RAM Combo SST30VR043 Data Sheet FEATURES: • Organized as 512K x8 ROM + 32K x8 SRAM • ROM/RAM combo on a monolithic chip • Wide Operating Voltage Range: 2.7-3.3V • Chip Access Time – 2.7V Operation: 500 ns (Max.) • Low Power Dissipation: – Standby 3.0V Operation: 1.0µW (Typical) – Operating 3.0V Operation: 3.0 mW (Typical) • Fully Static Operation – No clock or refresh required • Three state Outputs • Packages Available – 32-Pin TSOP (8mm x 20mm) – 32-Pin STSOP (8mm x13.4mm) 1 2 3 4 5 PRODUCT DESCRIPTION The SST30VR043 is a ROM/RAM combo chip consisting of 4 Mbit Read Only Memory organized as 512 KBytes and a 256 Kbit Static Random Access Memory organized as 32 KBytes. Output Enable Input (OE#) is pin-shared with RAMCS# (RAM Enable Input) signal in order to maintain the standard 32 pin TSOP package. The device is fabricated using SST’s advanced CMOS low power process technology. The SST30VR043 has an output enable input for precise control of the data outputs. It also has two (2) separate chip enable inputs for selection of either RAM or ROM and minimize current drain during power-down mode. The SST30VR043 is particularly well suited for use in low voltage (2.7-3.3V) operation such as pagers, organizers and other handheld applications. 6 7 8 9 10 FUNCTIONAL BLOCK DIAGRAM OF SST30VR043 ROM/RAM COMBO 11 WE# OEB WEB 12 A15-A18 A0-A14 Address Buffer 256K RAM Data Buffer ROMCS# OE#/RAMCS# Control Circuit RAMCS# DQ0-DQ7 ROMCS# 13 14 OEB 4M ROM 15 378 ILL B1.2 16 © 2000 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. ComboMemory is a trademark of 378-03 2/00 1 Silicon Storage Technology, Inc. These specifications are subject to change without notice. Powered by ICminer.com Electronic-Library Service CopyRight 2003 4 Megabit ROM + 256 Kilobit SRAM ROM/RAM Combo SST30VR043 Data Sheet A11 A9 A8 A13 A14 A17 WE# VDD A18 A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Standard Pinout Top View Die Up 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE#/RAMCS# A10 ROMCS# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 378 ILL F01.2 FIGURE 1: PIN ASSIGNMENTS TABLE 1: PIN DESCRIPTION Symbol A0-A18 WE# OE#/RAMCS# ROMCS# DQ0-DQ7 VDD Vss Pin Name Address Inputs Write Enable Input Output Enable/RAM Enable Input ROM Enable Input Data Inputs/Outputs Power Supply Ground 378 PGM T1.1 Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Voltage on Any Pin Relative to VSS ............................................................................................................................. -0.5V to VDD+ 0.5V Voltage on VDD Supply Relative to VSS ..................................................................................................................................... -0.5 to 4.0V Power Dissipation .............................................................................................................................................. 1.0W Storage Temperature ...................................................................................................................... -65°C to +150°C Operating Temperature ..................................................................................................................... -20°C to +70°C Soldering Temperature (10 Seconds Lead Only) ............................................................................................. 260°C OPERATING RANGE Range Ambient Temp Commercial 0 °C to +70 °C Extended -20 °C to +70 °C Industrial -40 °C to +85 °C AC CONDITIONS OF TEST Input Pulse Level ........................ 0-3V VDD 2.7-3.3V 2.7-3.3V 2.7-3.3V Input & Output Timing Reference Levels .................. 1.5V Input Rise/Fall Time .................... 5 ns Output Load ................................ CL = 100 pF © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 2 378-03 2/00 4 Megabit ROM + 256 Kilobit SRAM ROM/RAM Combo SST30VR043 Data Sheet TABLE 2: RECOMMENDED DC OPERATING CONDITIONS Symbol Parameter VDD VSS VIH VIL Supply Voltage Ground Input High Voltage Input Low Voltage Min Max Units 2.7 0 2.4 -0.3 3.3 0 VDD+0.5 0.3 V V V V 1 2 378 PGM T2.0 3 TABLE 3: DC OPERATING CHARACTERISTICS VDD = 3.0±0.3V Min Max Units Symbol Parameter ILI ILO Input Leakage Current Output Leakage Current IDD1 ISB ROM Operating Supply Current RAM Operating Supply Current Standby VDD Current VOL VOH Output Low Voltage Output High Voltage IDD2 -1 -1 1 1 µA µA 4.0+1.1(f) mA 2.5+1(f) mA 10 µA 0.4 V V 2.2 4 Test Conditions VIN =VSS to VDD ROMCS# = RAMCS# = VIH or OE# = VIH or WE# = VIL, VI/O = VSS to VDD ROMCS# = VIL, RAMCS# = VIH, VIN = VIH or VIL II/O = Opens ROMCS# = VIH, RAMCS# = VIL, II/O = Opens ROMCS# ³ VDD-0.2V, RAMCS# ³ VDD-0.2V VIN ³ VDD-0.2V or VIN £ 0.2V IOL = 1.0 mA IOH = -0.5 mA 6 7 8 378 PGM T3.2 Note: f = 1/cycle time (MHz) 9 TABLE 4: CAPACITANCE (Ta = 25 °C, f=1 Mhz) Parameter Description CI/O CIN 5 Test Condition Maximum VI/O = 0V VIN = 0V 8 pF 6 pF I/O Capacitance Input Capacitance 10 378 PGM T4.0 11 12 VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT 13 VILT 378 ILL F07.0 14 AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Inputs rise and fall times (10% « 90%) are <5 ns. Note: VHT–VHIGH Test VLT–VLOW Test VIHT–VINPUT HIGH Test VILT–VINPUT LOW Test FIGURE 2: AC INPUT/OUTPUT REFERENCE WAVEFORMS © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 3 378-03 2/00 15 16 4 Megabit ROM + 256 Kilobit SRAM ROM/RAM Combo SST30VR043 Data Sheet TO TESTER TO DUT CL 378 ILL F08.0 FIGURE 3: A TEST LOAD EXAMPLE AC CHARACTERISTICS I. ROM Operation TABLE 5: READ CYCLE TIMING PARAMETERS Symbol TRC TAA TCO TOE TLZ TOLZ THZ TOHZ TOH VDD=3.0 V ± 0.3 Min Max 500 500 500 250 10 10 40 40 15 Parameter Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output Chip Select to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Unit ns ns ns ns ns ns ns ns ns 378 PGM T5.2 TRC Address TAA TOH Data Out Data Valid Previous Data Valid 378 ILL F02.0 FIGURE 4: ROM READ CYCLE TIMING DIAGRAM (ADDRESS CONTROLLED) (ROMCS# = OE# = VIL) © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 4 378-03 2/00 4 Megabit ROM + 256 Kilobit SRAM ROM/RAM Combo SST30VR043 Data Sheet TRC 1 Address THZ(1,2) TAA 2 TCO ROMCS# TLZ(2) 3 TOHZ(1) TOE OE# 4 TOLZ TOH High-Z Data Valid Data Out 5 378 ILL F03.1 Notes: 1. THZ and TOHZ are defined as the time at which the outputs achieve the open circuit condition and are referenced to the VOH or VOL. 2. At any given temperature and voltage condition THZ(max) is less than TLZ(min) both for a given device and from device to device. 6 7 FIGURE 5: ROM READ CYCLE TIMING DIAGRAM (ROMCS# & OE# CONTROLLED) II. SRAM Operation (ROMCS# = VIH) 8 TABLE 6: READ CYCLE TIMING PARAMETERS Symbol TRC TAA TCO TLZ THZ TOH Parameter Read Cycle Time Address Access Time Chip Select to Output Chip Select to Low-Z Output Chip Disable to High-Z Output Output Hold from Address Change VDD=3.0 V ± 0.3 Min Max 500 500 500 10 40 15 9 Unit ns ns ns ns ns ns 10 11 378 PGM T6.2 12 Unit ns ns ns ns ns ns ns ns ns ns 13 TABLE 7: WRITE CYCLE TIMING PARAMETERS Symbol TWC TCW TAW TAS TWP TWR TWHZ TDW TDH TOW Parameter Write Cycle Time Chip Select to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z VDD=3.0 V ± 0.3 Min Max 500 365 400 0 400 0 80 200 0 10 14 15 16 378 PGM T7.1 © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 5 378-03 2/00 4 Megabit ROM + 256 Kilobit SRAM ROM/RAM Combo SST30VR043 Data Sheet TRC Address TAA TOH Data Out Data Valid Previous Data Valid 378 ILL F04.0 FIGURE 6: SRAM READ CYCLE TIMING DIAGRAM (ADDRESS CONTROLLED) (OE#/RAMCS# = VIL, WE# = VIH) TRC Address THZ(1,2) TAA TCO OE#/RAMCS# TLZ(2) TOH High-Z Data Valid Data Out Notes: 1. THZ and TOHZ are defined as the time at which the outputs achieve the open circuit condition and are referenced to the VOH or VOL. 2. At any given temperature and voltage condition THZ(max) is less than TLZ(min) both for a given device and from device to device. 3. WE# is high for Read cycle. 378 ILL F05.2 FIGURE 7: SRAM READ CYCLE TIMING DIAGRAM (OE#/RAMCS# CONTROLLED) © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 6 378-03 2/00 4 Megabit ROM + 256 Kilobit SRAM ROM/RAM Combo SST30VR043 Data Sheet TWC 1 Address 2 TWR(4) TAW TCW(2) OE#/RAMCS# 3 TAS(3) TWP(1) TOH 4 WE# TDH TDW High-Z 5 Data Valid Data In TWHZ(5) TOW High-Z (6) Data Out (7) 6 (8) 7 378 ILL F06.2 Notes: 1. A write occurs during the overlap (TWP) of a low RAMCS# and low WE#. A write begins at the latest transition among RAMCS# going low and WE# going low: A write end at the earliest transition among RAMCS# going high and WE# going high, TWP is measured from the beginning of write to the end of write. 2. TCW is measured from the later of RAMCS# going low to the end of write. 3. TAS is measured from the address valid to the beginning of write. 4. TWR is measured from the end of write to the address change. 5. If RAMCS#, WE# are in the read mode during this period, the I/O pins are in the outputs Low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 6. If RAMCS# goes low simultaneously with WE# going low or after WE# going low, the outputs remain high impedance state. 7. DOUT is the same phase of the latest written data in this write cycle. 8. DOUT is the read data of new address 9. ROMCS# = VIH 8 9 10 11 FIGURE 8: SRAM WRITE CYCLE TIMING DIAGRAM 12 13 14 15 16 © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 7 378-03 2/00 4 Megabit ROM + 256 Kilobit SRAM ROM/RAM Combo SST30VR043 Data Sheet TABLE 8: FUNCTIONAL DESCRIPTION/TRUTH TABLE A0=A18 ROMCS# OE#/RAMCS# (PIN 32) WE# DQ0-DQ7 X H H X Z Standby A0-A18 L OE# (H) X Z Output Floating A0-A18 L OE# (L) X Dout ROM Read Only A0-A14 are valid * H RAMCS# (L) H Dout RAM Read Only A0-A14 are valid * H RAMCS# (L) L Din RAM Write * A15-A18 must be fixed to “L” or “H” 378 PGM T9.1 Note: (1) OE# & RAMCS# are pin-shared (2) X means Don’t Care. © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 8 378-03 2/00 4 Megabit ROM + 256 Kilobit SRAM ROM/RAM Combo SST30VR043 Data Sheet Device SST30VR043 Speed Suffix1 Suffix2 - XXX X XX - RXXXX 1 C-Spec Number 2 Package Modifier H = 32 leads Numeric = Die modifier 3 Package Type K = TSOP (die up) 8mm x 13.4mm E = TSOP (die up) 8mm x 20mm U = Die only 4 Temperature Range C = Commercial = 0° to 70°C E = Extended = -20° to 70°C I = Industrial = -40° to 85°C 5 6 Read Access Speed 500 = 500 ns Density 043 = 4 Mbit ROM + 256 Kbit SRAM 7 Voltage Range V = 2.7-3.3V 8 Device Family 30 = ROM/RAM Combo 9 10 SST30VR043 Valid combinations SST30VR043-500-C-KH SST30VR043-500-E-KH SST30VR043-500-I-KH SST30VR043-500-C-EH SST30VR043-500-E-EH SST30VR043-500-I-EH SST30VR043-500-C-U1 11 12 Example: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. 13 14 15 16 © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 9 378-03 2/00 4 Megabit ROM + 256 Kilobit SRAM ROM/RAM Combo SST30VR043 Data Sheet PACKAGING DIAGRAMS PIN # 1 .91 1.05 ALTERNATE INDICATOR .50 BSC .16 .27 7.90 8.30 † 0.05 0.20 11.70 11.90 0.70 0.30 Note: 13.20 13.60 32.TSOP-KH-ILL.4 1. Complies with JEDEC publication 95 MO-142 BA dimensions (except as noted), although some dimensions may be more stringent. † = JEDEC max is 8.1; SST max is less stringent 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±.05) mm. 32-PIN THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 13.4MM SST PACKAGE CODE: KH © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 10 378-03 2/00 4 Megabit ROM + 256 Kilobit SRAM ROM/RAM Combo SST30VR043 Data Sheet 1.05 0.95 PIN # 1 IDENTIFIER 1 .50 BSC 2 8.10 7.90 .27 .17 3 4 0.15 0.05 18.50 18.30 5 6 0.70 0.50 Note: 20.20 19.80 7 1. Complies with JEDEC publication 95 MO-142 BD dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±.05) mm. 8 32.TSOP-EH-ILL.3 32-PIN THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 20MM SST PACKAGE CODE: EH 9 10 11 12 13 14 15 16 © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 11 378-03 2/00 4 Megabit ROM + 256 Kilobit SRAM ROM/RAM Combo SST30VR043 Data Sheet Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 www.SuperFlash.com or www.ssti.com • Literature FaxBack 888-221-1178, International 732-544-2873 © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 12 378-03 2/00