SuperLite™ 2.5V/3.3V 2.5GHz DIFFERENTIAL 2-CHANNEL PRECISION CML DELAY LINE Micrel SuperLite™ SY55856U SY55856U FINAL FEATURES ■ Guaranteed AC parameters over temp and voltage • > 2.5GHz FMAX • < 384ps prop delay • < 120ps Tr/Tf ■ Delay either clock or data ■ 50ps increments ■ ± 350ps total delay ■ Delay either clock or data ■ Source terminated CML outputs ■ Full differential I/O ■ Wide supply voltage spectrum: 2.3V to 3.6V ■ Available in a tiny 32-pin EPAD-TQFP package SuperLite™ DESCRIPTION The SY55856U is a 2.5GHz, two-channel, fully differential CML (Current Mode Logic) delay line. The device is optimized to adjust the relative delay between two channels, such as clock and data, in 50ps increments. Both inputs may be adjusted in either direction in 7 increments of 50ps, for a total adjustment range of ±350ps. In addition, the clock input maybe inverted through the CINV control pin. The SY55856U inputs are designed to accept singleended or differential CML signals. The differential CML outputs are optimized for 50Ω loads (50Ω source terminated), thus only requires a single 100Ω resistor across the output pair. Output rise and fall time is an extremely fast 110ps(max) and the differential swing is 400mV. The maximum throughput of the SY55856U is guaranteed to exceed 2.5GHz (1.25Gbps). APPLICATIONS ■ ■ ■ ■ ■ ■ Data communications systems Telecom systems High-speed backplanes Signal de-skewing Pulse alignment Digitally controlled delay lines PIN NAMES VCC VCC S0 S1 Pin S2 DELAY_SEL VCC VCC PIN CONFIGURATION Function CLK_IN, /CLK_IN Differential Clock Input (CML compatible) 1 24 /DATA_OUT CLK_OUT, /CLK_OUT Differential Clock Output (CML) /DATA_IN 32 31 30 29 28 27 26 25 GND 2 23 GND CINV Clock Inversion Control (CML compatible) DATA_IN 3 22 DATA_OUT 4 21 GND DATA_IN, /DATA_IN Differential Data Input (CML compatible) GND GND 5 20 GND 6 19 CLK_OUT DATA_OUT, /DATA_OUT Differential Data Output (CML) CLK_IN GND 7 18 GND /CLK_IN Control Level Select (CML compatible) 17 /CLK_OUT LVL 8 DELAY_SEL Delay Path Control (CML compatible) S2, S1, S0 Delay Selection Control (LSB=S0) GND Ground VCC VCC Top View EPAD-TQFP H32-1 VCC VCC LVL NC NC CINV 10 11 12 13 14 15 16 VCC VCC 9 SuperLite is a trademarks of Micrel, Inc. Rev.: B 1 Amendment: /0 Issue Date: March 2003 SuperLite™ SY55856U Micrel BLOCK DIAGRAM A0 A1 A3 A2 A4 A5 A6 VCC DATA_IN /DATA_IN INPUT BUFFER A7 S1 S0 DATA_OUT /DATA_OUT S2 S2 S1 5k S0 LVL 5k VREF = 1.3V DEL_SEL A0 A1 A3 A2 A4 A5 A6 CLK_IN /CLK_IN CLK_OUT /CLK_OUT A7 S1 S2 S0 INPUT BUFFER CINV GND PIN DESCRIPTIONS CLK_IN, /CLK_IN – CML Input (Differential) This is one of the differential CML inputs, the clock in signal. A delayed version of this input appears at CLK_OUT, /CLK_OUT. CINV – VT Input (Single Ended) This is the clock inversion select signal. This input optionally inverts the CLK_IN, /CLK_IN signal which results in an inverted CLK_OUT, /CLK_OUT. A voltage below the VT threshold results in no inversion. A voltage above the threshold value results in an inversion from the clock input to the clock output. Refer to the “VT input” section below. CLK_OUT, /CLK_OUT – CML Output (Differential) This is one of the CML outputs, the clock output. It is a delayed, copy of CLK_IN, /CLK_IN. DATA_IN, /DATA_IN – CML Input (Differential) This is one of the CML inputs, the data in signal. A delayed version of this signal appears at DATA_OUT, /DATA_OUT. DATA_OUT, /DATA_OUT – CML Output (Differential) This is one of the CML outputs, the data output. It is a delayed version of CLK_IN, /CLK_IN. LVL – Analog Input This input determines what level differentiates logic high from logic low. This input affects the behavior of the CINV, S0, S1 and S2 inputs. Please refer to the “VT input“ section below for more details. For the control interface, see Figure 3b. For TTL control interface, see Figure 3b. DELAY_SEL – VT Input (Single Ended) CML compatible control logic. This is the delay path control input. Logic high delays the clock signal with respect to the data signal. A logic low delays the data signal with respect to the clock signal. Inputs S2, S1 and S0 control amount of delay. S0, S1, S2 – VT Input (Single Ended) CML compatible control logic. This is the delay selection control input. These three bits define how much relative delay will occur between the data and clock signals, as per the truth table shown in Table 2. For the control logic interface, see Figure 3b. For TTL control interface, see Figure 3b. S0=LSB. 2 SuperLite™ SY55856U Micrel FUNCTIONAL DESCRIPTION Establishing Static Logic Inputs The true pin of a CML input pair is internally biased to ground through a 75kΩ resistor. The complement pin of a CML input pair is internally biased halfway between VCC and ground by a voltage divider consisting of two 75kΩ resistors. To keep a CML input at static logic zero at VCC > 3.0V, leave both inputs unconnected. For VCC ≤ 3.0V, connect the complement input to VCC and leave the true input unconnected. To make an input static logic one, connect the true input to VCC, and leave the complement input unconnected. These are the only safe ways to cause CML inputs to be at a static value. In particular, no CML input should be directly connected to ground. All NC pins in the figures below should be left unconnected. VT (Variable Threshold) Inputs Five inputs to SY55856U, CINV, DELAY_SEL, S0, S1, and S2, are variable threshold inputs. The LVL input determines VCC IN NC /IN the Voltage threshold that differentiates logic high from logic low for these five inputs only. If LVL is left unconnected, the VT inputs will switch at about VCC + GND or V TCL , 2 whichever is higher. To obtain a logic switching threshold different from this, the LVL input must be driven with the actual desired threshold voltage. The user may drive the LVL pin with any voltage between VCC – 0.1V and ground. For example, driving LVL with a voltage set at Vcc – 1.3V causes the VT inputs to accept single ended PECL outputs and switch appropriately. Note that VT inputs are internally clamped so that the threshold will not fall below VTCL Volts. Since driving the LVL input to ground causes the threshold to be somewhere between VTCL (min) and VTCL (max), it is expected that the user will keep the Voltage at the LVL pin at or above VTCL (max). Please refer to Figure 3 for clarification. NC IN NC /IN VCC > 3.0V Figure 1. Hard Wiring a Logic "1"(1) NC IN VCC /IN Logic Switching Threshold VCC ≤ 3.0V VCC Figure 2. Hard Wiring a Logic "0"(1) VCC — 0.1V VCC VTCL Operating Range VTCL VCC — 0.1V 3.0V ≤ VCC ≤ 3.6V 1.10k VCC TTL Driver LVL Input VCC SY55856 3 S0, S1, S2 LVL 909Ω Figure 3a. Logic Switching Threshold Note 1. IN is either the DATA_IN or the CLK_IN input. /IN is either the / DATA_IN or the /CLK_IN input. Figure 3b. Interfacing TTL-to-CML Select (CINV, DELAY_SEL, S0, S1, S2) 3 SuperLite™ SY55856U Micrel ABSOLUTE MAXIMUM RATINGS(1) Symbol Rating Value Unit –0.5 to +6.0 V VCC Power Supply Voltage VIN Input Voltage –0.5 to VCC+5.0 V VOUT CML Output Voltage –0.5 to VCC+5.0 V TA Operating Temperature Range –40 to +85 °C Tstore Storage Temperature Range –55 to +125 °C θJA Package Thermal Resistance (Junction-to-Ambient) Exposed pad soldered to PCB GND pin 28 20 °C/W °C/W θJC Package Thermal Resistance (Junction-to-Case) 4 °C/W Note 1. – Still Air – 500lfpm Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG conditions for extended periods may affect device reliability. CML TERMINATION SY55856U inputs are designed to accept a termination resistor between the true and complement inputs of a CML differential input pair, as shown in Figure 4. All CML inputs accept a CML output from any other member of this family. All CML outputs are source terminated 50Ω differential drivers as shown in Figure 4. SY55856U expects its inputs to be externally terminated. VCC 50Ω 50Ω 50Ω 100Ω 50Ω 16mA SY55856U Figure 4. 50Ω Load CML Output 4 SuperLite™ SY55856U Micrel TRUTH TABLES DATA_IN CLK_IN CINV DATA_OUT /DATA_OUT CLK_OUT /CLK_OUT 0 0 0 0 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 0 0 1 1 0 1 0 1 1 0 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 Table 1. Input to Output Connectivity S2 S1 S0 DATA_OUT (D_SEL=0) (ps) CLK_OUT (D_SEL=1) (ps) (CLK_OUT–CLK_IN) – (DATA_OUT–DATA_IN) (ps) 0 0 0 350 0 –350 0 0 1 300 50 –250 0 1 0 250 100 –150 0 1 1 200 150 –50 1 0 0 150 200 50 1 0 1 100 250 150 1 1 0 50 300 250 1 1 1 0 350 350 Table 2. Nominal Differential Delay Values Note 1. Table 2 defines the approximate relative delay between the two paths. For example, if S2, S1, S0 = 000, and an edge appears at CLK_IN at the same instant as an edge appears at DATA_IN, then an edge at CLK_OUT will appear about 350ps earlier than an edge at DATA_OUT. That is, negative values imply CLK_OUT being shifted early with respect to DATA_OUT. Likewise, a positive value in the third column implies that CLK_OUT is shifted late with respect to DATA_OUT. Please consult the “AC ELECTRICAL CHARACTERISTICS” section for more precise delay values. Note 2. As another example, if an edge at CLK_IN appears 100ps before an edge at DATA_IN, and if S2, S1, S0 = 100, then an edge at CLK_OUT will appear about 50ps after an edge at DATA_OUT. This setting of the select inputs shifts CLK_IN to CLK_OUT about 150ps later than DATA_IN to DATA_OUT, moving the timing of the “C” side from 100ps early to 50ps late, as compared with the “D” channel, going through the part. 5 SuperLite™ SY55856U Micrel DC ELECTRICAL CHARACTERISTICS(1) TA = –40°C Symbol Parameter TA = +25°C TA = +85°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit VCC Power Supply Voltage 2.3 — 3.6 2.3 — 3.6 2.3 — 3.6 V ICC Power Supply Current — — 140 — 115 140 — — 140 mA Note 1. Condition No Load Specification for packaged product only. VT INPUTS DC ELECTRICAL CHARACTERISTICS(1) VCC = 2.3V to 3.6V; GND = 0V; TA = –40°C to +85°C(2) Symbol Parameter Min. Typ. Max. Unit VILVL Input(3) VTCL — VCC - 0.1 V VSW + 0.1 — VCC V Analog VT Input High Voltage(4,5) VILVT VT Input High Voltage(4,5) 0.0 — VSW – 0.1 V VIST Input Switching Threshold Differential Voltage(6) 100 50 — mV VTCL Threshold Clamp Voltage 1.2 — 1.4 V VIHVT Note 1. Specification for packaged product only. Note 2. DC parameters are guaranteed after thermal equilibrium has been established. Note 3. The LVL input determines the voltage switching threshold that differentiates logic high from logic low for the VT inputs S0, S1, S2, S2, and CINV. LVL may be driven to VCC, but this is not useful, as the VT inputs could then not get high enough to reliably indicate logic high. Also, as shown in Figure 3, the LVL input internally clamps at VTCL. If LVL is left unconnected, the VT inputs will switch at about the maximum of VCC + GND VCC and VTCL. = 2 2 Note 4. VT inputs are S0, S1, S2, S3, and CINV. Note 5. VSW is the threshold switching voltage. It is equal to the voltage at the LVL pin, when this voltage is above VTCL (max). VSW is some value between VTCL (min) and VTCL (max) when the Voltage at the LVL pin is below VTCL (max). Note 6. VIST is the voltage difference needed to guarantee a stable logic level. Logic high must be at least VIST above VSW. Logic low must be at most VIST below VSW. Thus, the minimum input swing on a given VT input pin, that is, |VIHVT - VILVT|, must be at least 2×VIST. CML DC ELECTRICAL CHARACTERISTICS(1, 2) VCC = 2.3V to 3.6V; GND = 0V; TA = –40°C to +85°C Symbol Parameter Min. Typ. Max. Unit Condition VID Differential Input Voltage 100 — — mV VIH Input HIGH Voltage 1.6 — VCC V VIL Input LOW Voltage 1.5 — VCC –0.1 V VOH Output HIGH Voltage VCC –0.040 VCC –0.010 VCC V No Load VOL Output LOW Voltage VCC –1.00 VCC –0.800 VCC –0.65 V No Load 0.650 — 0.800 0.400 1.00 — V 40 50 60 Ω Swing(3) VOUT (Swing) Output Voltage ROUT Output Source Impedance (CLK_OUT, /CLK_OUT and DATA_OUT, /DATA_OUT) No Load 50Ω Environment Note 1. Specification for packaged product only. Note 2. DC parameters are guaranteed after thermal equilibrium has been established. Note 3. VOUT(SWING) is defined as the swing on one output of a differential pair, that is |VOH - VOL| on one pin. The swing for common mode noise immunity purposes is 2 × VOUT(SWING). Actual voltage levels and differential swing will depend on customer termination scheme. Typically, a 400mV swing is available in a 50Ω environment. Refer to “CML Termination” figures for more details. 6 SuperLite™ SY55856U Micrel AC ELECTRICAL CHARACTERISTICS(1, 2) VCC = 2.3V to 3.6V; GND = 0V TA = –40°C Symbol Parameter TA = +25°C TA = +85°C Min. Max. Min. Max. Min. Max. Unit fMAX Maximum Frequency 2.5 — 2.5 — 2.5 — GHz ∆t Delay step size 36 52 36 52 36 52 ps tPLH tPHL Delay line insertion delay(3) 232 384 232 384 232 384 ps tDELAY Delay line range 250 365 290 420 335 465 ps tJITTER Output jitter — <1 — <1 — <1 ps(rms) tSKEW Delay line duty cycle skew (ItPLH–tPHLI) — 50 — 50 — 50 ps DC Duty cycle 45 55 45 55 45 55 % tr/tf CML Output rise/fall time (20% to 80%) — 100 — 110 — 120 ps Note 1. Specification for packaged product only. Note 2. Tested using the 50W load, as shown in Figure 4. Note 3. Delay line insertion delay is the minimum input-to-output delay with select control set to S2:S0 = 0 for CLK_OUT and S2:S0 = 7 for DATA_OUT. This resulting delay is the inherent propagation delay. PRODUCT ORDERING CODE Ordering Code Package Type Operating Range Package Marking SY55856UHI H32-1 Industrial SY55856UHI SY55856UHITR* H32-1 Industrial SY55856UHI *Tape and Reel 7 SuperLite™ SY55856U Micrel 32 LEAD EPAD-TQFP (DIE UP) (H32-1) Rev. 01 MICREL, INC. TEL 1849 FORTUNE DRIVE SAN JOSE, CA 95131 + 1 (408) 944-0800 FAX + 1 (408) 944-0970 WEB USA http://www.micrel.com The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2003 Micrel, Incorporated. 8