TPS2836, TPS2837 SYNCHRONOUS-BUCK MOSFET DRIVER WITH DEAD-TIME CONTROL SLVS224A – NOVEMBER 1999 – REVISED NOVEMBER 2000 D D D D D D D D D D D PACKAGE (TOP VIEW) Floating Bootstrap or Ground-Reference High-Side Driver Adaptive Dead-Time Control 50-ns Max Rise/Fall Times With 3.3-nF Load 2.4-A Typical Output Current 4.5-V to 15-V Supply Voltage Range TTL-Compatible Inputs Internal Schottky Bootstrap Diode Low Supply Current....3 mA Typical Ideal for High-Current Single or Multiphase Power Supplies – 40°C to 125°C Operating Virtual Junction-Temperature Range IN PGND DT VCC 1 8 2 7 3 6 4 5 BOOT HIGHDR BOOTLO LOWDR description The TPS2836 and TPS2837 are MOSFET drivers for synchronous-buck power stages. These devices are ideal for designing a high-performance power supply using switching controllers that do not have MOSFET drivers. The drivers are designed to deliver minimum 2-A peak currents into large capacitive loads. The high-side driver can be configured as ground-reference or as floating-bootstrap. An adaptive dead-time control circuit eliminates shoot-through currents through the main power FETs during switching transitions and provides high efficiency for the buck regulator. The TPS2836 has a noninverting input, while the TPS2837 has an inverting input. These drivers, available in 8-terminal SOIC packages, operate over a junction temperature range of – 40°C to 125°C. AVAILABLE OPTIONS PACKAGED DEVICES TJ SOIC (D) TPS2836D TPS2837D – 40°C to 125°C The D package is available taped and reeled. Add R suffix to device type (e.g., TPS2836DR) Related Synchronous MOS FET Drivers DEVICE NAME TPS2830 TPS2831 TPS2832 TPS2833 TPS2834 TPS2835 ADDITIONAL FEATURES INPUTS ENABLE SYNC and CROWBAR ENABLE, CMOS W/O ENABLE, ENABLE SYNC and CROWBAR CMOS ENABLE SYNC and CROWBAR ENABLE, TTL Noninverted Inverted Noninverted Inverted Noninverted Inverted Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TPS2836, TPS2837 SYNCHRONOUS-BUCK MOSFET DRIVER WITH DEAD-TIME CONTROL SLVS224A – NOVEMBER 1999 – REVISED NOVEMBER 2000 functional block diagram 4 8 VCC BOOT 1 MΩ 7 (TPS2836 Only) HIGHDR 250 kΩ 6 BOOTLO 1 IN VCC (TPS2837 Only) 5 LOWDR 250 kΩ 2 3 PGND DT Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION BOOT 8 I Bootstrap terminal. A ceramic capacitor is connected between BOOT and BOOTLO to develop the floating bootstrap voltage for the high-side MOSFET. The capacitor value is typically between 0.1 µF and 1 µF. BOOTLO 6 O This terminal connects to the junction of the high-side and low-side MOSFETs. DT 3 I Dead-time control terminal. Connect DT to the junction of the high-side and low-side MOSFETs HIGHDR 7 O Output drive for the high-side power MOSFET IN 1 I Input signal to the MOSFET drivers (noninverting input for the TPS2836; inverting input for the TPS2837). LOWDR 5 O Output drive for the low-side power MOSFET PGND 2 VCC 4 2 Power ground. Connect to the FET power ground. I Input supply. Recommended that a 1 µF capacitor be connected from VCC to PGND. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS2836, TPS2837 SYNCHRONOUS-BUCK MOSFET DRIVER WITH DEAD-TIME CONTROL SLVS224A – NOVEMBER 1999 – REVISED NOVEMBER 2000 detailed description low-side driver The low-side driver is designed to drive low rDS(on) N-channel MOSFETs. The current rating of the driver is 2 A, source and sink. high-side driver The high-side driver is designed to drive low rDS(on) N-channel MOSFETs. The current rating of the driver is 2 A, source and sink. The high-side driver can be configured as a ground-reference driver or a floating bootstrap driver. The internal bootstrap diode is a Schottky for improved drive efficiency. The maximum voltage that can be applied between the BOOT terminal and ground is 30 V. dead-time (DT) control Dead-time control prevents shoot-through current from flowing through the main power FETs during switching transitions by controlling the turnon times of the MOSFET drivers. The high-side driver is not allowed to turn on until the gate drive voltage to the low-side FET is low, and the low-side driver is not allowed to turn on until the voltage at the junction of the power FETs (Vdrain) is low; the TTL-compatible DT terminal connects to the junction of the power FETs. IN The IN terminal is a TTL-compatible digital terminal that is the input control signal for the drivers. The TPS2836 has a noninverting input; the TPS2837 has an inverting input. absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 16 V Input voltage range: BOOT to PGND (high-side driver ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 30 V BOOTLO to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 16 V BOOT to BOOTLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 16 V IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 16 V DT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 30 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Unless otherwise specified, all voltages are with respect to PGND. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING D 600 mW 6.0 mW/°C 330 mW 240 mW recommended operating conditions MIN NOM MAX UNIT Supply voltage, VCC 4.5 15 V Input voltage 4.5 28 V BOOT to PGND POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TPS2836, TPS2837 SYNCHRONOUS-BUCK MOSFET DRIVER WITH DEAD-TIME CONTROL SLVS224A – NOVEMBER 1999 – REVISED NOVEMBER 2000 electrical characteristics over recommended operating virtual junction temperature range, VCC = 6.5 V, CL = 3.3 nF (unless otherwise noted) supply current PARAMETER TEST CONDITIONS Supply voltage range TYP 4.5 Quiescent current VCC MIN Quiescent current Quiescent current VCC =15 V, VCC =15 V, V(ENABLE) = LOW V(ENABLE) = HIGH VCC =12 V, fSWX = 200 kHz, CHIGHDR = 50 pF, BOOTLO grounded, CLOWDR = 50 pF, See Note 2 MAX 15 100 300 400 3 UNIT V µA mA NOTE 2: Ensured by design, not production tested. output drivers PARAMETER TEST CONDITIONS MIN TYP Duty cycle < 2%, tpw < 100 µs (see Note 3) VBOOT – VBOOTLO = 4.5 V, VHIGHDR = 4 V VBOOT – VBOOTLO = 6.5 V, VHIGHDR = 5 V VBOOT – VBOOTLO = 12 V, VHIGHDR = 10.5 V 0.7 1.1 1.1 1.5 2 2.4 High side High-side source (see Note 4) Duty cycle < 2%, tpw < 100 µs (see Note 3) VBOOT – VBOOTLO = 4.5 V, VHIGHDR = 0.5V VBOOT – VBOOTLO = 6.5 V, VHIGHDR = 1.5 V VBOOT – VBOOTLO = 12 V, VHIGHDR = 1.5 V 1.2 1.4 1.3 1.6 2.3 2.7 Duty cycle < 2%, tpw < 100 µs (see Note 3) VCC = 4.5 V, VCC = 6.5 V, VLOWDR = 4 V VLOWDR = 5 V 1.3 1.8 L id sink i k Low-side (see Note 4) 2 2.5 VCC = 12 V, VCC = 4.5 V, VLOWDR = 10.5 V 3 3.5 VLOWDR = 0.5V VLOWDR = 1.5 V 1.4 1.7 2 2.4 VLOWDR = 1.5 V 2.5 3 High-side Hi h id sink i k (see Note 4) Peak outputcurrent Low side Low-side source (see Note 4) Duty cycle < 2%, tpw < 100 µs (see Note 3) VCC = 6.5 V, VCC = 12 V, MAX A A A A VBOOT – VBOOTLO = 4.5 V, VHIGHDR = 0.5 V VBOOT – VBOOTLO = 6.5 V, VHIGHDR = 0.5 V VBOOT – VBOOTLO = 12 V, VHIGHDR = 0.5 V 5 High-side sink (see Note 4) 75 High-side source (see Note 4) VBOOT – VBOOTLO = 4.5 V, VHIGHDR = 4 V VBOOT – VBOOTLO = 6.5 V, VHIGHDR = 6 V VBOOT – VBOOTLO = 12 V, VHIGHDR =11.5 V Output resistance Low-side sink (see Note 4) Low-side source (see Note 4) VDRV = 4.5 V, VDRV = 6.5 V VLOWDR = 0.5 V VLOWDR = 0.5 V VDRV = 12 V, VDRV = 4.5 V, VLOWDR = 0.5 V VDRV = 6.5 V, VDRV = 12 V, VLOWDR = 4 V VLOWDR = 6 V UNIT 5 Ω 5 75 Ω 75 9 7.5 Ω 6 75 75 Ω VLOWDR = 11.5 V 75 NOTES: 3. Ensured by design, not production tested. 4. The pullup/pulldown circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the combined current from the bipolar and MOSFET transistors. The output resistance is the rDS(on) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS2836, TPS2837 SYNCHRONOUS-BUCK MOSFET DRIVER WITH DEAD-TIME CONTROL SLVS224A – NOVEMBER 1999 – REVISED NOVEMBER 2000 electrical characteristics over recommended operating virtual junction temperature range, VCC = 6.5 V, CL = 3.3 nF (unless otherwise noted) (continued) dead-time PARAMETER VIH VIL High-level input voltage VIH VIL High-level input voltage Low-level input voltage Low-level input voltage TEST CONDITIONS LOWDR DT Over the VCC range (see Note 3) MIN TYP MAX UNIT 0.7VCC V 1 V 2 Over the VCC range V 1 V NOTE 3: Ensured by design, not production tested. digital control terminals (IN) PARAMETER VIH VIL TEST CONDITIONS High-level input voltage TYP MAX UNIT 2 Over the VCC range Low-level input voltage MIN V 1 V switching characteristics over recommended operating virtual junction temperature range, CL = 3.3 nF (unless otherwise noted) PARAMETER TEST CONDITIONS HIGHDR output (see Note 3) Rise time LOWDR output (see Note 3) HIGHDR output (see Note 3) LOWDR output (see Note 3) i low l ((excluding l di deadd d HIGHDR going time) (see Note 3) Propagation delay time LOWDR going i hi high h ((excluding l di dead-time) (see Note 3) Propagation delay time Driver nonoverlap time NOTE 3: LOWDR going i low l ( (excluding l di deadd d time) (see Note 3) DT to LOWDR and LOWDR to HIGHDR (see Note 3) TYP MAX VBOOTLO = 0 V VBOOTLO = 0 V 60 VBOOT = 12 V, VCC = 4.5 V VBOOTLO = 0 V 50 50 VBOOT = 4.5 V, VBOOT = 6.5 V, 30 ns ns 30 VBOOTLO = 0 V 50 VBOOTLO = 0 V VBOOTLO = 0 V 40 ns 40 40 VCC = 6.5 V VCC = 12 V 30 ns 30 VBOOT = 4.5 V, VBOOT = 6.5 V, VBOOTLO = 0 V VBOOTLO = 0 V 95 VBOOT = 12 V, VBOOT = 4.5 V, VBOOTLO = 0 V 65 VBOOTLO = 0 V VBOOTLO = 0 V 80 VBOOTLO = 0 V 60 VBOOT = 6.5 V, VBOOT = 12 V, UNIT 40 VCC = 6.5 V VCC = 12 V VBOOT = 12 V, VCC = 4.5 V Fall time MIN VBOOT = 4.5 V, VBOOT = 6.5 V, 80 70 VCC = 4.5 V VCC = 6.5 V 80 VCC = 12 V VCC = 4.5 V 60 VCC = 6.5 V VCC = 12 V 70 40 170 25 135 15 85 ns ns ns ns Ensured by design, not production tested. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TPS2836, TPS2837 SYNCHRONOUS-BUCK MOSFET DRIVER WITH DEAD-TIME CONTROL SLVS224A – NOVEMBER 1999 – REVISED NOVEMBER 2000 TYPICAL CHARACTERISTICS FALL TIME vs SUPPLY VOLTAGE RISE TIME vs SUPPLY VOLTAGE 50 50 CL = 3.3 nF TJ = 25°C 45 40 40 t f – Fall Time – ns t r – Rise Time – ns CL = 3.3 nF TJ = 25°C 45 High Side 35 30 Low Side 25 35 High Side 30 25 20 20 15 15 10 Low Side 10 4 5 6 7 9 10 11 12 13 8 VCC – Supply Voltage – V 14 15 4 5 6 Figure 1 FALL TIME vs JUNCTION TEMPERATURE 50 50 VCC = 6.5 V CL = 3.3 nF 45 VCC = 6.5 V CL = 3.3 nF 40 40 t f – Fall Time – ns t r – Rise Time – ns High Side 35 30 Low Side 25 High Side 35 30 25 Low Side 20 20 15 15 10 –50 –25 0 25 50 75 100 125 10 –50 –25 0 25 Figure 3 Figure 4 POST OFFICE BOX 655303 50 75 TJ – Junction Temperature – °C TJ – Junction Temperature – °C 6 14 15 Figure 2 RISE TIME vs JUNCTION TEMPERATURE 45 8 7 9 10 11 12 13 VCC – Supply Voltage – V • DALLAS, TEXAS 75265 100 125 TPS2836, TPS2837 SYNCHRONOUS-BUCK MOSFET DRIVER WITH DEAD-TIME CONTROL SLVS224A – NOVEMBER 1999 – REVISED NOVEMBER 2000 TYPICAL CHARACTERISTICS HIGH-TO-LOW PROPAGATION DELAY TIME vs SUPPLY VOLTAGE, HIGH TO LOW LEVEL 150 t PHL – High-to-Low Propagation Delay Time – ns t PLH – Low-to-High Propagation Delay Time – ns LOW-TO-HIGH PROPAGATION DELAY TIME vs SUPPLY VOLTAGE, LOW TO HIGH LEVEL CL = 3.3 nF TJ = 25°C 140 130 120 110 100 90 80 70 60 Low Side 50 40 30 20 4 5 6 7 9 10 11 12 13 8 VCC – Supply Voltage – V 14 15 150 CL = 3.3 nF TJ = 25°C 140 130 120 110 100 90 80 70 High Side 60 50 40 Low Side 30 20 4 5 6 8 7 9 10 11 12 13 VCC – Supply Voltage – V Figure 5 Figure 6 150 130 VCC = 6.5 V CL = 3.3 nF 120 110 100 High Side 90 80 70 60 Low Side 50 40 30 20 –50 HIGH-TO-LOW PROPAGATION DELAY TIME vs JUNCTION TEMPERATURE t PHL – High-to-Low Propagation Delay Time – ns t PLH – Low-to-High Propagation Delay Time – ns LOW-TO-HIGH PROPAGATION DELAY TIME vs JUNCTION TEMPERATURE 140 14 15 –25 25 75 0 50 100 TJ – Junction Temperature – °C 125 150 140 130 VCC = 6.5 V CL = 3.3 nF 120 110 100 90 High Side 80 70 60 50 Low Side 40 30 20 –50 –25 0 25 50 75 100 125 TJ – Junction Temperature – °C Figure 7 Figure 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TPS2836, TPS2837 SYNCHRONOUS-BUCK MOSFET DRIVER WITH DEAD-TIME CONTROL SLVS224A – NOVEMBER 1999 – REVISED NOVEMBER 2000 TYPICAL CHARACTERISTICS DRIVER-OUTPUT FALL TIME vs LOAD CAPACITANCE DRIVER-OUTPUT RISE TIME vs LOAD CAPACITANCE 1000 1000 VCC = 6.5 V TJ = 27°C t f – Fall Time – ns t r – Rise Time – ns VCC = 6.5 V TJ = 27°C 100 High Side Low Side 10 1 0.01 1 0.1 10 100 High Side Low Side 10 1 0.01 100 CL – Load Capacitance – nF 10 Figure 9 Figure 10 SUPPLY CURRENT vs SUPPLY VOLTAGE SUPPLY CURRENT vs SUPPLY VOLTAGE 100 25 6000 TJ = 25°C CL = 50 pF 5500 TJ = 25°C CL = 50 pF 5000 20 4500 ICC – Supply Current – mA ICC – Supply Current – µ A 1 0.1 CL – Load Capacitance – nF 500 kHz 4000 300 kHz 3500 200 kHz 3000 100 kHz 50 kHz 25 kHz 2500 2000 1500 1000 2 MHz 15 10 1 MHz 5 500 0 0 4 6 8 10 12 14 16 4 VCC – Supply Voltage – V 8 10 Figure 12 POST OFFICE BOX 655303 12 VCC – Supply Voltage – V Figure 11 8 6 • DALLAS, TEXAS 75265 14 16 TPS2836, TPS2837 SYNCHRONOUS-BUCK MOSFET DRIVER WITH DEAD-TIME CONTROL SLVS224A – NOVEMBER 1999 – REVISED NOVEMBER 2000 TYPICAL CHARACTERISTICS PEAK SOURCE CURRENT vs SUPPLY VOLTAGE PEAK SINK CURRENT vs SUPPLY VOLTAGE 4 4 TJ = 25°C TJ = 25°C 3.5 3 3 Low Side Peak Sink Current – A Peak Source Current – A 3.5 2.5 2 High Side 1.5 Low Side 2.5 2 High Side 1.5 1 1 0.5 0.5 0 0 4 6 8 10 12 14 16 4 6 VCC – Supply Voltage – V Figure 13 12 10 14 16 Figure 14 INPUT THRESHOLD VOLTAGE vs SUPPLY VOLTAGE INPUT THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 2.0 2.0 TJ = 25°C VCC = 6.5 V V IT – Input Threshold Voltage – V V IT – Input Threshold Voltage – V 8 VCC – Supply Voltage – V 1.8 1.6 1.4 1.2 1 4 6 8 10 12 14 16 1.8 1.6 1.4 1.2 1 –50 –25 0 25 50 75 100 125 TJ – Junction Temperature – °C VCC – Supply Voltage – V Figure 15 Figure 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TPS2836, TPS2837 SYNCHRONOUS-BUCK MOSFET DRIVER WITH DEAD-TIME CONTROL SLVS224A – NOVEMBER 1999 – REVISED NOVEMBER 2000 APPLICATION INFORMATION Figure 17 shows the circuit schematic of a 100-kHz synchronous-buck converter implemented with a TL5001A pulse-width-modulation (PWM) controller and a TPS2837 driver. The converter operates over an input range from 4.5 V to 12 V and has a 3.3-V output. The circuit can supply 3 A continuous load and the transient load is 5 A. The converter achieves an efficiency of 94% for VIN = 5 V, Iload=1 A, and 93% for VIN = 5 V, Iload = 3 A. VIN + C10 100 µF C5 100 µF + R1 1 kΩ U1 TPS2837 1 IN C11 0.47 µF R5 0Ω BOOT 2 PGND HIGHDR 3 DT BOOTLO 4 VCC LOWDR 8 C15 1.0 µF 7 R6 1 MΩ Q1 Si4410 6 5 R7 3.3 Ω R11 4.7 Ω Q2 Si4410 C14 1 µF GND L1 27 µH C13 10 µF C7 100 µF + C12 100 µF + C6 1000 pF RTN C8 0.1 µF C3 0.0022 µF U2 TL5001A C2 VCC 0.033 µF R2 1.6 kΩ COMP 3 2 1 C9 0.22 µF OUT 6 DTC FB 4 5 SCP RT 7 R8 121 kΩ C4 0.022 µF R3 180 Ω R4 2.32 kΩ GND C1 1 µF 8 R9 90.9 kΩ R10 1.0 kΩ Figure 17. 3.3 V 3 A Synchronous-Buck Converter Circuit 10 3.3 V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS2836, TPS2837 SYNCHRONOUS-BUCK MOSFET DRIVER WITH DEAD-TIME CONTROL SLVS224A – NOVEMBER 1999 – REVISED NOVEMBER 2000 APPLICATION INFORMATION Great care should be taken when laying out the PC board. The power-processing section is the most critical and will generate large amounts of EMI if not properly configured. The junction of Q1, Q2, and L1 should be very tight. The connection from Q1 drain to the positive sides of C5, C10, and C11 and the connection from Q2 source to the negative sides of C5, C10, and C11 should be as short as possible. The negative terminals of C7 and C12 should also be connected to Q2 source. Next, the traces from the MOSFET driver to the power switches should be considered. The BOOTLO signal from the junction of Q1 and Q2 carries the large gate drive current pulses and should be as heavy as the gate drive traces. The bypass capacitor (C14) should be tied directly across VCC and PGND. The next most sensitive node is the FB node on the controller (terminal 4 on the TL5001A). This node is very sensitive to noise pickup and should be isolated from the high-current power stage and be as short as possible. The ground around the controller and low-level circuitry should be tied to the power ground as the output. If these three areas are properly laid out, the rest of the circuit should not have other EMI problems and the power supply will be relatively free of noise. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TPS2836, TPS2837 SYNCHRONOUS-BUCK MOSFET DRIVER WITH DEAD-TIME CONTROL SLVS224A – NOVEMBER 1999 – REVISED NOVEMBER 2000 MECHANICAL DATA D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 0.010 (0,25) M 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 0.010 (0,25) 1 7 0°– 8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047 / D 10/96 NOTES: A. B. C. D. 12 All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 2000, Texas Instruments Incorporated