Standard Products UT22VP10 Universal RADPALTM Data Sheet November 2000 FEATURES q High speed Universal RADPAL - tPD: 15.5ns, 20ns, 25ns maximum - fMAX1: 33MHz maximum external frequency - Supported by industry-standard programmer Amorphous silicon anti-fuse q Radiation-hardened process and design; total dose irradiation testing to MIL-STD-883, Method 1019 - Total dose: 1.0E6 rads(Si) - Upset threshold 50 MeV-cm2/mg (min) - Latchup immune(LET>109 MeV-cm2/mg) q QML Q & V compliant q Asynchronous and synchronous RADPAL operation - Synchronous PRESET - Asynchronous RESET q Packaging options: - 24-pin 100-mil center DIP (0.300 x 1.2) - 24-lead flatpack (.45 x .64) - 28-lead quad-flatpack (.45 x .45) q Up to 22 input and 10 output drivers may be configured - CMOS & TTL-compatible input and output levels - Three-state output drivers q Standard Military Drawing 5962-94754 available q Variable product terms, 8 to 16 per output q 10 user-programmable output macrocells - Registered or combinatorial operation - Output driver polarity control selectable - Two feedback paths available 13 12 11 10 9 8 7 6 5 4 3 2 1 VSS Reset PROGRAMMABLE ARRAY LOGIC (132 X 44) 8 10 12 14 16 16 14 12 10 8 Preset Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell CP VDD 14 15 16 17 18 19 20 21 22 23 24 Figure 1. Block Diagram 1 PRODUCT DESCRIPTION QUAD-FLATPACK PIN CONFIGURATION The UT22VP10 RADPAL is a fuse programmable logic array device. The familiar sum-of-products (AND-OR) logic structure is complemented with a programmable macrocell. The UT22VP10 is available in 24-pin DIP, 24-lead flatpack, and 28-lead quad-flatpack package offerings providing up to 22 inputs and 10 outputs. Amorphous silicon anti-fuse technology provides the programming of each output. The user specifies whether each of the potential outputs is registered or combinatorial. Output polarity is also individually selected, allowing for greater flexibility for output configuration. A unique output enable function allows the user to configure bidirectional I/O on an individual basis. The UT22VP10 architecture implements variable sum terms providing 8 to 16 product terms to outputs. This feature provides the user with increased logic function flexibility. Other features include common synchronous preset and asynchronous reset. These features eliminate the need for performing the initialization function. The UT22VP10 provides a device with the flexibility to implement logic functions in the 500 to 800 gate complexity. The flexible architecture supports the implementation of logic functions requiring up to 21 inputs and only a single output or down to 12 inputs and 10 outputs. Development and programming support for the UT22VP10 is provided by DATA I/O. DIP & FLATPACK PIN CONFIGURATION I I 4 CK/I VDD VDD I/O0 I/O1 3 2 1 28 27 26 I 5 25 I/O2 I 6 24 I/O3 I 7 23 I/O4 VSS 8 22 VSS I 9 I 10 I 11 21 12 13 I I 14 15 VSS VSS 16 I 17 I/O5 20 I/O6 19 I/O7 18 I/O9 I/O8 PIN NAMES CK/I Clock/Data Input I Data Input I/O Data Input/Output VDD Power VSS Ground FUNCTION DESCRIPTION 2 CK/I I 1 2 24 23 VDD I/O0 I 3 22 I/O1 I 4 21 I/O2 I I 5 6 20 19 I/O3 I/O4 I 7 18 I/O5 I 8 17 I/O6 I I 9 10 16 15 I/O7 I/O8 I VSS 11 14 I/O9 12 13 I The UT22VP10 RAD PAL implements logic functions as sumof-products expressions in a one-time programmable-AND/ fixed-OR logic array. User-defined functions are created by programming the connections of input signals into the array. User-configurable output structures in the form of I/O macrocells further increase logic flexibility. Table 1. Macrocell Configuration Table1, 2, 3 C2 C1 C0 Output Type Polarity Feedback 0 0 0 Registered Active LOW Registered 0 0 1 Registered Active HIGH Registered X 1 0 Combinatorial Active LOW I/O X 1 1 Combinatorial Active HIGH I/O 1 0 0 Registered Active LOW I/O 1 0 1 Registered Active HIGH I/O Notes: 1. 0 equals programmed low or programmed. 2. 1 equals programmed high or unprogrammed. 3. X equals don’t care. OVERVIEW The UT22VP10 RAD PAL architecture (see figure 1) has 12 dedicated inputs and 10 I/Os to provide up to 22 inputs and 10 outputs for creating logic functions. At the core of the device is a one-time programmable anti-fuse AND array that drives a fixed OR array. With this structure, the UT22VP10 can implement up to 10 sum-of-products logic expressions. Associated with each of the 10 OR functions is a macrocell which is independently programmed to one of six different configurations. The one-time programmable macro cells allow each I/O to create sequential or combinatorial logic functions with either Active-High or Active-Low polarity. LOGIC ARRAY The one-time programmable AND array of the UT22VP10 RADPAL is formed by input lines intersecting product terms. The input lines and product terms are used as follows: 44 input lines: • 24 input lines carry the true and complement of the signals applied to the input pins • 20 lines carry the true and complement values of feedback or input signals from the 10 I/Os 132 product terms: • 120 product terms (arranged in 2 groups of 8, 10, 12, 14, and 16) used to form logic sums • 10 output enable terms (one for each I/O) • 1 global synchronous preset term • 1 global asynchronous reset term a Don’t Care state exists and that term will always be a logical one. PRODUCT TERMS The UT22VP10 provides 120 product terms that drive the 10 OR functions. The 120 product terms connect to the outputs in two groups of 8, 10, 12, 14, and 16 to form logical sums. MACROCELL ARCHITECTURE The output macrocell provides complete control over the architecture of each output. Configuring each output independently permits users to tailor the configuration of the UT22VP10 to meet design requirements. Each I/O macrocell (see figure 2) consists of a D flip-flop and two signal-select multiplexers. Three configuration select bits controlling the multiplexers determine the configuration of each UT22VP10 macrocell (see table 1). The configuration select bits determine output polarity, output type (registered or combinatorial) and input feedback type (registered or I/O). See figure 3 for equivalent circuits for the macrocell configurations. OUTPUT FUNCTIONS The signal from the OR array may be fed directly to the output pin (combinatorial function) or latched in the D flip-flop (registered function). The D flip-flop latches data on the rising edge of the clock. When the synchronous preset term is satisfied, the Q output of the D flip-flop output will be set logical one at the next rising edge of the clock input. Satisfying the asynchronous clear term sets Q logical zero, regardless of the clock state. If both terms are satisfied simultaneously, the clear will override the preset. At each input-line/product-term intersection there is an antifuse cell which determines whether or not there is a logical connection at that intersection. A product term which is connected to both the true and complement of an input signal will always be logical zero, and thus will not effect the OR function that it drives. When there are no connections on a product term 3 OUTPUT SELECT MUX AR D Q CK Q C1 C0 SP INPUT/ FEEDBACK MUX C1 C2 C1 C0 C2 Figure 2. Macrocell OUTPUT POLARITY BIDIRECTIONAL I/O Each macrocell can be configured to implement Active-High or Active-Low logic. Programmable polarity eliminates the need for external inverters. The feedback signal is taken from the I/O pin when the macrocell implements a combinatorial function (C1 = 1) or a registered function (C2 = 1, C 1 = 0). In this case, the pin can be used as a dedicated input, a dedicated output, or a bidirectional I/O. OUTPUT ENABLE The output of each I/O macrocell can be enabled or disabled under the control a programmable output enable product term. The output signal is propagated to the I/O pin when the logical conditions programmed on the output enable term are satisfied. Otherwise, the output buffer is driven to the high-impedance state. POWER-ON RESET The output enable term allows the I/O pin to function as a dedicated input, dedicated output, or bidirectional I/O. When every connection is unprogrammed, the output enable product term permanently enables the output buffer and yields a dedicated output. If every connection is programmed, the enable term is logically low and the I/O functions as a dedicated input. ANTI-FUSE SECURITY REGISTER FEEDBACK The feedback signal to the AND array is taken from the Q output when the I/O macrocell implements a registered function (C2 = 0, C1 = 0). 4 To ease system initialization, all D flip-flops will power-up to a reset condition and the Q output will be low. The actual output of the UT22VP10 will depend on the programmed output polarity. The reset delay time is 5µs maximum. See the Power-up Reset section for a more descriptive list of POR requirements. The UT22VP10 provides a security bit that prevents unauthorized reading or copying of designs programmed into the device. The security bit is set by the PLD programmer at the conclusion of the programming cycle. Once the security bit is set it is no longer possible to verify (read) or program the UT22VP10. NOTE: UTMC does not recommend using the UT22VP10 unless the security fuse has been programmed. The security bit must be blown to ensure proper functionality of the UT22VP10. AR D Q CK Q SP Registered Feedback, Registered, Active-Low Output (C2 = 0, C 1 = 0, C0 = 0) AR D Q CK Q SP Registered Feedback, Registered, Active-High Output (C2 = 0, C1 = 0, C0 = 1) I/O Feedback, Combinatorial, Active-Low Output (C 2 = X, C1 = 1, C0 = 0) Figure 3. Macrocell Configuration (continued on next page) 5 I/O Feedback, Combinatorial, Active-High Output (C 2 = X, C 1 = 1, C 0 = 1) AR D Q CK Q SP I/O Feedback, Registered, Active-Low Output (C 2 = 1, C 1 = 0, C 0 = 0) AR D Q CK Q SP I/O Feedback, Registered, Active-High Output (C 2 = 1, C1 = 0, C 0 = 1) Figure 3. Macrocell Configuration 6 ABSOLUTE MAXIMUM RATINGS 1 SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O2 Input voltage any pin -0.3 to +7.0 V TSTG Storage Temperature range -65 to +150 °C TJ Maximum junction temperature +175 °C TS Lead temperature (soldering 10 seconds) +300 °C ΘJC Thermal resistance junction to case 20 °C/W II DC input current ±10 mA PD3 Maximum power dissipation 1.6 W IO Output sink current 12 mA Notes: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Minimum voltage is -0.6VDD which may undershoot to -2.0VDD for pulses of less than 20ns. Maximum output pin voltage is VDD +0.75VDD which may overshoot to +7.0V DD for pulses of less than 20ns. 3. (ICC max + IOS) 5.5V. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMIT UNITS VDD1 Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 °C Notes: 1. See page 12 for minimum V DD requirements at power-up. 7 DC ELECTRICAL CHARACTERISTICS 1, 7 (VDD2 = 5.0V ±10%; VSS = 0V3, -55°°C < TC < +125°°C) SYMBOL PARAMETER CONDITION MINIMUM MAXIMUM UNIT VIL Low-level input voltage TTL -- .8 V VIH High-level input voltage TTL 2.2 -- V VIL Low-level input voltage CMOS -- .3*V DD V VIH High-level input voltage CMOS .7*V DD -- V VOL Low-level output voltage IOL = 12.0mA, VDD = 4.5V (TTL) .4 V VOH High-level output voltage IOH = -12.0mA, V DD = 4.5V (TTL) 2.4 -- V VOL Low-level output voltage IOL = 200µ µA, VDD = 4.5V (CMOS) -- VSS+0.05 V VOH High-level output voltage IOH = -200µ µA, VDD = 4.5V (CMOS) VDD-0.05 -- V IIN Input leakage current VIN = VDD and VSS -10 10 µA IOZ Three-state output leakage current VO = VDD and VSS, VDD = 5.5V -10 10 µA IOS4,5 Short-circuit output current VDD = 5.5V, V O = VDD VDD = 5.5V, V O = 0V -160 160 mA CIN5,6 Input capacitance ƒ=1MHz @0V -- 15 pF CI/O5,6 Bidirectional capacitance ƒ=1MHz @0V -- 15 pF IDD5 Supply current: Output VDD = 5.5V three-state, worst-case pattern programmed, ƒ=fMAX1 -- 120 mA IDDQ Supply current: Unprogrammed -- 25 mA VDD = 5.5V Notes: 1. All specifications valid for radiation dose < 1E6 rads(Si). 2. See page 12 for minimum V DD requirements at power-up. 3. Maximum allowable relative shift equals 50mV. 4. Duration not to exceed 1 second, one output at a time. 5. Tested initially and after any design or process changes that affect that parameter and, therefore, shall be guaranteed to the limit specified. 6. All pins not being tested are to be open. 7. CMOS levels only tested on CMOS devices. TTL levels only tested on TTL devices. 8 AC CHARACTERISTICS READ CYCLE (Post-Radiation) 1,2 (VDD3 = 5.0V ±10%; -55°C < T C < +125°C) SYMBOL tPD4,5,6 PARAMETER 22VP10-15.5 MIN MAX Input to output propagation delay 22VP10-20 MIN MAX 22VP10-25 MIN MAX UNIT 15.5 20 25 ns tEA4 Input to output enable delay 23 23 25 ns tER4 Input to output disable delay 23 23 25 ns tCO4,6 Clock to output delay 15 15 15 ns tCO24 Clock to combinatorial output delay via internal registered feedback 24 24 28 ns tS4,6 Input or feedback setup time 15 15 18 ns tH4,6 Input or feedback hold time 2 2 2 ns External clock period (tCO + tS) 30 30 33 ns tWH, WL4 Clock width, clock high time, clock low time 12 12 14 ns fMAX14,6 External maximum frequency (1/(tCO + tS)) 33 33 30 MHz fMAX24,6 Data path maximum frequency (1/(tWH + tWL)) 42 42 36 MHz fMAX34,6 Internal feedback maximum frequency (1/(tCO + tCF)) 32 32 32 MHz tCF4 Register clock to feedback input 13 13 13 ns tAW4 Asynchronous reset width 20 20 25 ns tAR4 Asynchronous reset recovery time 20 20 25 ns tAP4 Input to asynchronous reset tP4 20 20 25 ns tSPR4,6 Synchronous preset recovery time 20 20 25 ns tPR4,6 Power up reset time 1.0 1.0 1.0 µs Notes: 1. Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1.0E6 rads(Si). 2. Guaranteed by characterization. 3. See page 12 for minimum VDD requirements for power-up. 4. Tested initially and after any design or process changes that affect. 5. Device 22VP10-15 tested at -55°C, +25°C and +50°C. At 125°C, tested to 20ns limit. 6. Tested on Programmed Test Ring only. 9 INPUT OR BIDIRECTIONAL INPUT INPUT OR BIDIRECTIONAL VT VT INPUT tS tPD tH CLOCK COMBINATIONAL OUTPUT VT VT tCO REGISTERED OUTPUT VT tp Registered Output Combinatorial Output tWH INPUT OR BIDIRECTIONAL VT INPUT tER VT tEA OUTPUT VT tWL Clock Width Combinatorial Output (VOH - 0.5V, V OL + 0.5V) tAW INPUT ASSERTING ASYNCHRONOUS RESET INPUT ASSERTING SYNCHRONOUS PRESET VT t AP tS CLOCK REGISTERED OUTPUT VT VT REGISTERED OUTPUT Asynchronous Reset Notes: 1. VT = 1.5V. 2. Input pulse amplitude 0V to 3.0V. 3. Input rise and fall times 3ns maximum. 10 tH tSPR VT VT tCO tAR CLOCK VT VT Synchronous Preset Figure 4. AC Electrical1,2,3 CLK PRODUCT TERMS CLK Q D PRODUCT TERMS REGISTER Q D REGISTER Q Q tCF 1 PRODUCT TERMS PRODUCT TERMS CLK D OUTPUT OUTPUT Q REGISTER Clock to Combinatorial Output (tCO2) Note: 1. tCF defined as the propagation delay from Q to D register input. fMAX3; Internal Feedback 1 tCO + tCF Figure 5. Signal Paths 11 POWER-UP RESET The power-up reset feature ensures that all flip-flops will be reset to LOW after the device has been powered up. The output state will depend on the programmed pattern. This feature is valuable in simplifying state machine initialization. See figure 6 for a timing diagram. Due to the synchronous operation of the power-up reset and the wide range of ways V DD can rise to its steady state, the following five conditions are required to ensure a valid power-up reset. 4. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met. 5. The power-up voltage must meet the minimum V DD requirements described by the following device dependent and temperature dependent equations: SMD Device types 01, 02, 03, 04, 08 VDD =4.61V -0.0090*(oC) SMD Device types 05, 06, 07 VDD =4.41 -0.0090* (oC) 1. The voltage supplied to the V DD pin(s) must be equal to 0V prior to the intended power-up sequence. 2. The voltage on V DD must rise from 0V to 1V at a rate of 0.1V/s or faster. 3. The V DD rise must be continuously increasing with respect to time, through 3V, and monotonic thereafter. VDD CMOS and TTL CMOS Note: The minimum VDD requirement above is not applicable if the UT22VP10 application is purely combinatorial (i.e. no registered outputs). VDD VDD min tPR REGISTERED ACTIVE-LOW OUTPUT tS CLOCK tWL Figure 6. Power-Up Reset Waveform RADIATION HARDNESS The UT22VP10 RADPAL incorporates special design and layout features which allow operation in high-level radiation environments. UTMC has developed special low-temperature processing techniques designed to enhance the total-dose radiation hardness of both the gate oxide and the field oxide while maintaining the circuit density and reliability. For transient radiation hardness and latchup immunity, UTMC builds radiation-hardened products on epitaxial wafers using an advanced twin-tub CMOS process. RADIATION HARDNESS DESIGN SPECIFICATIONS1 PARAMETER CONDITION MINIMUM UNIT +25°C per MIL-STD-883 Method 1019 1.0E6 rads(Si) LET Threshold -55°C to +125°C 50 MeV-cm2/mg Neutron Fluence 1MeV equivalent 1.0E14 n/cm2 Total Dose Note: 1. The RADPAL will not latchup during radiation exposure under recommended operating conditions. 12