VND830LSP ® DOUBLE CHANNEL HIGH SIDE DRIVER TYPE VND830LSP RDS(on) 60 mΩ (*) IOUT 18 A (*) VCC 36 V (*) Per each channel CMOS COMPATIBLE INPUTS OPEN DRAIN STATUS OUTPUTS ■ ON STATE OPEN LOAD DETECTION ■ OFF STATE OPEN LOAD DETECTION ■ SHORTED LOAD PROTECTION ■ UNDERVOLTAGE AND OVERVOLTAGE SHUTDOWN ■ LOSS OF GROUND PROTECTION ■ VERY LOW STAND-BY CURRENT ■ ■ ■ 10 1 PowerSO-10™ REVERSE BATTERY PROTECTION (**) DESCRIPTION The VND830LSP is a monolithic device made by using STMicroelectronics VIPower M0-3 Technology, intended for driving any kind of load with one side connected to ground. Active VCC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). Active current limitation combined with thermal shutdown and automatic restart protects the device against overload. The device detects open load condition both in on and off state. The openload threshold is aimed at detecting the 5W/12V standard bulb as an openload fault in the on state. Device automatically turns off in case of ground pin disconnection. BLOCK DIAGRAM VCC VCC CLAMP OVERVOLTAGE UNDERVOLTAGE GND CLAMP 1 OUTPUT1 INPUT1 DRIVER 1 CLAMP 2 STATUS1 CURRENT LIMITER 1 OVERTEMP. 1 LOGIC DRIVER 2 OUTPUT2 OPENLOAD ON 1 CURRENT LIMITER 2 INPUT2 OPENLOAD OFF 1 OPENLOAD ON 2 STATUS2 OPENLOAD OFF 2 OVERTEMP. 2 (**) See application schematic at page 8 March 2003 1/18 VND830LSP ABSOLUTE MAXIMUM RATING Symbol VCC - VCC - IGND IOUT - IOUT IIN ISTAT VESD Ptot EMAX Tj Tc Tstg Parameter DC Supply Voltage Reverse DC Supply Voltage DC Reverse Ground Pin Current DC Output Current Reverse DC Output Current DC Input Current DC Status Current Electrostatic Discharge (Human Body Model: R=1.5KΩ; C=100pF) Value 41 - 0.3 - 200 Internally Limited -6 +/- 10 +/- 10 Unit V V mA A A mA mA - INPUT 4000 V - STATUS 4000 V - OUTPUT 5000 V - VCC Power Dissipation TC=25°C Maximum Switching Energy 5000 74 V W 52 mJ Internally Limited - 40 to 150 - 55 to 150 °C °C °C (L=0.14mH; RL=0Ω; Vbat=13.5V; Tjstart=150ºC; IL=14A) Junction Operating Temperature Case Operating Temperature Storage Temperature CONNECTION DIAGRAM (TOP VIEW) OUTPUT OUTPUT N.C. OUTPUT OUTPUT 5 4 3 6 7 GROUND INPUT 1 STATUS 1 STATUS 2 INPUT 2 8 9 2 10 1 1 1 2 2 11 V CC CURRENT AND VOLTAGE CONVENTIONS IS I IN1 VCC VCC INPUT 1 ISTAT1 VIN1 STATUS 1 VSTAT1 IOUT1 IIN2 OUTPUT 1 INPUT 2 VIN2 ISTAT2 IOUT2 STATUS 2 VSTAT2 GND OUTPUT 2 VOUT2 IGND 2/18 1 VOUT1 VND830LSP THERMAL DATA Symbol Rthj-case Parameter Thermal Resistance Junction-case Value 2 Unit °C/W Rthj-amb Thermal Resistance Junction-ambient 52 (*) °C/W (*) When mounted on a standard single-sided FR-4 board with 50mm2 of Cu (at least 35µm thick). Horizontal mounting and no artificial air flow. ELECTRICAL CHARACTERISTICS (8V<VCC<36V; -40°C< Tj <150°C, unless otherwise specified) (Per each channel) POWER OUTPUT Symbol VCC (**) VUSD (**) VOV (**) RON IS (**) IL(off1) IL(off2) IL(off3) IL(off4) Parameter Operating Supply Voltage Undervoltage Shut-down Overvoltage Shut-down On State Resistance Supply Current Off State Output Current Off State Output Current Off State Output Current Off State Output Current Test Conditions Min 5.5 3 36 Typ 13 4 Max 36 5.5 IOUT =2A; Tj=25°C 60 Unit V V V mΩ IOUT =2A; VCC> 8V Off State; VCC=13V; VIN=VOUT=0V 12 120 40 mΩ µA Off State; VCC=13V; Tj =25°C; VIN=VOUT=0V 12 25 µA On State; VCC=13V 5 7 50 0 5 3 mA µA µA µA µA Typ Max Unit VIN=VOUT=0V; VCC=36V; Tj=125°C VIN=0V; VOUT=3.5V VIN=VOUT=0V; Vcc=13V; Tj =125°C VIN=VOUT=0V; Vcc=13V; Tj =25°C 0 -75 Test Conditions RL=6.5Ω from VIN rising edge to VOUT=1.3V RL=6.5Ω from VIN falling edge to VOUT=11.7V Min (**) Per device SWITCHING (VCC =13V) Symbol Parameter td(on) Turn-on Delay Time td(off) Turn-off Delay Time dVOUT/ dt(on) Turn-on Voltage Slope RL=6.5Ω from VOUT=1.3V to VOUT=10.4V dVOUT/ dt(off) Turn-off Voltage Slope RL=6.5Ω from VOUT=11.7V to VOUT=1.3V 30 µs 30 µs See relative diagram See relative diagram V/µs V/µs LOGIC INPUT Symbol VIL IIL VIH IIH VI(hyst) VICL Parameter Input Low Level Low Level Input Current Input High Level High Level Input Current Input Hysteresis Voltage Input Clamp Voltage Test Conditions VIN = 1.25V Min Typ 1 3.25 VIN = 3.25V IIN = 1mA IIN = -1mA Max 1.25 10 0.5 6 6.8 -0.7 8 Unit V µA V µA V V V 3/18 1 VND830LSP ELECTRICAL CHARACTERISTICS (continued) STATUS PIN Symbol VSTAT ILSTAT CSTAT VSCL Parameter Test Conditions Status Low Output Voltage ISTAT= 1.6 mA Status Leakage Current Normal Operation; VSTAT= 5V Status Pin Input Normal Operation; VSTAT= 5V Capacitance ISTAT= 1mA Status Clamp Voltage ISTAT= - 1mA Min 6 Typ 6.8 Max 0.5 10 Unit V µA 100 pF 8 V -0.7 V PROTECTIONS Symbol TTSD TR Thyst tSDL Parameter Shut-down Temperature Reset Temperature Thermal Hysteresis Status Delay in Overload Conditions Ilim Current limitation Vdemag Turn-off Output Clamp Voltage Test Conditions Min 150 135 7 Typ 175 18 23 5.5V < VCC < 36V IOUT=2A; L= 6mH Unit °C °C °C 20 µs 29 A 29 A 15 Tj>TTSD VCC=13V Max 200 VCC-41 VCC-48 VCC-55 V OPENLOAD DETECTION Symbol IOL tDOL(on) VOL TDOL(off) Parameter Openload ON State Detection Threshold Openload ON State Detection Delay Openload OFF State Voltage Detection Threshold Openload Detection Delay at Turn Off Test Conditions Min Typ Max Unit 0.6 0.9 1.2 A 200 µs 3.5 V 1000 µs VIN=5V IOUT=0A VIN=0V 1.5 OPEN LOAD STATUS TIMING (with external pull-up) IOUT< IOL VOUT > VOL VINn 2.5 OVER TEMP STATUS TIMING Tj > TTSD VINn VSTATn VSTATn tSDL tDOL(off) tSDL tDOL(on) 4/18 2 1 VND830LSP Switching time Waveforms VOUTn 90% 80% dVOUT/dt(off) dVOUT/dt(on) 10% t VINn td(on) td(off) t TRUTH TABLE CONDITIONS Normal Operation Current Limitation Overtemperature Undervoltage Overvoltage Output Voltage > VOL Output Current < IOL INPUT L H L H H L H L H L H L H L H OUTPUT L H L X X L L L L L L H H L H STATUS H H H (Tj < TTSD) H (Tj > TTSD) L H L X X H H L H H L 5/18 1 VND830LSP ELECTRICAL TRANSIENT REQUIREMENTS ON VCC PIN ISO T/R 7637/1 Test Pulse I II TEST LEVELS III IV 1 2 3a 3b 4 5 -25 V +25 V -25 V +25 V -4 V +26.5 V -50 V +50 V -50 V +50 V -5 V +46.5 V -75 V +75 V -100 V +75 V -6 V +66.5 V -100 V +100 V -150 V +100 V -7 V +86.5 V ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 CLASS C E 6/18 I C C C C C C TEST LEVELS RESULTS II III C C C C C C C C C C E E Delays and Impedance 2 ms 10 Ω 0.2 ms 10 Ω 0.1 µs 50 Ω 0.1 µs 50 Ω 100 ms, 0.01 Ω 400 ms, 2 Ω IV C C C C C E CONTENTS All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device. VND830LSP Figure 1: Waveforms NORMAL OPERATION INPUTn OUTPUT VOLTAGEn STATUSn UNDERVOLTAGE VUSDhyst VCC VUSD INPUTn OUTPUT VOLTAGEn STATUSn undefined OVERVOLTAGE VCC<VOV VCC>VOV VCC INPUTn OUTPUT VOLTAGEn STATUSn OPEN LOAD with external pull-up INPUTn VOUT>VOL OUTPUT VOLTAGEn VOL STATUSn OPEN LOAD without external pull-up INPUTn OUTPUT VOLTAGEn STATUSn OVERTEMPERATURE Tj TTSD TR INPUTn OUTPUT CURRENTn STATUSn 7/18 1 VND830LSP APPLICATION SCHEMATIC +5V +5V +5V VCC Rprot STATUS1 Dld µC Rprot INPUT1 OUTPUT1 Rprot STATUS2 Rprot INPUT2 OUTPUT2 GND RGND VGND GND PROTECTION REVERSE BATTERY NETWORK AGAINST Solution 1: Resistor in the ground line (RGND only). This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1) RGND ≤ 600mV / IS(on)max. 2) RGND ≥ (−VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device’s datasheet. Power Dissipation in RGND (when VCC<0: during reverse battery situations) is: PD= (-VCC)2/RGND This resistor can be shared amongst several different HSD. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not common with the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary DGND depending on how many devices are ON in the case of several high side drivers sharing the same RGND. If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the ST suggests to utilize Solution 2 (see below). Solution 2: A diode (DGND) in the ground line. A resistor (RGND=1kΩ) should be inserted in parallel to DGND if the device will be driving an inductive load. This small signal diode can be safely shared amongst several different HSD. Also in this case, the presence of the ground network will produce a shift (j600mV) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. LOAD DUMP PROTECTION Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds VCC max DC rating. The same applies if the device will be subject to transients on the VCC line that are greater than the ones shown in the ISO T/R 7637/1 table. 8/18 1 1 VND830LSP µC I/Os PROTECTION: supply the microprocessor. The external resistor has to be selected according to the following requirements: 1) no false open load indication when load is connected: in this case we have to avoid VOUT to be higher than VOlmin; this results in the following condition VOUT=(VPU/(RL+RPU))RL<VOlmin. 2) no misdetection when load is disconnected: in this case the VOUT has to be higher than VOLmax; this results in the following condition RPU<(VPU–VOLmax)/ IL(off2). Because Is(OFF) may significantly increase if Vout is pulled high (up to several mA), the pull-up resistor RPU should be connected to a supply that is switched OFF when the module is in standby. If a ground protection network is used and negative transient are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the µC I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of µC and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC I/Os. -VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= - 100V and I latchup ≥ 20mA; VOHµC ≥ 4.5V 5kΩ ≤ Rprot ≤ 65kΩ. Recommended Rprot value is 10kΩ. OPEN LOAD DETECTION IN OFF STATE Off state open load detection requires an external pull-up resistor (RPU) connected between OUTPUT pin and a positive supply voltage (VPU) like the +5V line used to The values of VOLmin, VOLmax and IL(off2) are available in the Electrical Characteristics section. Open Load detection in off state V batt. VPU VCC RPU INPUT DRIVER + LOGIC IL(off2) OUT + R STATUS VOL RL GROUND 9/18 VND830LSP High Level Input Current Off State Output Current Iih (µA) IL(off1) 6 1.35 1.2 5.25 Off State Vcc=13V Vin=Vout=0V 1.05 Vin=3.25V 4.5 0.9 3.75 0.75 3 0.6 2.25 0.45 1.5 0.3 0.75 0.15 0 0 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 75 100 125 150 175 Tc (ºC) Tc (ºC) Input Clamp Voltage Status Leakage Current Vicl (V) Ilstat (µA) 8 0.07 7.75 0.06 Iin=1mA Vstat=5V 7.5 0.05 7.25 0.04 7 0.03 6.75 0.02 6.5 0.01 6.25 6 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Tc (ºC) 100 125 150 175 Status Clamp Voltage Vstat (V) Vscl (V) 8 0.8 0.7 7.75 Istat=1.6mA Istat=1mA 0.6 7.5 0.5 7.25 0.4 7 0.3 6.75 0.2 6.5 0.1 6.25 0 6 -50 -25 0 25 50 75 Tc (ºC) 1 75 Tc (ºC) Status Low Output Voltage 10/18 50 100 125 150 175 -50 -25 0 25 50 75 Tc (ºC) 100 125 150 175 VND830LSP On State Resistance Vs Tcase On State Resistance Vs VCC Ron (mOhm) Ron (mOhm) 100 160 90 140 Iout=2A Vcc=13V 80 Iout=2A 120 70 100 60 50 Tc=150ºC 80 40 60 Tc=25ºC 30 40 Tc= -40ºC 20 20 10 0 0 -50 -25 0 25 50 75 100 125 150 175 0 5 10 15 Tc (ºC) 20 25 30 35 40 Vcc (V) Openload On State Detection Threshold Input High Level Iol (A) Vih (V) 2 4 3.8 1.75 Vin=5V 3.6 1.5 3.4 1.25 3.2 1 3 2.8 0.75 2.6 0.5 2.4 0.25 2.2 0 2 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Tc (ºC) 50 75 100 125 150 175 100 125 150 175 Tc (ºC) Input Low Level Input Hysteresis Voltage Vil (V) Vihyst (V) 2.25 1.4 2.125 1.3 1.2 2 1.1 1.875 1 1.75 0.9 1.625 0.8 1.5 0.7 1.375 0.6 1.25 0.5 -50 -25 0 25 50 75 Tc (ºC) 100 125 150 175 -50 -25 0 25 50 75 Tc (ºC) 11/18 1 VND830LSP Overvoltage Shutdown Openload Off State Voltage Detection Threshold Vov Vol (V) 50 5 4.5 47.5 Vin=0V 4 45 3.5 42.5 3 40 2.5 2 37.5 1.5 35 1 32.5 0.5 30 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Tc (ºC) 100 125 150 175 Turn-off Voltage Slope dVout/dt(on) (V/ms) dVout/dt(off) (V/ms) 800 800 700 700 Vcc=13V Rl=6.5Ohm 600 Vcc=13V Rl=6.5Ohm 600 500 500 400 400 300 300 200 200 100 100 0 0 -50 -25 0 25 50 75 100 125 150 175 Tc (ºC) Ilim (A) 35 32.5 Vcc=13V 30 27.5 25 22.5 20 17.5 15 12.5 10 -50 -25 0 25 50 -50 -25 0 25 50 75 Tc (ºC) ILIM Vs Tcase 75 Tc (ºC) 1 75 Tc (ºC) Turn-on Voltage Slope 12/18 50 100 125 150 175 100 125 150 175 VND830LSP Maximum turn off current versus load inductance ILMAX (A) 100 10 A B C 1 0.01 0.1 1 L(mH ) 10 100 A = Single Pulse at TJstart=150ºC B= Repetitive pulse at TJstart=100ºC C= Repetitive Pulse at TJstart=125ºC Conditions: VCC=13.5V Values are generated with RL=0Ω In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C. VIN, IL Demagnetization Demagnetization Demagnetization t 13/18 1 VND830LSP PowerSO-10™ THERMAL DATA PowerSO-10™ PC Board Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm, Cu thickness=35µm, Copper areas: from minimum pad lay-out to 8cm2). Rthj-amb Vs PCB copper area in open box free air condition RTHj_amb (°C/W) 55 Tj-Tamb=50°C 50 45 40 35 30 0 2 4 6 PCB Cu heatsink area (cm^2) 14/18 8 10 VND830LSP PowerSO-10 Thermal Impedance Junction Ambient Single Pulse ZTH (°C/W) 1000 100 0.5 cm2 6 cm2 10 1 0.1 0.0001 0.001 0.01 0.1 1 Time (s) Thermal fitting model of a double channel HSD in PowerSO-10 10 100 1000 Pulse calculation formula Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ ) where δ = tp ⁄ T Thermal Parameter Tj_1 C1 C2 C3 C4 C5 C6 R1 R2 R3 R4 R5 R6 Pd1 Tj_2 C1 C2 R1 R2 Pd2 T_amb Area/island (cm2) R1 (°C/W) R2 (°C/W) R3( °C/W) R4 (°C/W) R5 (°C/W) R6 (°C/W) C1 (W.s/°C) C2 (W.s/°C) C3 (W.s/°C) C4 (W.s/°C) C5 (W.s/°C) C6 (W.s/°C) 0.5 0.15 0.8 0.7 0.8 12 37 0.0006 2.10E-03 0.013 0.3 0.75 3 6 22 5 15/18 VND830LSP PowerSO-10™ MECHANICAL DATA mm. DIM. MIN. A A (*) A1 B B (*) C C (*) D D1 E E2 E2 (*) E4 E4 (*) e F F (*) H H (*) h L L (*) α α (*) inch TYP 3.35 3.4 0.00 0.40 0.37 0.35 0.23 9.40 7.40 9.30 7.20 7.30 5.90 5.90 MAX. MIN. 3.65 3.6 0.10 0.60 0.53 0.55 0.32 9.60 7.60 9.50 7.60 7.50 6.10 6.30 0.132 0.134 0.000 0.016 0.014 0.013 0.009 0.370 0.291 0.366 0.283 0.287 0.232 0.232 1.35 1.40 14.40 14.35 0.049 0.047 0.543 0.545 1.80 1.10 8º 8º 0.047 0.031 0º 2º 1.27 TYP. MAX. 0.144 0.142 0.004 0.024 0.021 0.022 0.0126 0.378 0.300 0.374 300 0.295 0.240 0.248 0.050 1.25 1.20 13.80 13.85 0.50 0.053 0.055 0.567 0.565 0.002 1.20 0.80 0º 2º 0.070 0.043 8º 8º (*) Muar only POA P013P B 0.10 A B 10 H E E E2 1 SEATING PLANE e B DETAIL "A" A C 0.25 h E4 D = D1 = = = SEATING PLANE A F A1 A1 L DETAIL "A" α P095A 16/18 1 VND830LSP PowerSO-10™ SUGGESTED PAD LAYOUT TUBE SHIPMENT (no suffix) 14.6 - 14.9 CASABLANCA B 10.8- 11 MUAR C 6.30 C A A 0.67 - 0.73 10 9 1 9.5 2 3 B 0.54 - 0.6 All dimensions are in mm. 8 7 4 5 1.27 Base Q.ty Bulk Q.ty Tube length (± 0.5) 6 Casablanca Muar 50 50 1000 1000 532 532 A B C (± 0.1) 10.4 16.4 4.9 17.2 0.8 0.8 TAPE AND REEL SHIPMENT (suffix “13TR”) REEL DIMENSIONS Base Q.ty Bulk Q.ty A (max) B (min) C (± 0.2) F G (+ 2 / -0) N (min) T (max) 600 600 330 1.5 13 20.2 24.4 60 30.4 All dimensions are in mm. TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 (± 0.1) P D (± 0.1/-0) D1 (min) F (± 0.05) K (max) P1 (± 0.1) All dimensions are in mm. 24 4 24 1.5 1.5 11.5 6.5 2 End Start Top No components Components No components cover tape 500mm min Empty components pockets saled with cover tape. 500mm min User direction of feed 17/18 1 VND830LSP Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics 2003 STMicroelectronics - Printed in ITALY- All Rights Reserved. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 18/18 1