VP5313/VP5513 NTSC/PAL Digital Video Encoder Supersedes DS4509 1.9 September 1997 edition The VP5313/VP5513 converts digital Y Cr Cb data into analog PAL or NTSC composite video, and also provides simultaneous RGB outputs. These additional converters can optionally provide separate luma and chroma outputs plus a further composite video channel. All outputs are capable of driving doubly terminated 75Ω loads with standard video levels. All D/A converters are to 9 bit accuracy, and are provided with 27MHz oversampled data. The latter simplifies the requirement for external analog anti-aliasing filters, and reduces the sinx/x distortion inherent in D/A converters. Separate digital scaling is applied to the chroma data path in order to make the most efficient use of the 9 bit dynamic range. The device accepts data inputs complying with CCIR recommendation 656. In this format 4:2:2 video is multiplexed onto an 8 bit bus using a 27MHz clock. Active video markers are embedded into the data stream and extracted by the VP5313/VP5513. Optionally the user can supply separate horizontal and vertical syncs, and colour can be genlocked to an external subcarrier if necessary. In an alternative operating mode the VP5313/VP5513 can be configured as the source of sync for the rest of the system. In this master mode the horizontal and vertical sync pins become outputs, and any control codes in the CCIR656 bit stream are ignored. The VP5313/VP5513 supports the insertion of teletext data through a serial interface. An internal filter shapes the data edges. FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Converts Y, Cr, Cb data to analog RGB and composite or S-video and composite video Supports CCIR recommendations 601 and 656 All digital video encoding Selectable master/slave mode for sync signals Switchable chrominance bandwidth CCIR 624 PAL SMPTE or 170M NTSC compatible outputs GENLOCK mode I2C bus serial microprocessor interface Only VP5313 supports Macrovision anti-taping Rev. 7.01 Line 21 Closed Caption encoding Teletext insertion, fully line programmable DS4509 - 2.2 October 1998 33 34 22 44 12 1 Digital Cable TV Digital Satellite TV Multi-media Video games Digital VCRs Karaoke 11 GP44 Fig.1 Pin connections (top view) PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 FUNCTION VDD PD5 PD6 PD7 CLAMP COMPSYNC PALID SCSYNC REFSQ GND VDD FC2 FC1 FC0 HSYNC VSYNC TTXREQ SA TTXDATA VDD GND RESET APPLICATIONS ■ ■ ■ ■ ■ ■ 23 ORDERING INFORMATION VP5313A/CG/GP1N VP5513A/CG/GP1N PIN 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 FUNCTION SCL SDA DACCOMP RED/C GREEN/Y AVDD AGND AVDD BLUE/CVBS2 CVBS1 VREF RREF AGND AGND AVDD PD0 PD1 PD2 PD3 PD4 GND PXCK VP5313/VP5513 RECOMMENDED OPERATING CONDITIONS Parameter Symbol Power supply voltage Power supply current (including analog outputs)1 Power supply current (including analog outputs)2 Input clock frequency SCL clock frequency Analog video output load DAC gain resistor Ambient operating temperature 1. 2. Min. VDD, AVDD 4.75 IDD IDD PXCK -50ppm fSCL 0 Typ. Max. 5.25 230 190 27.00 +50ppm 500 37.5 730 70 5.00 Units V mA mA MHz kHz Ω Ω °C All four DACs driving 37R5 loads All four DACs driving 75R loads ELECTRICAL CHARACTERISTICS Test conditions (unless otherwise stated): As specified in Recommended Operating Conditions DC CHARACTERISTICS Parameter Conditions Symbol Min. Input high voltage Input low voltage VIN VIL 2.0 Digital Inputs SDA, SCL Input high voltage VIH 0.7VDD Input low voltage Input high current VIL IIH Typ. Max. Units Digital Inputs TTL compatible (except SDA, SCL) VIN = VDD VIN = VSS Input low current Digital Outputs CMOS compatible Output high voltage Output low voltage Digital Output SDA Output low voltage IIL IOL = +4mA VOH VOL IOL = +6mA VOL IOH = -1mA V 0.8 V 0.3VDD V V 10 -10 µA µA 3.7 V 0.4 V 0.6 V Max. Units ±1.5 ±1 ±5 LSB LSB % DC CHARACTERISTICS DACs Parameter Symbol Accuracy (each DAC) Integral linearity error Diffential linearity error DAC matching error Monotonicity LSB size Internal reference voltage Internal reference voltage output impedance Reference Current (VREF/RREF) RREF = 730Ω Maximum output Peak Glitch Energy (see fig.3) ABSOLUTE MAXIMUM RATINGS Supply voltage VDD, AVDD Voltage on any non power pin Ambient operating temperature Storage temperature -0·3 to 7·0V -0·3 to VDD+0·3V 0 to 70°C -55°C to 150°C Min. Typ. INL DNL guaranteed VREF ZR IREF 0.95 66.83 1.00 8k 1.3899 34.15 50 1.05 µA V Ω mA mA pV-s Note: Stresses exceeding these listed under Absolute Maximum Ratings may induce failure. Exposure to Absolute Maximum Ratings for extended periods may reduce reliability. Functionality at or above these conditions is not implied. 2 VP5313/VP5513 ESD COMPLIANCE Pins Test All pins Human body model 2kV on 100pF through 1k5Ω All pins Machine model 200V on 200pF through 0Ω & 500nH Test Levels Notes Meets Mil-Std-883 Class 2 DC CHARACTERISTICS DACs Parameter Symbol Min. Typ. Max. Units RGB outputs: Peak level Black level 19.98 1.337 mA mA CVBS1, 2 Y and C outputs - NTSC (pedestal enabled) Maximum output, relative to sync bottom White level relative to black level Black level relative to blank level Blank level relative to sync level Colour burst peak - peak DC offset (bottom of sync) 33.75 17.63 1.40 7.61 7.61 0.40 mA mA mA mA mA mA CVBS1, 2, Y and C outputs - PAL White level relative to black level Black level relative to sync level Colour burst peak - peak DC offset (bottom of sync) 18.70 8.01 8.01 0.00 mA mA mA mA All figures are for: RREF = 730Ω; if RL = 75Ω then RREF = 1460Ω VIDEO CHARACTERISTICS (NTSC, PAL COMPOSITE VIDEO) Parameter Luminance bandwidth Chrominance bandwidth (Extended B/w mode) Chrominance bandwidth (Reduced B/w mode) Burst frequency (NTSC) Burst frequency (PAL-B, D,G,H,I) Burst frequency (PAL-N Argentina) Burst cycles (NTSC and PAL-N) Burst cycles ( PAL-B, D, G, H,I) Burst envelope rise / fall time (NTSC ) Burst envelope rise / fall time (PAL-B, D, G, H, I, N) Analog video sync rise / fall time (NTSC) Analog video sync rise / fall time (PAL-B, D, G, H,I) Analog video blank rise / fall time (NTSC ) Analog video blank rise / fall time (PAL-B, D, G, H,I) Differential gain Differential phase Signal to noise ratio (unmodulated ramp) Chroma AM signal to noise ratio (100% red field) Chroma PM signal to noise ratio (100% red field) Hue accuracy Colour saturation accuracy Residual sub carrier Luminance / chrominance delay Symbol Min. Typ. Max. 5.5 1.3 650 3.57954545 4.43361875 3.58205625 9 10 300 300 145 245 145 245 -60 5 1 1 -61 -56 -58 2.5 2.5 Units MHz MHz kHz MHz MHz MHz Fsc cycles Fsc cycles ns ns ns ns ns ns % pk-pk ° pk-pk dB dB dB % % dB ns 10 3 VP5313/VP5513 PIN DESCRIPTIONS Pin Name Pin No. Description PD0-7 2-4, 38-42 PXCK 44 27MHz Pixel Clock input. The VP5313/VP5513 internally divides PXCK by two to provide the pixel clock. SA 18 Slave address select. SCL 23 Standard I2C bus serial clock input. SDA 24 Standard I2C bus serial data input/output. FC0-2 12-14 8 Bit Pixel Data inputs clocked by PXCK. PD0 is the least significant bit. These pins are internally pulled low. Field Counter output in master sync mode. REFSQ 9 Reference square wave input used only during Genlock mode. SCSYNC 8 Subcarrier sync input, (synchronises phase quadrant in 4xfsc genlock mode), see fig 6. PALID 7 PAL IDENT input, controls swinging colour burst phase in PAL genlock mode. COMPSYNC 6 Composite sync pulse output. This is an active low output signal. CLAMP 5 The CLAMP output signal is synchronised to COMPSYNC output and indicates the position of the BURST pulse, (lines 10-263 and 273-525 for NTSC; lines 6-310 and 319-623 for PALB,D,G,I,N(Argentina)). TTXREQ 17 Teletext Data Request output, requests next line of teletext data. TTXDATA 19 Teletext Data input. HSYNC 15 Horizontal Sync, output in master mode, input in slave mode VSYNC 16 Vertical Sync, output in master mode, input in slave mode RESET 22 Master reset. This is an asynchronous, active low, input signal and must be asserted for a minimum 200ns in order to reset the VP5313/VP5513. VREF 33 Voltage reference output. This output is nominally 1·0V and should be decoupled with a 100nF capacitor to GND. RREF 34 DAC full scale current control. A resistor connected between this pin and GND sets the magnitude of the video output current. An internal loop amplifier controls a reference current flowing through this resistor so that the voltage across it is equal to the Vref voltage. This reference current has a weighting equal to 20.8 LSB’s. DACCOMP 25 DAC compensation. A 100nF ceramic capacitor must be connected to AVDD. CVBS1 32 Composite video output. These are high impedance current source outputs. A DC path to GND must exist from each of these pins. BLUE/CVBS2 31 Blue or composite DAC output. Output type as CVBS1. GREEN/Y 27 Green or luminance DAC output. Output type as CVBS1. RED/C 26 Red or chrominance DAC output. Output type as CVBS1. VDD 1, 11, 20 Positive supply input. All VDD pins must be connected. AVDD 37,28,30 Analog positive supply input. All AVDD pins must be connected. GND 10,21,43 Negative supply input. All GND pins must be connected. AGND 36,29,35 Analog negative supply input. All AGND pins must be connected. 4 VP5313/VP5513 SDA SCL SA SET-UP REGISTERS I2C INTERFACE ANTI-TAPING CONTROL CLOSED CAPTION RESETB TTXDATA TELETEXT CONTROL TTXREQ TELETEXT SHAPING FILTER YCrCb to RGB YCrCb B/CVBS2 PD7-0 INPUT DEMUX YUV INTERPOLATING FILTERS Y UV + R/C + 9 BIT DAC SYNC INSERT PXCK HSYNC VSYNC FC0-2 9 BIT DAC MUX YCrCb 8 VIDEO TIMING GENERATOR CVBS1 9 BIT DAC MODULATOR DAC REF 3 COMPSYNC CLAMP REFSQ SCSYNC PALID DIGITAL PHASE COMP G/Y 9 BIT DAC COLOUR SUBCARRIER GENERATOR RREF VREF DACCOMP Figure 2 Functional block diagram V W H Peak Glitch Area = H x W/2 T(ps) The glitch energy is calculated by measuring the area under the voltage time curve for any LSB step, typically specified in picoVolt-seconds (pV-s) Figure 3 Glitch Energy (see Peak Glitch Energy in table on page 2) 5 VP5313/VP5513 REGISTERS MAP See Register Details for further explanations. ADDRESS REGISTER NAME hex 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13-1F 20-33 34-3F 40 41 42 43 44 45 46 47 48-4F 50 51 52 53 54 55-5F 60 61 62-FD FE-FF BAR PART ID2 PART ID1 PART ID0 REV ID MODE GCR VOCR RSTCTL SC_ADJ FREQ2 FREQ1 FREQ0 SCHPHM SCHPHL HSOFFL HSOFFM SLAVE1 SLAVE2 TSTPAT Not used Reserved Not used TTXLO2 TTXLO1 TTXLO0 TTXLE2 TTXLE1 TTXLE0 TTXDD TTXCTL Not used CCREG1 CCREG2 CCREG3 CCREG4 CC_CTL Not used IICEXCTL IICEXW/R Not used Reserved 7 6 4 5 RA4 RA7 RA6 RA5 ID14 ID17 ID16 ID15 ID0C ID0F ID0E ID0D ID04 ID07 ID06 ID05 REV4 REV7 REV6 REV5 DACCFG FSC4SEL GENDITH GENLKEN NOLOCK DITHEN CHRMCLIP CHRBW SYNCDIS 3 2 RA3 RA2 ID13 ID12 ID0B ID0A ID03 ID02 REV3 REV2 VFS1 VFS0 PALIDEN YCDELAY BURDIS LUMDIS 1 0 R/W DEFAULT hex W R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 00 53 13 01 00 00 20 00 9C A8 26 2B 00 00 7E 00 00 00 00 SC7 FR17 FR0F FR07 SCH7 HSOFF7 NCORSTD HCNT7 - SC6 FR16 FR0E FR06 SCH6 HSOFF6 VBITDIS HCNT6 - SC5 FR15 FR0D FR05 SCH5 HSOFF5 VSMODE HCNT5 - SC4 FR14 FR0C FR04 SCH4 HSOFF4 F_SWAP HCNT4 - SC3 FR13 FR0B FR03 SCH3 HSOFF3 SL_HS1 HCNT3 - SC2 FR12 FR0A FR02 SCH2 HSOFF2 SL_HS0 HCNT2 - RA0 RA1 ID10 ID11 ID08 ID09 ID00 ID01 REV0 REV1 SYNCM0 SYNCM1 CLMPDIS CVBSCLMP PEDEN CHRDIS TSURST SC0 SC1 FR10 FR11 FR08 FR09 FR00 FR01 SCH8 SCH0 SCH1 HSOFF0 HSOFF1 HSOFF8 HSOFF9 HCNT8 HCNT9 HCNT0 HCNT1 RAMPEN TTXPAT L14 L22 L327 L335 TTXDD7 L13 L21 L326 L334 TTXDD6 L12 L20 L325 L333 TTXDD5 L11 L19 L324 L332 TTXDD4 L10 L18 L323 L331 TTXDD3 L9 L17 L322 L330 TTXDD2 L8 L16 L319 L321 L329 TTXDD1 L6 L7 L15 L318 L320 L328 TTXDD0 TTXEN R/W R/W R/W R/W R/W R/W R/W R/W 00 00 00 00 00 00 01 00 - F1W1D6 F1W2D6 F2W1D6 F2W2D6 - F1W1D5 F1W2D5 F2W1D5 F2W2D5 - F1W1D4 F1W2D4 F2W1D4 F2W2D4 - F1W1D3 F1W2D3 F2W1D3 F2W2D3 F2ST F1W1D2 F1W2D2 F2W1D2 F2W2D2 F1ST F1W1D1 F1W2D1 F2W1D1 F2W2D1 F2EN F1W1D3 F1W2D3 F2W1D3 F2W2D3 F1EN R/W R/W R/W R/W R/W XX XX XX XX 00 CTL7 W/RD7 CTL6 W/RD6 CTL5 W/RD5 CTL4 W/RD4 CTL3 W/RD3 CTL2 W/RD2 CTL1 W/RD1 CTL0 W/RD0 W R/W FF - Table.1 Register map 6 VP5313/VP5513 REGISTER DETAILS BAR RA7-0 Base register Register address PART ID 2-0 ID17-00 Part number Chip part ID number REV ID REV7-0 Revision number Chip revision ID number MODE DACCFG 0 1 Mode Control YCDELAY Add delay to luma channel 0 Luma to Chroma delay, 0ns 1 Luma to Chroma delay, 37ns CLAMPDIS CLAMP O/P select 0 CLAMP O/P enabled 1 CLAMP O/P disabled CVBSCLAMP Composite clamp enable VFS1 0 0 1 1 R,G,B & CVBS analog outputs Y,C, CVBS1 & CVBS2 analog outputs VFS0 0 1 0 1 SYNCM1 SYNCM0 0 0 0 1 1 0 1 1 GCR FSC4SEL Video Standard PAL-B,D,G,H,I,N(Arg.) NTSC Reserved Reserved Sync mode Slave, Rec. 656 Slave H & V I/P Master H & V O/P Reserved Global Control Input subcarrier frequency select 0 REFSQ I/P = Fsubcarrier SCSYNC I/P ignored 1 REFSQ I/P = 4 x Fsubcarrier When SCSYNC I/P is asserted the REFSQ I/P divide by 4 is reset GENDITH No dither added 1 Dither added Genlock enable control 0 Internal subcarrier generation 1 When high, enable Genlock to REFSQ NOLOCK Genlock status bit (read only) 0 Genlocked 1 Cannot lock to REFSQ. This bit is cleared by reading and set again if lock cannot be attained. PALIDEN CVBS Clamp disabled 1 Clamps CVBS output, to prevent out of range DAC codes. VOCR DITHEREN Video Output Control Luma dither enable 0 Normal operation 1 Luma dither enabled CHRMCLIP Chroma clipping select 0 No chroma clipping 1 Enable clipping of chroma data when luma is clipped CHRBW Chroma bandwidth select 0 ±650kHz 1 ±1·3MHz SYNCDIS Sync disable (in CVBS signal) 0 Normal operation 1 Sync disabled Genlock dither addition control 0 GENLKEN 0 (COMPSYNC O/P is not affected) BURDIS Chroma burst disable 0 Normal operation 1 Chroma burst disabled LUMDIS Luma input disable - force black level 0 Normal operation 1 Luma disabled CHRDIS Chroma input disable - force monochrome 0 Normal operation 1 Chroma disabled PAL Ident select 0 Normal operation, internal PAL switch is used. 1 Enables PALID input, a phase control an for PALID signal, (0 = +135°, 1 = -135°) PEDEN Pedestal (set-up) select Valid for NTSC 0 Pedestal disabled 1 7·5 IRE pedestal on lines 23-262 and 286-525 7 VP5313/VP5513 RSTCTL Reset Data Control TSTPAT Test Pattern Register TSURST Soft reset control TTX_PAT 0 Normal operation 0 Normal operation 1 Chip soft reset 1 Teletext test pattern enabled RAMPEN Modulated test ramp enable SC_ADJ SC7-0 FREQ2-0 FR17-00 SCHPHM-L SCH8-0 HSOFFL-M HSOFF9-0 Sub Carrier Adjust Sub carrier frequency seed value. Sub carrier frequency 24 bit Sub carrier frequency programmed via I2C bus. FREQ3 is the MSB. Sub carrier phase offset 9 bit Sub carrier phase relative to the 50% point of the leading edge of the horizontal part of composite sync. SCHPHM bit 0 is the MSB. Horizontal Sync Output Offset This is a 10 bit number which allows the user to offset the start of digital data input with reference to the pulse HS. SLAVE1-2 H & V Slave Mode Control NCORSTD NCO line reset disable NCO is always reset at end of 4(8) field sequence in NTSC(PAL) regardless of the value of this control bit 0 NCO is reset every line in NTSC mode 1 NCO line reset is disabled VBITDIS 0 Normal operation 1 Modulated test ramp enabled TTXLO2-0 L6-22 Teletext Odd Line Enable 1 = Teletext Enabled on that line number TTXLE2-0 L318-335 Teletext Even Line Enable 1 = Teletext Enabled on that line number TTXDD7-0 Teletext Request Pulse Position TTXCTL TTXEN Teletext Control Teletext enable 0 Teletext disabled 1 Teletext enabled CCREG1 F1W1D6-0 Closed Caption register 1 Field one (line 21), first data byte CCREG2 F1W2D6-0 Closed Caption register 2 Field one (line 21), second data byte CCREG3 F2W2D6-0 Closed Caption register 3 Field two (line 284), first data byte CCREG4 F2W2D6-0 Closed Caption register 4 Field two (line 284), second data byte CCCTL F1ST Closed Caption control register Field one (line 21) status bit Ignore REC656 V-bit select 0 REC656 V-bit will be decoded and the line blanked accordingly 1 REC656 V-bit will be ignored VSMODE Teletext test pattern enable Select type of Vsync input 0 New data has been loaded to CCREG1-2 0 Standard Vsync I/P 1 Data has been encoded 1 Field even/odd Vsync I/P F_SWAP Invert field detect decision 0 New data has been loaded to CCREG3-4 0 Standard relationship applies 1 Data has been encoded 1 Inverted relationship applies F2ST F1EN SL_HS(1:0) Field one (line 284) status bit Closed Caption field one (line 21) Internal Hsync delay control 0 Disabled 00 No internal delay 1 Enabled 01 1 x 27MHz cycle delay 10 2 x 27MHz cycle delay F2EN 11 3 x 27MHz cycle delay 0 Disabled 1 Enabled TSLAVE2 HCNT(9:0) - Internal H counter is reset to this value on falling edge of Hsync input. Closed Caption field one (line 284) 8 VP5313/VP5513 IICEXCTL CTL7-0 I2C Extension Control Each bit controls port direction 0 = output 1 = input IICEXR/W RD7-0 I2C Extension Control I2C bus read and write data from I2C extension port The V bit within REC656 defines the video blanking when in TRS slave mode. By setting VBITDIS in the SLAVE1 register this blanking can be overidden. When in MASTER mode the V bit is ignored; hence, if any lines are required to be blank, they must have no video signal input on them. I2C BUS CONTROL INTERFACE I2C bus address A6 A5 A4 A3 A2 A1 A0 0 0 0 1 1 0 SA R/ W X The serial microprocessor interface is via the bi-directional port consisting of a data (SDA) and a clock (SCL) line. It is compatible to the Philips I2C bus standard (Jan. 1992 publication number 9398 393 40011). The interface is a slave transmitter - receiver with a sub-address capability. All communication is controlled by the microprocessor. The SCL line is input only. The most significant bit (MSB) is sent first. Data must be stable during SCL high periods. A bus free state is indicated by both SDA and SCL lines being high. START of transmission is indicated by SDA being pulled low while SCL is high. The end of transmission, referred to as a STOP, is indicated by SDA going from low to high while SCL is high. The STOP state can be omitted if a repeated START is sent after the acknowledge bit. The reading device acknowledges each byte by pulling the SDA line low on the ninth clock pulse, after which the SDA line is released to allow the transmitting device access to the bus. The device address can be partially programmed by the setting of the pin SA. This allows the device to respond to one of two addresses, providing for system flexibility. The I2C bus address is seven bits long with the last bit indicating read/write for subsequent bytes. The first data byte sent after the device address, is the subaddress - BAR (base address register). The next byte will be written to the register addressed by BAR and subsequent bytes to the succeeding registers. The BAR maintains its data after a STOP signal. NTSC/PAL Video Standards Both NTSC (4-field, 525 lines) and PAL (8-field, 625 lines) video standards are supported by the VP5313/VP5513. All raster synchronisation, colour sub-carrier and burst characteristics are adapted to the standard selected. The VP5313/ VP5513 generates outputs which follow the requirements of SMPTE 170M and CCIR 624 for PAL signals. The device supports the following standards: PAL B, D, G, H, I, N (Argentina) (default state) and NTSC. Video Blanking The VP5313/VP5513 automatically performs standard composite video blanking. Lines 1-9, 264-272 inclusive, as well as the last half of line 263 are blanked in NTSC mode. In PAL mode, lines 1-5, 311-318, 624-625 inclusive, as well as the last half of line 623 are blanked. Interpolator The luminance and chrominance data is separately passed through interpolating filters to produce output sampling rates double that of the incoming pixel rate. This reduces the sinx/x distortion that is inherent in the digital to analog converters (DACs), and also simplifies the analog reconstruction filter requirements. Digital to Analog Converters The VP5313/VP5513 contains four 9 bit digital to analog converters which produce the analog video signals. The DACs use a current steering architecture in which bit currents are routed to one of two outputs; thus the DAC has true and complimentary outputs, however, only the true outputs are available on the pins. The use of identical current sources and current steering their outputs means that monoticity is guaranteed. An on-chip voltage reference of 1·00V (typ.) provides the necessary biasing; if required, this can be overridden by an external reference. The full-scale output currents of the DACs is set by an external 730Ω resistor between the RREF and AGND pins. An on-chip loop amplifier stabilises the full-scale output current against temperature and power supply variations. By digitally summing the luma and chroma outputs a composite output is generated. The analog outputs of the VP5313/VP5513 are capable of directly driving doubly terminated 75Ω co-axial cable. If it is required only to drive a single 75Ω load then the DACGAIN resistor is simply doubled. Luminance, Chrominance and Composite Video Outputs The Luminance video output drives a 37.5Ω load at 1·0V, sync tip to peak white. It contains only the luminance content of the image plus the composite sync pulses. In the NTSC mode, a set-up level offset is added during the active video portion of the raster. The Chrominance video output drives a 37.5Ω load at levels proportional in amplitude to the luma output (40 IRE pkpk burst). Burst is injected with the appropriate timing relative to the luma signal. Output sinx/x compensation filters are required on all video outputs, as shown in the typical application diagram, see fig. 11 & 12. RGB Video Outputs The RGB video outputs drive a 37.5Ω load at 0.7V blank to peak. Output sinx/x compensation filters are required on all video outputs, as shown in the typical application diagram, see fig. 11 & 12. Video Timing - Slave sync mode The VP5313/VP5513 has an internal timing generator which produces video timing signals appropriate to the mode of operation. TRS slave mode means that the video encoder synchronises itself to the TRS (Timing Reference Signal) codes that are embedded into the Rec. 656 data pattern. In the 9 VP5313/VP5513 default (power up) the TRS slave mode is selected. All internal timing signals are derived from the input clock, (PXCK) this must be derived from a crystal controlled oscillator. Input pixel data is latched on the rising edge of the PXCK clock. The video timing generator produces the internal blanking and burst gate pulses, together with the composite sync output signal. H&V slave mode is enabled by setting the SYNCM1-0 bits in the MODE register to 01. In this mode the position of the video syncs is derived from the HS and VS inputs. These HS and VS pins are automatically configured as inputs. Video Timing - Master sync mode When SYNCM1-0 of the MODE register are 10, the VP5313/VP5513 operates in a MASTER sync mode, all REC656 timing reference codes are ignored with VS, HS and FC0-2 outputs providing synchronisation signals to an external (MPEG) device. The PXCK signal is, however, still used to generate all internal clocks. In master mode the direction setting of bits 4 - 0 of the IICEXCTL register are ignored. VS is the start of the field sync datum in the middle of the equalisation pulses. HS is the line sync which is used by the preceding MPEG2 decoder to define when to output digital video data to the VP5313/VP5513. The position of the falling edge of HS relative to the first data Cb0, can be programmed in HSOFFM-L registers, see figure 5. Genlock using REFSQ input The VP5313/VP5513 can be Genlocked to another video source by setting GENLKEN high (in GCR register) and feeding a phase coherent sub carrier frequency signal into REFSQ. Under normal circumstances, REFSQ will be the same frequency as the sub carrier; however if FSC4SEL is set high (in GCR register), a 4 x sub carrier frequency signal may be input to REFSQ. In this case, the Genlock circuit can be reset to the required phase of REFSQ, by supplying a pulse to SCSYNC. The frequency of SCSYNC can be at the sub carrier frequency, once per line or once per field could be adequate, depending on the application. When GENLKEN is set high, the direction setting of bit 5 of the IICEXCTL register is ignored. PALID input When using PAL and Genlock mode; the VP5313/VP5513 requires a PAL phase identification signal, to define the correct phase on every line. This is supplied to PALID input, High = -135° and low = +135°. The signal is asynchronous, and should by changed before the sub carrier burst signal. PALID input is enabled by setting PALIDEN high (in GCR register). When PALIDEN is set high, the direction setting of bit 7 of the IICEXCTL register is ignored. Line 21 coding Two bytes of data are coded on the line 21 of each field, see figure 8. In the NTSC Closed Caption service, the default state is to code on line 21 of field one only. An additional service can also be provided using line 21 (284) of the second field. The data is coded as NRZ with odd parity, after a clock run-in and framing code. The clock run-in frequency = 0.5034965MHz which is related to the nominal line period, D = H / 32. D = 63.55555556 / 32µs Two data bytes per field are loaded via I2C bus registers CCREG1-4. Each field can be independently enabled by programming the enable bits in the control register (CC_CTL). The data is cleared to zero in the Closed Caption shift registers after it has been encoded by the VP5313/VP5513. Two status bit are provided (in CC_CTL), which are set high when data is written to the registers and set low when the data has been encoded on the Luma signal. The data is cleared to zero in the Closed Caption shift registers after it has been encoded by the VP5313/VP5513. The next data bytes must be written to the registers when the status bit goes high, otherwise the Closed Caption data output will contain Null characters. If a transmission slot is missed (ie. no data received) the encoder will send Null characters. Null characters are invisible to a closed caption reciever. The MSB (bit 7) is the parity bit and is automatically added by the encoder. Teletext The Teletext function within the VP5313/VP5513 coordinates the insertion of teletext serial data into the luminance data stream and subsequently the composite video data stream. The serial data is filtered prior to insertion to minimise the high frequency components and to reduce the jitter inherent in the digital data stream. The lines in which teletext data are inserted are individually programmable for both even and odd fields. The insertion of teletext data will only be enabled if the format of the composite video is configured to be PAL-B,G,H,I,N and the teletext enable bit TTXEN is asserted. For test purposes, the teletext function incorporates control logic to generate a serial clock cracker pattern in place of the normal teletext data. This test pattern is enabled when the TTX_PAT bit is asserted. There is no row coding used so it will not display on a TV. The VP5313/VP5513 teletext interface comprises of a teletext request output, TTX_REQ, and a serial data input, TTX_DATA. To ensure that the composite video timing requirements are satisfied, the serial data must be received at a specific point in time during lines containing teletext data. The teletext request output, TTX_REQ, will be asserted to indicate when data must be applied to TTX_DATA, which must be generated synchronous to the rising edges of PXCK. The TTX_REQ may be advanced in multiples of PXCK, to compensate for the latency within the source device, by writing to the TTXDD register. The serial teletext data which is applied to the TTX_DATA input must obey the sequence defined below. The teletext bit rate is defined to be 6.9375 MHz, which equates to 444 times the PAL line frequency (15.625 kHz). It is clear that for a 27 MHz system clock, a constant bit period cannot be achieved. 10 VP5313/VP5513 have a duration of 3 CLK27M cycles. The sequence will be repeated for all subsequent 37 bit groups. The horizontal line duration for PAL equates to 1728 CLK27M cycles and within each line there are 444 data bit periods. The duration of 37 data bits (the smallest number possible for an integer number of CLK27M cycles) therefore equates to 144 CLK27M cycles. Master Reset The VP5313/VP5513 must be initialised with RESET. This is an asynchronous, active low signal and must be active for a minimum of 200ns in order to reset the VP5313/VP5513. The device resets to line 64, start of horizontal sync (i.e. line blanking active). There is no on-chip power on reset circuitry. To ensure that the average bit rate is 6.9375 MHz, 33 in every 37 data bits will have a duration of 4 CLK27M cycles and 4 in every 37 data bits will have a duration of 3 CLK27M cycles. Of the first 37 data bits in each line, bits 10, 19, 28 and 37 will CVBS/Y textbit #: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 TTX_DATA 4 3 4 4 3 4 TTXDD TTX_REQ Figure 4 Teletext timing diagram NCO Adjustment NTSC PAL-B, G, H, I (d) Field field freq. HZ 59.94 525 50 625 PAL-N (Argentina) 625 Standard Lines/ 50 SC_ADJ Number of Horizontal Subcarrier fSC/fH register pixels/line freq. kHz. freq. kHz. hex at 27MHz fH fSC 15.734266 3.57954545 1716 (455/2) xx 15.625000 4.43361875 (1135/4+1/625) 1728 9C 15.625000 3.58205625 (917/4+1/625) 1728 57 FREQ2-0 registers hex 87 C1 F1 A8 26 2B 87 DA 51 Table.2 Line, field and subcarrier standards and register settings (d) = default xx = don’t care. The calculation of the FREQ register value is according to the following formula:FREQ = 226 x fSC/PXCK hex, where PXCK = 27.00MHz NTSC value is rounded UP from the decimal number. PAL-B, D, G, H, I and N (Argentina) are rounded DOWN. The SC_ADJ value is derived from the adjustment needed to be added after 8 fields to ensure accuracy of the Subcarrier frequency. Note the SC_ADJ value of 9C required for PAL-B, D, G, H, I. PXCK Input (27MHz) t SU; PD HS Nck=2 t HD; PD Nck=0 Cb0 Y0 Cr0 Y1 Cb1 Y2 Cr1 Y3 Pixel Data Input (PD[7,0]) Figure 5 REC 656 interface with HS output timing 11 VP5313/VP5513 2:1 mux REFSQ fSC 0 Divide by 4 Synchronous Counter 1 Input to Genlocking Block Q RESET FSC4_SEL SC_SYNC (register bit) 1/ f SC_SYNC t PWH; SC_SYNC REFSQ tSU; SC_SYNC t HD; SC_SYNC SC_SYNC Q Figure 6 REFSQ and SC_SYNC input timing Pixel Data Input (PD[7,0\) Sample Number 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 Y719 $FF $00 $00 $XY ANCILLARY DATA... EAV SEQUENCE t SU; PD t HD; PD t PWL; PXCK t PWH; PXCK PXCK Input (27MHz) t DUR; PAL_ID t SU; PAL_ID t HD; PAL_ID PAL_ID Stable Input (PAL_ID) Figure 7 PAL_ID input timing 12 VP5313/VP5513 TIMING INFORMATION Symbol Conditions Parameters Min. Units Max. 27.0 fPXCK Master clock frequency (PXCK input) Typ. MHz PXCK pulse width, HIGH tPWH; PXCK 10 ns PXCK pulse width, LOW tPWL; PXCK 14.5 ns PXCK rise time 10% to 90% points tRP TBD ns PXCK fall time 90% to 10% points tFP TBD ns PD7-0 set up time tSU;PD 10 ns PD7-0 hold time tHD;PD 5 ns SCSYNC set up time tSU;SC_SYNC 10 ns SCSYNC hold time tHD;SC_SYNC 0 ns PALID set up time tSU;PAL_ID 10 ns PALID hold time tHD;PAL_ID 0 ns PALID duration tDUR;PAL_ID 9 PXCK periods Output delay PXCK to COMPSYNC tDOS 25 ns PXCK to CLAMP Note: Timing reference points are at the 50% level. Digital CLOAD <40pF. H C B A 1 D START BITS CLOCK RUN-IN HSYNC COLOUR BURST 13 E DATA BYTE 1 DATA BYTE 2 50 P P 0 S1 -40 IRE S2 S3 BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7 BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7 0 1 0 0 0 0 1 1 FRAME CODE P = Parity Bit Figure 8 Closed Capation format 13 VP5313/VP5513 Interval Description Encoder minimum Encoder nominal Encoder maximum 10.500µs 10.750µs A H-sync to clock run-in B Clock run-in 2, 3 6.5D (12.910µs) C Clock run-in to third start bit 3 2.0D (3.972µs) D Data bit 1, 3 1.0D (1.986µs) 10.250µs characters 4 E Data H Horizontal line 1 16.0D (31.778µs) 32.0D (63.556) Rise / fall time of data bit transitions 5 0.240µs 0.288µs 48 IRE 50 IRE 52 IRE Data bit low (logic level zero) 6 Clock run-in minimum 0 IRE 0 IRE 2 IRE Data bit differential (high - low) Clock run-in differential (max. - min) 48 IRE 50 IRE 52 IRE Data bit high (logic level Clock run-in maximum one) 6 Table. 5 Closed Caption data timing. (source EIA R - 4.3 Sept 16 1992) Notes 1. The Horizontal line frequency fH is nominally 15734.26Hz ±0.05Hz. Interval D shall be adjusted to D = 1/(fH x 32) for the instantaneous fH at line 21. 2. The clock run-in signal consists of 7.0 cycles of a 0.5034965MHz (1/D) sine wave when measured from the leading to trailing 0 IRE points. The sine wave is to be symmetrical about the 25 IRE level. 3. The negative going midpoints (half amplitude) of the clock run-in shall be coherent with the midpoints (half amplitude) of the Start and Data bit transitions. 4. Two characters, each consisting of 7 data bits and 1 odd parity bit. 5. 2 T Bar, measured between the 10% and 90% amplitude points. 6. The clock run-in maximum level shall not differ from the data bit high level by more than ±1 IRE. The clock run-in minimum level shall not differ from the data bit low level by more than ±1 IRE. 14 VP5313/VP5513 Frequency Response Luma in RGB Path 0 2.5e+6 5e+6 0 2.5e+6 5e+6 7.5e+6 10e+6 12e+6 7.5e+6 10e+6 12e+6 0 M a g n i t u d e -20 -40 d B -60 Frequency in Hz Figure 9 Luma filter for RGB datapath Frequency Response of Cr and Cb in RGB Path 0 2.5e+6 5e+6 7.5e+6 10e+6 12e+6 0 2.5e+6 5e+6 7.5e+6 10e+6 12e+6 0 M a g n i t u d e d B -20 -40 -60 -80 Frequency in Hz Figure 10 Chroma filter for RGB datapath 15 VP5313/VP5513 FERRITE +5V BEAD VDD 10nF 2k2Ω I2C BUS SCL SDA SA DIGITAL VIDEO TELETEXT INTERFACE SYSTEM CLOCK RESET SYNC INTERFACE 8 GND 100µF 2k2Ω AT EVERY VDD PIN VDD, AVDD SCL G/Y SDA SA OUTPUT FILTER GREEN/LUMA B/CVBS2 OUTPUT FILTER BLUE/CVBS R/C OUTPUT FILTER RED/CHROMA CVBS1 OUTPUT FILTER CVBS PD0-7 TTXDATA TTXREQ PXCK RESET HS 100nF DAC COMP +5V 730Ω VS RREF VREF GND, AGND 100nF GND Figure 11 Typical application diagram. (Output filter - see Fig.12) to drive 37.5ohms 15pF 1.0µH 470pF 220pF 75Ω EXT 75Ω GND Figure 12 Output reconstruction filter 16 VP5313/VP5513 Note: The VP5313 is only available to customers with a valid and existing authorisation to purchase issued by MACROVISION CORPORATION. This device is protected by U.S. patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. Use of the Macrovision anticopy process in the device is licensed by Macrovision for non-commercial, home and limited exhibition uses only. Reverse engineering or disassembly is prohibited. 17 For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) is believed to be reliable. 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