VITESSE SEMICONDUCTOR CORPORATION Data Sheet Dual Repeater/Retimer for Fibre Channel and Gigabit Ethernet VSC7130 Features • Used in Switches, Hubs, GBICs, MIAs and JBODs • ANSI T11 Fibre Channel Compliant at 1.0625Gb/s • IEEE 802.3z Gigabit Ethernet Compliant at 1.25Gb/s • Dual Clock and Data Recovery Units Configurable as Repeaters or Retimers • Two-Wire Serial Communications Port for Control and Status • 1/10th or 1/20th Baud Rate TTL/PECL Reference Clock Input and PECL Output • Bidirectional Analog/Digital Signal Detect • 3.3V, 850mW Power Typical • 64-pin, 10x10x1.0mm TQFP Package • Cost Effective 0.35µm CMOS Technology • Combined Analog/Digital Signal Detect Units General Description The VSC7130 is used in Fibre Channel (1.0625Gb/s) and Gigabit Ethernet (1.25Gb/s) systems to provide bidirectional Clock and Data Recovery (CDR) to ensure standards compliance at critical systems interfaces. As protocol ASICs integrate multiple SerDes functions, the ASICs tend to be located far from interface connectors which results in signal degradation and difficulty in meeting industry-standard signal quality specifications. The VSC7130 provides a low-cost, easy-to-use solution to this problem by ensuring standards-compliant signal quality at system interfaces. Additional circuitry implements an FC-AL Hub node. The VSC7130 provides a pair of bidirectional CDRs which can be configured as either repeaters or retimers or bypassed altogether. Internal system data is recovered and retransmitted with standards-compliant signal quality at the connector. External receive data from the connector is recovered and retransmitted to the internal system with increased amplitude and attenuated jitter. An optional Two-Wire Interface allows robust configuration control and status monitoring of the device in order to enhance operation. VSC7130 Block Diagram MUX1SEL SI+ SI- SDU0 MUX4SEL 0 CDR0 MUX1 0 TX+ TX- MUX4 1 1 T/R TXDIS 1 0 MUX5 R1/0 MUX2SEL SO+ SO- 1 0 MUX5SEL 0 1 MUX3 CDR1 MUX2 0 BYP SDU1 REFO+ REFO- 53.125 or106.25MHz REFI+ REFI- CMU HALF/FULL x10/x20 CAP0 G52297-0, Rev 4.0 04/02/01 1 RX0+ RX0RX1+ RX1SDET 1.0625 GHz CAP1 NOT SHOWN: Two-Wire Interface, test, modes and RXBIAS Clock Frequencies shown for Fibre Channel © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 1 VITESSE SEMICONDUCTOR CORPORATION Data Sheet Dual Repeater/Retimer for Fibre Channel and Gigabit Ethernet VSC7130 Applications Several Fibre Channel and Gigabit Ethernet applications can use the VSC7130. Configuration changes between different applications are accomplished with mode pins and the Two-Wire Interface. SI+/- and SO+/are normally connected to the duplex interface from the system while TX+/- and RX0+/- or RX1+/- are connected to the external link through a connector or optical transceiver. Redundant receive inputs are provided in order to optimize layouts with copper connectors or optical modules. CDR0 improves the signal quality of SI and retransmits the data on TX. CDR1 improves signal quality of RX0 or RX1 and retransmits recovered data to SO. In this document, the term “Repeater” will be used for a clock and data recovery function (CDR) where the recovered serial data is retransmitted synchronously to the recovered clock. Unlike standard PLL-based CDRs, this circuit is all-digital which results in good jitter tolerance, excellent jitter transfer and low latency in a circuit which performs identically across process, voltage and temperature. The term “Retimer” is used for a CDR which retransmits the recovered serial data synchronously to the local reference clock. This complex CDR function eliminates jitter transfer at the expense of latency. Due to the potential mismatch between the baud rate of the incoming data and the local reference clock (i.e. +/-100ppm), an add/drop elasticity buffer is needed to insert/delete Ordered Sets to match this rate difference. The data which is added/dropped must meet Fibre Channel protocol specifications. By eliminating jitter transfer, standards compliance is ensured. The retimer function is not available for Gigabit Ethernet. Multi-Node Switch One application for the VSC7130 is in high port-count Fibre Channel and Gigabit Ethernet systems such as switches. Figure 1 shows a switch with a CMOS protocol ASIC with integrated Serializer/Deserializers located on the Switch Fabric card. Serial data from the protocol ASIC passes through multiple connectors and long traces on the PCB before reaching the connector. Without the VSC7130, the signal quality at the connectors would result in poor system performance. However, by using the VSC7130, signal quality is improved to meet the specifications of Fibre Channel and Gigabit Ethernet at the system interface connectors. Figure 1: Fibre Channel or Gigabit Ethernet Switch Port 1 Port N Connectors Protocol ASIC VSC7130 CDR0> <CDR1 Switch Fabric Card Backplane Page 2 Line Card © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com G52297-0, Rev 4.0 04/02/01 VITESSE SEMICONDUCTOR CORPORATION Data Sheet Dual Repeater/Retimer for Fibre Channel and Gigabit Ethernet VSC7130 Fibre Channel Hub The VSC7130 may be used as a single node in a Fibre Channel Arbitrated Loop Hub. In this application, incoming data on RX goes through a repeater (CDR1) which reduces jitter. The data is then output on SO to the next hub node. Incoming data from the previous hub node on SI goes through CDR0 which is configured as a retimer to eliminate any jitter generated inside the Hub. A bypass multiplexer (MUX3) is used to bypass nodes which do not have active devices connected. The signal detection circuitry identifies valid data at RX in order to control the configuration of MUX3. The BYP pin may be connected via an inverter to SDET, BYP may be controlled externally or MUX3 may be controlled via the Two-Wire Interface. Access to internal registers through the Two-Wire Interfaces allows numerous features requires by sophisticated managed Hubs such as Ordered Set Recognition, Ordered Set Generation and simple traffic monitoring. Figure 2: Fibre Channel Arbitrated Loop Hub External Device External Device External Device TX RX TX RX TX RX CDR0 Retimer CDR1 Repeater CDR0 Retimer CDR1 Repeater CDR0 Retimer CDR1 Repeater SO SI SO SI MUX3 Node N-1 SO SI MUX3 Node N MUX3 Node N+1 Internal Loop Optical/Electrical Transceiver (GBIC) As a dual repeater, the VSC7130 may provide the functions required on an Optical/Electrical transceiver such as an Optical or an a active copper Gigabit Interface Converter (GBIC). In this application, outgoing data from a system goes through CDR0 which can be configured as either a repeater or a retimer. Incoming data passing through repeater CDR1 is transferred to the system. This function implements the critical circuits in an active GBIC including RX_LOS. G52297-0, Rev 4.0 04/02/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 3 VITESSE SEMICONDUCTOR CORPORATION Data Sheet Dual Repeater/Retimer for Fibre Channel and Gigabit Ethernet VSC7130 Figure 3: Active Copper GBIC Module +TX_DAT -TX_DAT TX_DISABLE TX_FAULT +RX_DAT -RX_DAT RX_LOS SI+ SI- CDR0 Repeater TX+ TX- TX+ TX- CDR1 Repeater RX+ RX- RX+ RX- TXDIS SO+ SO- DB-9 or HSSDC GBIC CONNECTOR, 20-PIN SCA-2 VSC7130 SDET OSC MOD_DEF0 MOD_DEF1 MOD_DEF2 SERIAL EEPROM Functionality Note this datasheet does not completely describe the VSC7130. A companion document, the VSC7130 User’s Manual describes additional applications issues and goes into great depth regarding the Two-Wire Interface and internal register operation. Notation All I/O pin names are in bold. All register bit names are italicized. Differential signals can be identified individually, e.g., I0+ and I0-, or together, e.g., I0. Signals and circuits which are repeated are generically named using an ‘x’ to denote “any channel”, e.g., TXx for any Transmit pins. All registers are identified by underlining, e.g., CDRxC and the address for each referenced register will be listed immediately following the register name (i.e. CDRxC-20h). Clock Multiplier Unit and Reference Clock A reference clock is needed for the clock multiplier unit (CMU) in order to generate the internal baud rate clock. The VSC7130 is used for both Fibre Channel (1.0625Gb/s) and Gigabit Ethernet (1.25Gb/s) applications. The HALF/FULL signal indicates whether the reference clock is 1/20th of the baud rate (HIGH) or 1/10th of the baud rate (LOW). Table 1 indicates the valid combinations of the HALF/FULL signal and reference clock frequency. Combinations not listed in the table will result in abnormal functionality. Table 1: Reference Clock Frequency Selection HALF / FULL Pin Frequency (MHz) HIGH 53.125 LOW 106.25 HIGH 62.5 LOW 125.0 All Other Combinations Page 4 Application Fibre Channel @ 1.0625Gb/s Fibre Channel @ 1.0625Gb/s Gigabit Ethernet @ 1.25Gb/s Gigabit Ethernet @ 1.25 Gb/s Not Allowed. © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com G52297-0, Rev 4.0 04/02/01 VITESSE SEMICONDUCTOR CORPORATION Data Sheet Dual Repeater/Retimer for Fibre Channel and Gigabit Ethernet VSC7130 Implementing reference clock distribution in multi-node systems can be difficult and expensive if optimal signal quality is to be achieved. In order to reduce this burden, the VSC7130 has a flexible reference input buffer which can be either single-ended TTL, or differential PECL. If single-ended TTL, REFI+ should be connected to the clock source and REFI- should be left unconnected. REFI- is biased to VDD/2 for TTL thresholds. If a PECL source is used, connect the positive side to REFI+ and the negative side to REFI-. In order to provide the reference clock to multiple devices, a reference clock output, REFO+/-, is provided which is just a PECL buffered version of REFI+/-. In this way, multiple VSC7130s may be daisy chained together with the REFO driving the REFI of the next device. When REFO is driving REFI, a 100Ω resistor should be connected between REFI+ and REFI-. The reference clock is used by the clock multiplier unit (CMU) in order to generate the internal baud rate clock. In order to maximize signal quality of the TX and SO outputs, the REFI input should be of the highest quality possible with sharp edges and low jitter. Duty cycle distortion is not very important since only the rising edge of REFI is used. The CMU is a high performance analog PLL which multiplies the reference clock frequency by 20 or 10 depending on HALF/FULL. The on-chip PLL uses a single external 0.1µF capacitor, connected between CAP0 and CAP1, to control the Loop Filter. This capacitor should be a multilayer ceramic dielectric, or better, with at least a 5V working voltage rating and a good temperature coefficient, i.e. NPO is preferred but X7R is acceptable. These capacitors are used to minimize the impact of common mode noise on the CMU, especially power supply noise. Higher value capacitors provide better robustness in systems. NPO is preferred because if an X7R capacitor is used, the power supply noise sensitivity will vary with temperature. For best noise immunity, the designer may use a three capacitor circuit with one differential capacitor between CAP0 and CAP1, C1, a capacitor from CAP0 to ground, C2, and a capacitor from CAP1 to ground, C3. Larger values are better but 0.1µF is adequate. However, if the designer cannot use a three capacitor circuit, a single differential capacitor, C1, is adequate. These components should be isolated from noisy traces. Figure 4 is the recommended Loop filtering scheme. Separate power (VDDA) and ground (VSSA) are provided in order to allow a separately filtered power supply to reduce noise. Figure 5 is the recommended VDDA filtering scheme. Figure 4: Loop Filter Capacitors (Recommended Circuit) VSC7130 C1=C2=C3= >0.1µF MultiLayer Ceramic Surface Mount NPO (Preferred) or X7R 5V Working Voltage Rating C2 CAP0 C1 C3 CAP1 Figure 5: VDDA Filtering (Recommended Circuit) VDD VSC7130 VDDA L1 L1=Ferrite bead with C1 high impedance at high frequencies and some DC resistance (0.5Ω) G52297-0, Rev 4.0 04/02/01 C2 C3 C1=10-33µF C2=0.1µF C3=0.01µF-0.001µF VSSA © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 5 VITESSE SEMICONDUCTOR CORPORATION Data Sheet Dual Repeater/Retimer for Fibre Channel and Gigabit Ethernet VSC7130 Input and Output Buffers, Analog Signal Detection, Cable Equalization The RX0+/-, RX1+/- and SI+/- differential inputs are high performance input buffers which amplify the incoming signal. Furthermore, a cable equalization circuit is included in the input buffer which accentuates high frequency signals in order to compensate for the high frequency loss found in copper cables and traces. This cable equalization circuit enhances the ability of the VSC7130 to reliably receive serial inputs which have been degraded with jitter. The RX1+/- input buffer also includes an analog signal detection circuit which has adjustable thresholds set by the external RXBIAS pin (see Figure 9). The output of this signal is processed further in the Signal Detection circuitry described elsewhere, as well as selectable threshold levels which are selected with the RXBIAS input. If the Two-Wire Interface is not used, R1/0 directly controls the RX0 and RX1 input buffers and Cable Equalization is enabled in SI, RX0 and RX1. If the Two-Wire Interface is used, microcontroller control allows enabling or disabling of the cable equalization circuit. Please refer to the VSC7130 User’s Manual for a more complete description of the input and output buffer controls and cable equalization controls. High-Speed I/O Termination Schemes The high-speed I/O lines for the VSC7130 require the standard Vitesse 1Gb/s CMOS device termination schemes. Please refer to the Termination for 1Gb/s CMOS Devices Application Note (AN-54) for VSC7130 RX and TX termination schemes. When using the REFI+/- and REFO+/- pins on the VSC7130 in daisy-chained clock applications, specific termination must be implemented. If the REFO+/- pins of one VSC7130 are to be routed to the REFI+/- pins of a second VSC7130, 50Ω single-ended (100Ω differential) traces should be used. AC coupling caps should be placed between the two VSC7130s. Additionally, a 100Ω 1% termination resistor should be place between the REFI+ and REFI- lines of the second VSC7130. This termination resistor should be located as close to the REFI+/- pins as possible. Figure 6 shows the recommended termination and components when using the VSC7130’s REFI and REFO. Figure 6: REFI and REFO Recommended Termination 53.125 or 106.25MHz 22Ω Oscillator (TTL) X VSC7130 #1 REFI+ REFO+ REFI- REFO- 0.01µF 100Ω 1% VSC7130 #2 REFI+ REFO+ REFI- REFO- 50Ω 0.01µF 50Ω 1% 0.01µF 1% 0.01µF Page 6 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com G52297-0, Rev 4.0 04/02/01 VITESSE SEMICONDUCTOR CORPORATION Data Sheet Dual Repeater/Retimer for Fibre Channel and Gigabit Ethernet VSC7130 Clock and Data Recovery (CDR) Two Clock and Data Recovery Units (CDR) are included in the VSC7130 in order to improve signal quality of serial data by amplification and jitter attenuation. Figure 7 shows a block diagram of each CDR with its corresponding Signal Detect Unit (SDU). Table 2 shows how each CDR may be configured as either a repeater or a retimer using the MODE0, MODE1 and T/R pins or via the Two-Wire Interface by programming the MODEDIS, T/RDIS and ITRx register bits. Figure 7: CDRx/SDUx Block Diagram BYPx Serial In 1 (derived from MODE[1:0], T/R, MODEDIS, T/RDIS and and ITRx) Serial Out 0 SELRTx 1 D Q REPEATERx CLKO 0 UNDERx OVERx ADDx DROPx OSGENx OSGxSEL OSGENxA 0 OSGENxB 1 D Q RETIMERx Baud Rate Clock (from CMU) D Analog Signal Detect In (from input buffer) ASDDISx RLLDISx K28DISx KWINDx(5:0) SDUx D OSREC0A IDLEx ARBx OPENx CLSx LIPF7,F7x LIPF8,F7X LIPF7,Xx LIPF8,Xx LIPYXx LIPFFx NLIPF8x OSRxA OSREC0B OSRxB HUB Support G52297-0, Rev 4.0 04/02/01 SDx PSDx ASDx RLLx K28x © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 7 VITESSE SEMICONDUCTOR CORPORATION Data Sheet Dual Repeater/Retimer for Fibre Channel and Gigabit Ethernet VSC7130 Table 2: CDRx Repeater/Retimer Configuration MODE1 Pin MODE0 Pin 0 0 0 1 1 1 0 1 T/R Pin 0 CDR1 Repeater (SELRT1=1) CDR0 Repeater (SELRT0=1) 1 Repeater (SELRT1=1) Retimer (SELRT0=0) 0 Repeater (SELRT1=1) Repeater (SELRT0=1) 1 Repeater (SELRT1=1) Retimer (SELRT0=0) Bypass Bypass and power down n/a n/a Bypass Bypass and power down 0 Retimer (SELRT1=0) Repeater (SELRT0=1) 1 Retimer (SELRT1=0) Retimer (SELRT0=0) The SELRTx signal determines whether the repeater or retimer output is selected, as shown in Figure 4. The MODEDIS register bit (CHIPCA-01h, bit 7) and the T/RDIS register bit (CHIPCA-01h, bit 4) can be used to disable the pin controls defined in Table 2 for selecting repeater or retimer mode for each CDR unit. For CDR0, if the MODEDIS and T/RDIS bits are both set, the ITR0 register bit (CDR0C-20h, bit 4) will control the repeater/retimer selection. For CDR1, only the MODEDIS register bit needs to be set in order to use ITR1 (CDR1C-28h, bit 4) to control the repeater/retimer selection. A HIGH in ITRx selects repeater mode, and a LOW selects retimer mode. Normally, the SI input passes through MUX1 to the input of CDR0 whose output is transmitted on TX+/- if TXDIS is LOW. If TXDIS is HIGH, TX+ and TX- will be HIGH. Similarly, the RX input normally passes through MUX2, CDR1 and MUX3 to the SO output. Retimer Operation NOTE: Retimer operation is only used for Fibre Channel data at 1.0625Gb/s. Do not use Retimer mode unless the incoming data is Fibre Channel or follows the Ordered Set structure defined by Fibre Channel. Failure to do so will result in data corruption. When CDRx is configured as a Retimer, recovered data is resynchronized to an internally generated baud rate clock derived from the REFI. This prevents jitter at the inputs from transferring to the outputs. However, incoming data is not necessarily at the same frequency as the internal baud rate clock, so special Fibre Channel Ordered Sets, called Fill Words, are added or dropped from the data stream in order to accommodate this speed difference. The rules for adding and dropping Fill Words are delineated in documents generated by the T11 committee: FC-PH, FC-PH2, FC-PH3, FC-AL, FC-AL2 and FC-AL3. The VSC7130 is compliant with these rules. A detailed block diagram of the Retimer is shown in Figure 8. Incoming data goes into a CRU where the data is recovered and resampled. Recovered data and recovered clock are sent to the Add/Drop FIFO where the data is stored using the recovered clock. Data is removed from the Add/Drop FIFO and resynchronized by the Retransmitting Flip-Flop using the internally generated baud rate clock derived from REFI. The output of the Flip-Flop is recovered serial data which is synchronous to the low-jitter baud rate clock and complies with all jitter specifications for Fibre Channel. Page 8 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com G52297-0, Rev 4.0 04/02/01 VITESSE SEMICONDUCTOR CORPORATION Data Sheet Dual Repeater/Retimer for Fibre Channel and Gigabit Ethernet VSC7130 Figure 8: Retimer Block Diagram To RTMRxC Register UNDERx OVERx ADDx DROPx Clock Recovery Unit INPUT DATA D CLKI Retransmit Flip-Flop Q CLKO D Q CLKI CLK D Q OUTPUT DATA CLK ADD/DROP FIFO 1.0625GHz Internal Baud Rate Clock The internally generated baud rate clock (nominally 1.0625GHz) is used by the Retimer for several functions. First, it provides the timing reference for the CRU. Second, it clocks data out of the FIFO. Third, it retimes the retransmitted output data. The quality of the baud rate clock will impact the jitter tolerance of the Clock Recovery Unit and the jitter generation of the Retransmitter Flip-Flop. The signal quality of the internally generated baud rate clock is directly related to jitter on REFI and power supply noise. The user is encouraged to minimize both REFI jitter and power supply noise in order to maximize jitter tolerance at the input and minimize jitter generation at the output. In the Add/Drop FIFO, a phase detector monitors the phase difference between the recovered clock and the internally generated baud rate clock to determine when to add or drop Fill Words. Fill Words can only be added/ dropped between packets following the rules delineated by the Fibre Channel Specifications mentioned previously. The retimer has two outputs indicating whether it is adding (ADDx) or dropping (DROPx) ordered sets from the serial stream in order to perform rate matching between the incoming serial data and the local reference clock. The retimer also has an output (OVERx) indicating that an overrun condition has occurred when an order set which needed to be dropped was not able to be dropped. Similarly, underrun errors are reported when a Fill Word which needed to be added was not able to be added. Please refer to the VSC7130 User’s Manual for more information regarding retimer operation and associated register controls. Signal Detection Associated with each CDR is a Signal Detect Unit (SDU) which is used to determine if a valid Fibre Channel signal is present at the CDR. Each SDU employs three independent checks to qualify the signal as valid: K28.5- primitive detection, Run-Length-Limit (RLL) error detection and K28.5- density checking. In addition, when the RX1 input pair is selected for input (instead of RX0), SDU1 also uses the Analog Signal Detect (ASD) circuit associated with the RX1 input pair as an additional signal detect qualification. Signal Detect assertions and deassertions are triggered by different conditions observed by the VSC7130 on the incoming serial data signal. Signal Detect assertions are triggered only when two consecutive valid Fibre G52297-0, Rev 4.0 04/02/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 9 VITESSE SEMICONDUCTOR CORPORATION Data Sheet Dual Repeater/Retimer for Fibre Channel and Gigabit Ethernet VSC7130 Channel primitives containing K28.5- characters are received. Once Signal Detect is asserted, there are several conditions which can result in the deassertion of Signal Detect: (1) An RLL error (a violation of 8B/10B coding rules in which there are more than five consecutive zeros or ones in the data stream), (2) no K28.5- character seen for one density window time (defaults to apx. 77 microseconds, but can be modified using the Two-Wire Interface to write to the KWINDx-25h/2Dh register), or (3) an invalid signal level detected by the Analog Signal Detect circuit (only applies to SDU1 when the RX1 input is selected). The Analog Signal Detect circuit is used to ensure that the signal amplitude presented to the RX1 input pair is high enough to be considered valid. Analog transition detection is performed on the input to verify that the signal swings are of adequate amplitude. The RX1+/- input buffer contains a differential voltage comparator which has adjustable thresholds set by the external RXBIAS pin (see Figure 9). If the Two-Wire Interface is being used, the Analog Signal Detect check for SDU1 can also be disabled by setting the ASDDIS1 register bit (SDU1C-29h, bit). Figure 9 shows an approximation to the Analog Signal Detect thresholds which can be obtained with biasing resistors or another voltage reference source to the RXBIAS pin. Figure 9: VSC7130 RXBIAS Equations and Graph R1 x R2 3.3V VSC7130 < R1 + R2 ~ R1 RXBIAS Pin 46 RXBIAS R1 <_ R2 <_ 1kΩ 3.3V - VRXBIAS 150uA R2 VRXBIAS 50uA SDET Threshold Voltage (mV, pk-pk differential) 600 500 400 300 200 100 0.00 0.20 0.40 0.60 0.80 1.00 V RXBIAS /VDD Page 10 1. From the graph find the optimal SDET trip threshold for your system. It is recommended that the rising edge of the graph be used unless pulling RXBIAS to ground via a 1kΩ resistor. 2. From the SDET threshold, determine the voltage level for RXBIAS from VRXBIAS/VDD. In most systems, VDD is assumed to be 3.3V and VRXBIAS is the voltage seen at the RXBIAS pin. 3. Use the equations to determine the resistance values for R1 and R2. The use of 1% resistors for R1 and R2 is recommended. Other regulated voltage sources may be used as long as the minimal current is provided. © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com G52297-0, Rev 4.0 04/02/01 VITESSE SEMICONDUCTOR CORPORATION Data Sheet Dual Repeater/Retimer for Fibre Channel and Gigabit Ethernet VSC7130 Hub Support Several functions are provided in the CDRx/SDUx circuitry to support FC-AL Hubs. Two programmable 40-bit registers are available to generate data on TX or SO, allowing simple 40-bit patterns to be generated easily. Monitoring of the serial data out of the repeater provides the user with information concerning data content of packets as they are received. Many FC-AL ordered sets are detected (all ARBs, IDLE, all LIPs, all CLS and all OPENs). Furthermore, two 40-bit registers/comparators are provided to allow the user to identify when user programmable patterns occur in the data. One use of these would be to monitor for the presence of ordered sets defined after release of this product. Please refer to the VSC7130 User’s Manual for a more complete description of the ordered set generation and recognition capabilities and associated register controls. Performance Monitoring In order to determine the relative traffic on the link, a 32-bit counter is provided which increments on each occurrence of an ARB ordered set or an IDLE ordered set. By reading this counter periodically, the relative traffic on the link can be calculated. Please refer to the VSC7130 User’s Manual for a more complete description of the performance monitoring capabilities and associated register controls. Power-On-Reset The VSC7130 has an internal Power-On-Reset circuit to provide approximately one millisecond delay after power up during which all Two-Wire accessible registers are reset. An alternate method for resetting the device is available. If TEST0 and A4 are LOW, the device is reset. Connect an active LOW Reset signal to TEST0 and A4 if it would be HIGH during normal operation. When the reset input is LOW, the alternative reset method is activated. When the reset input is HIGH, TEST0 and A4 assume their normal value. Two-Wire Interface An industry-standard Two-Wire Interface is provided to allow user access to internal control and status. Use of the interface is optional. SCL is the serial interface clock running at up to 400kHz when used with readily available microcontrollers. SDA is a bidirectional data signal. A4 and A3 selects the group address of the device while A2-A0 set the address. TWI and TWO are used to serially configure the address of daisy-chained devices in order to accommodate large numbers of devices on each Two-Wire Interface link. INT# is an open drain output used to signal an interruptible event to the microcontroller. Please refer to the VSC7130 User’s Manual for a more complete description of this interface, including timing diagrams. Proprietary Interface If higher performance than 400kHz is required, a proprietary mode may be used. In this mode, the SCL clock can operate at a maximum speed of 6.25MHz. Due to the speed of this link, significant electrical limitations may be placed on the link which will restrict trace lengths, the number of daisy-chained devices and the use of multiple masters. G52297-0, Rev 4.0 04/02/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 11 VITESSE SEMICONDUCTOR CORPORATION Data Sheet Dual Repeater/Retimer for Fibre Channel and Gigabit Ethernet VSC7130 The Verilog code for the Master Controller in proprietary mode will be made available to customers in order to ensure compatibility. This Master Controller core is designed to use either a 25MHz or a 50MHz clock to generate a 6.25MHz SCL clock frequency with a 25% high, 75% low duty cycle (1 clock high, 3 clocks low at 25MHz). Slower clock frequencies are also allowable. When using the Proprietary High-Speed mode of the Two-Wire Interface, all other interface functionality is identical to the standard Two-Wire Interface with the exception that the interface timing has changed. Interrupt Circuitry Interrupts are available only when the Two-Wire Interface is used, otherwise INT# will be disabled. The INT# output is open-drain so an external pull-up resistor is needed to allow the output to achieve a valid TTL or CMOS HIGH level. Multiple INT# outputs can be wire ORed together. INT# is a glitchless signal which is synchronized to divide-by-32 REFO clock. The output of the interrupt controller prior to the output buffer is readable in the INTOUT register bit, bit 2 of the CHIPS-00h register. The VSC7130 is capable of managing several different kinds of internal interrupt conditions. Each interrupt source can be enabled independently using the registers accessible via the Two-Wire Interface. When an enabled interrupt event occurs, the open-drain INT# output will be asserted LOW and will stay LOW until the interrupt is cleared. The register address corresponding to the highest priority pending interrupt can be read from ISR-F8h. This provides a relatively fast means for determining the source of the interrupt with a single register read operation. Please refer to the VSC7130 User’s Manual for a more complete description of the interrupt controller and its associated register controls. Table 3: Interrupt Status Register Addresses, Priorities and Sources Address (Hex) Priority Label Function 22 1 (Highest) SDU0S SDU0 Status Register: SDR0 (7), SDF0 (6), ASD0 (2), RLL0 (1), K280 (0) 2A 2 SDU1S SDU1 Status Register: SDR1 (7), SDF1 (6), ASD1 (2), RLL1 (1), K281 (0) 23 3 RTMR0C Retimer0 Configuration Register: UNDER0 (6), OVER0 (4), ADD0 (2), DROP0 (0) 2B 4 RTMR1C Retimer1 Configuration Register: UNDER1 (6), OVER1 (4), ADD1 (2), DROP1 (0) 6C 5 MATCHA0 Ordered Set Match Register A for CDR0: All Bits except RES (1) 6D 6 MATCHB0 Ordered Set Match Register B for CDR0: All Bits except RES (6) 7C 7 MATCHA1 Ordered Set Match Register A for CDR1: All Bits except RES (1) 7D 8 MATCHB1 Ordered Set Match Register B for CDR1: All Bits except RES (6) F4 9 (Lowest) TEST4 Test Register 4: TESTINT (4) for diagnostics Figure 10: Block Diagram of Interrupt Output INTOUT (CHIPS-00h, bit 2) Interrupt Controller Page 12 VDD Shared by Other Devices INT# © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com G52297-0, Rev 4.0 04/02/01 VITESSE SEMICONDUCTOR CORPORATION Data Sheet Dual Repeater/Retimer for Fibre Channel and Gigabit Ethernet VSC7130 Programmable Registers A list of the programmable registers accessible by the Two-Wire Interface is shown in Table 4. This list includes the address of the register, whether it is Readable and/or Writable, if it is a source of interrupts, the register’s name and function. Table 4: Programmable Registers Address (Hex) Read/ Write (or Clear) Interrupt Source Label Function CONFIGURATION/STATUS REGISTERS Chip Status Register 00 R N CHIPS 01 R/W N CHIPCA Chip Configuration Register A 02 R/W N CHIPCB Chip Configuration Register B 03 R/W N CHIPCC Chip Configuration Register C 20/28 R/W N CDRxC CDRx Configuration Register CDR0/CDR1 21/29 R/W N SDUxC SDUx Configuration Register 22/2A R/C Y SDUxS SDUx Status Register 23/2B R/W/C Y RTMRxC Retimer0 Configuration Register 25/2D R/W N KWINDx K28.5- Signal Detect Density Window Register for SDUx 60/70 R/W N OSGENxA0 Ordered Set Generator A, Bits 39-32 for CDRx 61/71 R/W N OSGENxA1 Ordered Set Generator A, Bits 31-24 for CDRx 62/72 R/W N OSGENxA2 Ordered Set Generator A, Bits 23-16 for CDRx 63/73 R/W N OSGENxA3 Ordered Set Generator A, Bits 15-8 for CDRx 64/74 R/W N OSGENxA4 Ordered Set Generator A, Bits 7-0 for CDRx 65/75 R/W N OSGENxB0 Ordered Set Generator B, Bits 39-32 for CDRx 66/76 R/W N OSGENxB1 Ordered Set Generator B, Bits 31-24 for CDRx 67/77 R/W N OSGENxB2 Ordered Set Generator B, Bits 23-16 for CDRx 68/78 R/W N OSGENxB3 Ordered Set Generator B, Bits 15-8 or CDRx 69/79 R/W N OSGENxB4 Ordered Set Generator B, Bits 7-0 for CDRx 6C/7C R/C Y MATCHAx Match Register A for CDRx 6D/7D R/C Y MATCHBx Match Register B for CDRx 6E/7E R/W N MATIEAx Match Interrupt Enable Register A for CDRx 6F/7F R/W N MATIEBx Match Interrupt Enable Register B for CDRx 80/90 R/W N OSRECxA0 Ordered Set Recognition Register A, Bits 39-32 for CDRx 81/91 R/W N OSRECxA1 Ordered Set Recognition Register A, Bits 32-24 for CDRx 82/92 R/W N OSRECxA2 Ordered Set Recognition Register A, Bits 23-16 for CDRx 83/93 R/W N OSRECxA3 Ordered Set Recognition Register A, Bits 15-8 for CDRx 84/94 R/W N OSRECxA4 Ordered Set Recognition Register A, Bits 7-0 for CDRx 85/95 R/W N OSMASKxA0 G52297-0, Rev 4.0 04/02/01 Ordered Set Mask Register A, Bits 39-32 for CDRx © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 13 VITESSE SEMICONDUCTOR CORPORATION Data Sheet Dual Repeater/Retimer for Fibre Channel and Gigabit Ethernet Address (Hex) Read/ Write (or Clear) Interrupt Source VSC7130 Label Function 86/96 R/W N OSMASKxA1 Ordered Set Mask Register A, Bits 31-24 for CDRx 87/97 R/W N OSMASKxA2 Ordered Set Mask Register A, Bits 23-16 for CDRx 88/98 R/W N OSMASKxA3 Ordered Set Mask Register A, Bits 15-8 for CDRx 89/99 R/W N OSMASKxA4 Ordered Set Mask Register A, Bits 7-0 for CDRx A0/B0 R/W N OSRECxB0 Ordered Set Recognition Register B, Bits 39-32 for CDRx A1/B1 R/W N OSRECxB1 Ordered Set Recognition Register B, Bits 32-24 for CDRx A2/B2 R/W N OSRECxB2 Ordered Set Recognition Register B, Bits 23-16 for CDRx A3/B3 R/W N OSRECxB3 Ordered Set Recognition Register B, Bits 15-8 for CDRx Ordered Set Recognition Register B, Bits 7-0 for CDRx A4/B4 R/W N OSRECxB4 A5/B5 R/W N OSMASKxB0 Ordered Set Mask Register B, Bits 39-32 for CDRx A6/B6 R/W N OSMASKxB1 Ordered Set Mask Register B, Bits 31-24 for CDRx A7/B7 R/W N OSMASKxB2 Ordered Set Mask Register B, Bits 23-16 for CDRx A8/B8 R/W N OSMASKxB3 Ordered Set Mask Register B, Bits 15-8 for CDRx A9/B9 R/W N OSMASKxB4 Ordered Set Mask Register B, Bits 7-0 for CDRx C0/D0 R/W N PCNT0x Performance Counter x, Bits 31-24 for CDRx C1/D1 R/W N PCNT1x Performance Counter x, Bits 23-16 for CDRx C2/D2 R/W N PCNT2x Performance Counter x, Bits 15-8 for CDRx C3/D3 R/W N PCNT3x Performance Counter x, Bits 7-0 for CDRx C4/D4 R/W N PCxCTL Performance Counter x Control Register MISCELLANEOUS REGISTERS F0 - N TEST0 Test Register #0, For Factory Test Only, Do Not Access F1 - N TEST1 Test Register #1, For Factory Test Only, Do Not Access F2 - N TEST2 Test Register #2, For Factory Test Only, Do Not Access F3 - N TEST3 Test Register #3, For Factory Test Only, Do Not Access F4 R/W Y TEST4 Test Register #4, Soft Reset, TWOPOR & INT# Control Register F5 - N TEST5 Test Register #5, For Factory Test Only, Do Not Access F6 - N TEST6 Test Register #6, For Factory Test Only, Do Not Access F7 R/W N SADDR Soft ADDRess Register F8 R/C N ISR FD R N MODEL1 Interrupt Status Register (Read, then write FFh to Clear) Model Number Register (High Byte) FE R N MODEL0 Model Number Register (Low Byte) FF R N VER Version Register NOTE: Please refer to the VSC7130 User’s Manual for a thorough description of each register and its function. Page 14 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com G52297-0, Rev 4.0 04/02/01 VITESSE SEMICONDUCTOR CORPORATION Data Sheet Dual Repeater/Retimer for Fibre Channel and Gigabit Ethernet VSC7130 AC Characteristics (Over Recommended Operating Conditions) Figure 11: AC Timing Diagrams RX0+/RX1+/SI1+/80% 20% TX+/SO+/- TP TS TS TP VIH(MIN) VIL(MAX) REFI TH TT TT TL T Table 5: AC Characteristics (Over recommended operating conditions) Parameters Description Min Typ Max Units TP Latency from any Serial Input to any Serial Output 0.25 — 8.75 ns No Retimer in path TS Differential Output Rise/Fall time — — 300 ps Between 20% and 80% TJ(RPTR) Total data output jitter [Repeater Mode] ps Jitter Generation at TX/SO when driven by the CRU in Repeater Mode. IEEE 802.3z Clause 38.68 TDJ(RPTR) Serial data output deterministic jitter (p-p) [Repeater Mode] ps Jitter Generation at TX/SO when driven by the CRU in Repeater Mode. IEEE 802.3z Clause 38.68 ps Jitter Generation at TX/SO when driven by the CRU in Retimer Mode. IEEE 802.3z Clause 38.68 TJ(RTMR) Total data output jitter [Retimer Mode] TDJ(RTMR) Serial data output deterministic jitter (p-p) [Retimer Mode] TJTOL Jitter Tolerance at RX0/RX1/SI TT REFI input rise/fall times F — — — — — — 192 80 192 Conditions — — 80 ps Jitter Generation at TX/SO when driven by the CRU in Retimer Mode. IEEE 802.3z Clause 38.68 0.24 — — UI Minimum Eye Opening for proper operation as defined in MJS 8.0. — — 1.5 ns Between VIL(MAX) and VIH(MIN) REFI Frequency 105 52.5 — 126 63 MHz HALF/FULL is LOW HALF/FULL is HIGH FO Frequency Offset between incoming data and REFI. -200 — +200 ppm DC REFI Duty Cycle 70 % G52297-0, Rev 4.0 04/02/01 30 Measured at 1.5V © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 15 VITESSE SEMICONDUCTOR CORPORATION Data Sheet Dual Repeater/Retimer for Fibre Channel and Gigabit Ethernet VSC7130 DC Characteristics (Over recommended operating conditions). Parameters Description Min Typ Max Units VIH Input HIGH voltage (TTL) 2.0 — 5.5 V VIL Input LOW voltage (TTL) 0 — 0.8 V Conditions IIH Input HIGH current (TTL) — 10 110 mA VIN = 2.4V IIL Input LOW current (TTL) — — -110 mA VIN = 0.5V VOH Output HIGH voltage (TTL) 2.4 — — V IOH = -1.0mA VOL Output LOW voltage (TTL) — — 0.5 V IOL= +1.0mA VDD Supply voltage 3.14 — 3.47 V PD Power dissipation — 850 1200 mW IDD Supply current — 260 345 mA ∆VIN(1) PECL input swing: RX0, RX1 or SI (PECL+) - (PECL-) 300 — 2200 mVp-p AC-coupled. Internally biased at VDD/2 ∆VOUT75(1) PECL output swing: TX or SO (PECL+) - (PECL-) 1200 — 2200 mVp-p 75Ω to VDD – 2.0 V ∆VOUT50(1) PECL output swing: TX or SO (PECL+) - (PECL-) 1000 — 2200 mVp-p 50Ω to VDD – 2.0 V ∆VIN PECL input REFI+ 300 — 2200 mVp-p ∆VOUT PECL output REFO+ 1000 — 2200 mVp-p VDD = 3.3V + 5% Outputs open, Typical is at 3.3V, maximum is at 3.47V, highest temperature NOTE (1): Refer to Application Note AN-37 for differential measurement techniques. Absolute Maximum Ratings (1) Power Supply Voltage (VDD) .............................................................................................................-0.5V to +4V PECL DC Input Voltage ......................................................................................................... -0.5V to VDD +0.5V TTL DC Input Voltage....................................................................................................................... -0.5V to 5.5V DC Voltage Applied to TTL Outputs ................................................................................... -0.5V to VDD + 0.5V TTL Output Current .................................................................................................................................... ±50mA PECL Output Current .................................................................................................................................. ±50mA Case Temperature Under Bias ...................................................................................................... -55°C to +125oC Storage Temperature.................................................................................................................... -65°C to + 150oC Maximum Input ESD (Human Body Model)............................................................................................... 1500V NOTE: (1) CAUTION: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods may affect device reliability. Recommended Operating Conditions Power Supply Voltage (VDD) .................................................................................................................+3.3V+5% Ambient Operating Temperature Range ....................................................................0oC Ambient to +95oC Case Page 16 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com G52297-0, Rev 4.0 04/02/01 VITESSE SEMICONDUCTOR CORPORATION Data Sheet Dual Repeater/Retimer for Fibre Channel and Gigabit Ethernet VSC7130 Package Pin Descriptions 63 59 57 51 49 R1/0 A4 A3 47 3 45 5 43 7 41 9 39 11 37 Exposed Pad Area 13 15 MODE0 MODE1 TXDIS 31 INT# VDD 29 VSS SI- 27 SI+ VSS 25 VDDP SO- 23 SO+ T/R 21 VDDP 19 VSS CAP1 17 VDDA CAP0 TEST0 HALF/FULL 35 TEST2 VSSA REFIVDD VDD SDET VDD REFI+ REFOVDDP SDA SCL VDDP REFO+ VSS TWI A0 VSS VDD RXBIAS A2 A1 VSS RX1+ VSS 53 RX1- N/C 55 N/C VDDP TX+ TX- VSS VDDP RX0+ 61 1 33 TEST1 BYP TWO RX0- VSS VSS N/C Figure 12: Pin Diagram, Top View NOTE: Exposed pad on bottom must be connected to ground. G52297-0, Rev 4.0 04/02/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 17 VITESSE SEMICONDUCTOR CORPORATION Data Sheet Dual Repeater/Retimer for Fibre Channel and Gigabit Ethernet VSC7130 Table 6: Pin Identification Pin # Name 61, 60 RX0+, RX0- INPUT - PECL. Serial input to MUX2/MUX1 from the external media. 50, 51 RX1+, RX1- INPUT - PECL. Serial input to MUX2/MUX1 from the external media. 48 R1/0 26, 27 SI+, SI- 57, 56 TX+, TX- OUTPUT - PECL. Serial output from CDR0 to the external media. 22, 23 SO+, SO- OUTPUT - PECL. Serial output from CDR1 to the internal system. 31 TXDIS INPUT - TTL. When HIGH, TX+=HIGH, TX-=HIGH. When LOW, TX+/- is enabled. Can be overridden by TXDDIS. 40 39 REFI+ REFI- INPUT - TTL or PECL. REFerence CLocK at 1/10th or 1/20th the baud rate as determined by HALF/FULL. Used for the clock multiplier unit. If TTL, leave REFIopen. If PECL, connect both REFI+ and REFI-. 35 34 MODE0 MODE1 36 HALF/FULL 9 10 REFO+ REFO- 13 SDET BIDIRECTIONAL - TTL: Configured by default as an output. Can be configured as an input via the Two-Wire Interface. Open drain, external 4.7KW pull-up required. 46 RXBIAS INPUT - ANALOG: External resistors set the level of the analog signal detect circuits in the RX1+/- input. See the Signal Detection section for more details. 20 T/R INPUT - TTL. When HIGH, CDR0 is configured as a Retimer, when LOW, a Repeater. Overridden by T/RDIS. 32 BYP INPUT - TTL. When HIGH, MUX3 passes SI to SO. When LOW, MUX3 passes the output of CDR1 to SO. Overridden by BYPDIS. 16, 17 CAP0, CAP1 INPUT - TTL. Selects RX1+/- when HIGH, RX0+/- when LOW. INPUT - PECL. Serial input to MUX1/MUX3 from the internal system. INPUT - TTL. Selects the mode of operation for CDRx. Overridden by the MODEDIS register bit. INPUT - TTL. When LOW, REFI is 1/10th the baud rate. When HIGH, REFI is 1/20th the baud rate OUTPUT - PECL: This is a buffered version of REFI+/- which is intended for daisy chaining the reference clocks between multiple chips. Clock Multiplier Unit PLL Loop Filter Capacitor. Nominally 0.1 µF, +/-20%, X7R SDA BIDIRECTIONAL - TTL: This is the Two-Wire Interface data pin. Open drain, external 4.7KW pull-up required. If not used, pull HIGH. 42 SCL INPUT - TTL: This is the Two-Wire Interface serial clock input. For normal Two-Wire Interface usage, SCL may be clocked at up to 400 KHz. For Proprietary Link mode, SCL should be at REFI/8 (HALF/FULL is HIGH) or REFI/16 (HALF/FULL is LOW). Open drain, external 4.7KW pull-up required. If not used, pull HIGH. 6, 5, 4, 3, 2 A0-A4 INPUT - TTL: A4 is the address to select the group address for Two-Wire Interface addressing. A0-A3 select the Two-Wire Interface address. A0-A3 are active only if TWI is LOW. If not used, pull HIGH or LOW. 44 TWI INPUT - TTL: Two-Wire Interface Input. This input enables daisy chaining of devices on the Two-Wire Interface so that addresses can be assigned in software. If not used, connect to VSS. 43 Page 18 Description © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com G52297-0, Rev 4.0 04/02/01 VITESSE SEMICONDUCTOR CORPORATION Data Sheet Dual Repeater/Retimer for Fibre Channel and Gigabit Ethernet VSC7130 Pin # Name Description 1 TWO BIDIRECTIONAL - TTL: Two-Wire Interface Output. This output enables daisy chaining of devices on the Two-Wire Interface so that addresses can be assigned in software. Input for power-up sensing. Output for Two-Wire Interface functions. Open drain. For Soft Addressing, pull HIGH with a 4.7kW resistor. For Fixed Addressing, pull LOW with a 4.7kW resistor. 30 INT# OUTPUT - TTL: This output indicates that an interruptible condition occurred internally. Open drain, external 4.7kW pull-up required. If not used, pull HIGH. 37 33 14 TEST0 TEST1 TEST2 12, 29, 38 41, 47 VDD Power Supply, 3.3V. 8, 11 21, 24 55, 58 VDDP High-Speed Output Power Supply. Pins 8 and 11 are for REFO+/- and may be left unconnected in order to power down this output buffer. Pins 21 and 24 are for SO+/-. Pins 55 and 58 are for TX+/- 18 VDDA Analog Power Supply, 3.3V for Clock Multiplier PLL. Filter and bypass to VSSA. 15 VSSA Analog Ground 7, 19, 25 28, 45, 49, 52 59, 62, 64 VSS Ground. 53, 54, 63 N/C Do not connect (these are internally connected.). G52297-0, Rev 4.0 04/02/01 INPUT - TTL. LOW for factory test, HIGH for normal operation. © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 19 VITESSE SEMICONDUCTOR CORPORATION Data Sheet Dual Repeater/Retimer for Fibre Channel and Gigabit Ethernet VSC7130 Package Information: 64-pin TQFP F G 64 Item 10 mm Tolerance A 1.20 MAX A1 0.10 ±0.05 A2 1.00 ±0.05 E 0.22 ±0.05 F 12.00 BASIC G 10.00 BASIC H 12.00 BASIC I 10.00 BASIC 49 48 L 1 M I H 16 33 17 32 Exposed Pad (Bottom Side) J 0.60 ±0.15 K 0.50 BASIC L 5.00 BASIC M 5.00 BASIC o 11/13 8 PLACES A2 A K 0.08/0.20 R STANDOFF A1 A 0.08 R MIN 0o- 7o 0.09/0.20 0.25 0.08 MAX. LEAD COPLANARITY E J NOTES: Drawing not to scale. All units in mm unless otherwise noted. Page 20 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com G52297-0, Rev 4.0 04/02/01 VITESSE SEMICONDUCTOR CORPORATION Data Sheet Dual Repeater/Retimer for Fibre Channel and Gigabit Ethernet VSC7130 Package Thermal Characteristics The VSC7130 is packaged in an exposed pad, thin quad flatpack (TQFP) which adheres to industry-standard EIAJ footprints for a 10x10x1.0mm body, 64-lead TQFP. The package construction is shown in Figure 13. The bottom of the leadframe is exposed so that it can be soldered to the printed circuit board and connected to the ground plane. This provides excellent thermal characteristics and reduces electrical parasitics as well. Note: contact Vitesse for the package vendor Application Note for details about using the exposed pad. Figure 13: Package Cross Section Wire Bond Die Die Attach Epoxy Plastic Molding Compound Copper Lead Frame Grounded Down Bond Exposed Pad Table 7: 64-pin, Exposed Pad, TQFP Thermal Resistance Symbol Description Value Units qCA-0 Thermal resistance from case to ambient, still air 30 o C/W qCA-100 Thermal resistance from case to ambient, 100 LFPM air 25 o C/W C/W qCA-200 Thermal resistance from case to ambient, 200 LFPM air 23 o qCA-400 Thermal resistance from case to ambient, 400 LFPM air 21 o C/W 20 o C/W qCA-600 Thermal resistance from case to ambient, 600 LFPM air The VSC7130 is designed to operate with a case temperature up to 95oC. The user must guarantee that the case temperature specification is not violated. With the thermal resistances shown above, the VS7130 can operate in still air ambient temperatures of 70oC [ ~70oC = 95oC - 0.8W * 30 ]. If the ambient air temperature exceeds these limits then some form of cooling through a heatsink or an increase in airflow must be provided. Additional heat can be transferred to the printed circuit board by not using thermal reliefs on the power and ground plane vias as well as using multiple vias to the power and ground planes. If the exposed pad is not soldered to the printed circuit board and grounded, both thermal and electrical performance will be degraded significantly. Moisture Sensitivity Level This device is rated at a Moisture Sensitivity Level 3 rating with maximum floor life of 168 hours at 30ºC, 60% relative humidity. Please refer to Application Note AN-20 for appropriate handling procedures G52297-0, Rev 4.0 04/02/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 21 VITESSE SEMICONDUCTOR CORPORATION Data Sheet Dual Repeater/Retimer for Fibre Channel and Gigabit Ethernet VSC7130 Order information The order number for this product is formed by a combination of the device number, and package type. VSC7130 XX Device Type Dual Repeater/Retimer for Fibre Channel and Gigabit Ethernet Package RC: 64-Pin Exposed Pad TQFP, 10x10x1.0mm Marking Information The top of the package is marked as in Figure 13. Figure 14: Package Marking Information Pin 1 Identifier Part Number VSC7130RC DateCode ####AAAAA Package Suffix Lot Tracking Code (4 or 5 characters) VITESSE Notice Vitesse Semiconductor Corporation (“Vitesse”) provides this document for informational purposes only. This document contains pre-production information about Vitesse products in their concept, development and/or testing phase. All information in this document, including descriptions of features, functions, performance, technical specifications and availability, is subject to change without notice at any time. Nothing contained in this document shall be construed as extending any warranty or promise, express or implied, that any Vitesse product will be available as described or will be suitable for or will accomplish any particular task. Vitesse products are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without written consent is prohibited. Page 22 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com G52297-0, Rev 4.0 04/02/01