PRELIMINARY W204 Spread Spectrum FTG for 440BX and VIA Apollo Pro-133 Features CPU Cycle to Cycle Jitter: ..........................................250 ps • Maximized EMI suppression using Cypress’s spread spectrum technology • Optimized system frequency synthesizer for 440BX and VIA Apollo Pro-133 • Four copies of CPU output • Eight copies of PCI clock (synchronous w/CPU output) • Two copies of 14.318-MHz IOAPIC output and three buffered copies of 14.318-MHz reference input • One copy of 48-MHz USB output • Selectable 24-/48-MHz clock-through-resistor strapping • Power management control input pins • Programmable clock outputs up to 155 MHz via SMBus interface (32 selectable frequencies) CPU0:3 Output Skew: ................................................175 ps PCI_F, PCI1:7 Output Skew: .......................................500 ps CPU to PCI Output Skew: ............... 1.0–4.0 ns (CPU Leads) REF0/SEL48#, SCLK,SDATA:........................... 250K pull-up FS1:...............................................................250K pull-down FS0:...................................................No pull-up or pull-down Test mode and output three-state through SMBus interface Table 1. Pin Selectable Frequency Key Specifications FS1 FS0 CPU(0:3) PCI 1 1 133.3 MHz 33.3 MHz 1 0 105 MHz 35 MHz 0 1 100 MHz 33.3 MHz 0 0 66.8 MHz 33.3 MHz Supply Voltages: ..................................... VDDQ3 = 3.3V±5% VDDQ2 = 2.5V±5% [1] Block Diagram Pin Configuration VDDQ3 REF0/SEL48# X1 X2 REF1 XTAL OSC REF2 GND VDDQ2 APIC0 PLL Ref Freq VDDCORE0/1 GNDCORE0/1 APIC1 GND VDDQ2 CPU_STOP# CPU0 CPU1 GND VDDQ2 CPU2 Stop Clock Control FS0:1 PLL 1 CPU3 GND VDDQ3 ÷2/÷3 SPREAD# PCI_F PCI1 Stop Clock Control PCI2 PCI3 GND VDDQ3 PCI4 PCI_STOP# SDATA SCLK REF0/SEL48# REF1 GND X1 X2 GND PCI_F PCI1 VDDQ3 PCI2 PCI3 GND PCI4 PCI5 VDDQ3 PCI6 PCI7 GND VDDQ3 GND VDDQ3 48MHz 24_48MHz/FS1 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDQ3 REF2 VDDQ2 APIC0 APIC1 GND NC VDDQ2 CPU0 CPU1 GND VDDQ2 CPU2 CPU3 GND VDDQ3 GND PCI_STOP# CPU_STOP# PWR_DWN# SPREAD# SDATA SCLK FS0 Note: 1. Internal pull-up resistors should not be relied upon for setting I/O pins HIGH. PCI5 I2C Logic PCI6 PCI7 Power Down Control PWR_DWN# GND VDDQ3 48MHz PLL2 24_48MHz/FS1 GND Cypress Semiconductor Corporation Document #: 38-07264 Rev. *A • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 22, 2002 PRELIMINARY W204 Pin Definitions Pin No. Pin Type CPU0:3 40, 39, 36, 35 O CPU Clock Outputs 0 through 3: These four CPU clock outputs are controlled by the CPU_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ2. PCI1:7 8, 10, 11, 13, 14, 16, 17 O PCI Bus Clock Outputs 1 through 7: These seven PCI clock outputs are controlled by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ3. PCI_F 7 O Fixed PCI Clock Output: Unlike PCI1:7 outputs, this output is not controlled by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ3. CPU_STOP# 30 I CPU_STOP# Input: When brought LOW, clock outputs CPU0:3 are stopped LOW after completing a full clock cycle (2-3 CPU clock latency). When brought HIGH, clock outputs CPU0:3 start beginning with a full clock cycle (2-3 CPU clock latency). PCI_STOP# 31 I PCI_STOP# Input: The PCI_STOP# input enables the PCI 1:7 outputs when HIGH and causes them to remain at logic 0 when LOW. The PCI_STOP signal is latched on the rising edge of PCI_F. Its effect takes place on the next PCI_F clock cycle. SPREAD# 28 I SPREAD# Input: When brought low this pin activates Spread Spectrum clocking. APIC0:1 45, 44 O I/O APIC Clock Outputs: Provides 14.318-MHz fixed frequency. The output voltage swing is controlled by VDDQ2. 48MHz 22 O 48-MHz Output: Fixed clock outputs at 48 MHz. Output voltage swing is controlled by voltage applied to VDDQ3. 24_48MHz/FS1 23 O 24-MHz or 48-MHz Output/Frequency Select 1: 24 MHz output when pin 1 is strapped through 10-KΩ resistor to VDDQ3. 48-MHz output when pin 1 is strapped through 10-KΩ resistor to GND. This pin also serves as the select strap to determine device operating frequency as described in Table 1. REF0/SEL48# 1 I/O I/O Dual-Function REF0 and SEL48# pin: During power-on, SEL48# input will be latched which will set pin 23 to output 24 MHz or 48 MHz. It then reverts to REF0 fixed output. 2, 47 O Fixed 14.318-MHz Outputs 1 through 2: Used for various system applications. Output voltage swing is controlled by voltage applied to VDDQ3. FS0 25 I Frequency Selection 0: Selects power-up default CPU clock frequency as shown in Table 1. SCLK 26 I Clock pin for SMBus circuitry. SDATA 27 I/O X1 4 I Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. X2 5 I Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. PWR_DWN# 29 I Power-Down Control: When this input is LOW, device goes into a low-power standby condition. All outputs are actively held LOW while in power-down. CPU and PCI clock outputs are stopped LOW after completing a full clock cycle (2–3 CPU clock cycle latency). When brought high, CPU, SDRAM and PCI outputs start with a full clock cycle at full operating frequency (3 ms maximum latency). VDDQ3 9, 15, 19, 21, 33, 48 P Power Connection: Connect to 3.3V supply. VDDQ2 46, 41, 37 P Power Connection: Power supply for APIC0:1 and CPU0:3 output buffers. Connect to 2.5V. 3, 6, 12, 18, 20, 24, 32, 34, 38, 43 G Ground Connections: Connect all ground pins to the common system ground plane. Pin Name REF1:2 GND Document #: 38-07264 Rev. *A Pin Description Data pin for SMBus circuitry. Page 2 of 16 PRELIMINARY Overview The W204, a motherboard clock synthesizer, can provide either a 2.5V or 3.3V CPU clock swing making it suitable for a variety of CPU options. A fixed 48-MHz clock is provided for other system functions. The device W204 supports spread spectrum clocking for reduced EMI. Functional Description I/O Pin Operation Pins 1 and 23 are dual-purpose l/O pins. Upon power-up these pins act as a logic input, allowing the determination of assigned device functions. A short time after power-up, the logic state of the pin is latched and the pin becomes a clock output. This feature reduces device pin count by combining clock outputs with input select pins. An external 10-KΩ “strapping” resistor is connected between the l/O pin and ground or VDD. Connection to ground sets a latch to “0”, connection to VDD sets a latch to “1”. Figure 1 and Figure 2 show two suggested methods for strapping resistor connections. Upon W204 power-up, the first 2 ms of operation is used for input logic selection. During this period, pins 1 and 23 are W204 three-stated, allowing the output strapping resistor on the l/O pin to pull the pin and its associated capacitive clock load to either a logic HIGH or LOW state. At the end of the 2-ms period, the established logic “0” or “1” condition of the l/O pin is then latched. Next the output buffer is enabled which converts the l/O pin into an operating clock output. The 2-ms timer is started when VDD reaches 2.0V. The input bits can only be reset by turning VDD off and then back on again. It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive impedance of clock output is 40Ω (nominal) which is minimally affected by the 10-KΩ strap to ground or VDD. As with the series termination resistor, the output strapping resistor should be placed as close to the l/O pin as possible in order to keep the interconnecting trace short. The trace from the resistor to ground or VDD should be kept less than two inches in length to prevent system noise coupling during input logic sampling. When the clock outputs are enabled following the 2-ms input period, the associated output frequencies are delivered on the pins, assuming that VDD has stabilized. If VDD has not yet reached full value, output frequency initially may be below target but will increase to target once VDD voltage has stabilized. In either case, a short output clock cycle may be produced from the CPU clock outputs when the outputs are enabled. VDD Output Strapping Resistor Series Termination Resistor 10 kΩ (Load Option 1) Clock Load W204 Output Buffer Power-on Reset Timer Hold Output Low Output Three-state Q 10 kΩ (Load Option 0) D Data Latch Figure 1. Input Logic Selection Through Resistor Load Option Jumper Options Output Strapping Resistor VDD Series Termination Resistor 10 kΩ W204 Power-on Reset Timer R Output Buffer Hold Output Low Output Three-state Q Clock Load Resistor Value R D Data Latch Figure 2. Input Logic Selection Through Jumper Option Document #: 38-07264 Rev. *A Page 3 of 16 PRELIMINARY W204 Spread Spectrum Feature Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured. The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 3. The output clock is modulated with a waveform depicted in Figure 4. This waveform, as discussed in “Spread Spectrum Clock Generation for the Reduction of Radiated Emissions” by Bush, Fessler, and Hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. The deviation selected for this chip is ± 0.5% of the center frequency. Figure 4 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices. As shown in Figure 3, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is: dB = 6.5 + 9*log10(P) + 9*log10(F) 5dB/div Typical Clock Amplitude (dB) SSFTG –1.0 0 –0.5% –SS% Frequency Span (MHz) +1.0 +0.5% +SS% Figure 3. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% FREQUENCY MAX (+0.5%) MIN (–0.5%) Figure 4. Typical Modulation Profile Document #: 38-07264 Rev. *A Page 4 of 16 PRELIMINARY Serial Data Interface The W204 features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Upon power-up, the W204 initializes with default register settings. Therefore, the use of this serial data interface is optional. The serial interface is write-only (to the clock chip) and is the dedicated function of device pins SDATA and SCLOCK. In motherboard applications, SDATA and SCLOCK are typically driven by two logic outputs of the W204 chipset. Clock device register changes are normally made upon system initialization, if required. The interface can also be used during system operation for power management functions. Table 2 summarizes the control functions of the serial data interface. Operation Data is written to the W204 in ten bytes of eight bits each. Bytes are written in the order shown in Table 3. Table 2. Serial Data Interface Control Functions Summary Control Function Description Common Application Clock Output Disable Any individual clock output(s) can be disabled. Disabled outputs are actively held LOW. Unused outputs are disabled to reduce EMI and system power. Examples are clock outputs to unused PCI slots. CPU Clock Frequency Selection Provides CPU/PCI frequency selections beyond the 100- and 66.66-MHz selections that are provided by the FS0:1 pins. Frequency is changed in a smooth and controlled fashion. For alternate microprocessors and power management options. Smooth frequency transition allows CPU frequency change under normal system operation. Output Three-state Puts all clock outputs into a high impedance state. Production PCB testing. Test Mode All clock outputs toggle in relation to X1 input, in- Production PCB testing. ternal PLL is bypassed. Refer to Table 4. (Reserved) Reserved function for future device revision or pro- No user application. Register bit must be written duction device testing. as 0. Table 3. Byte Writing Sequence Byte Sequence Byte Name 1 Slave Address 11010010 Commands the W204 to accept the bits in Data Bytes 3–6 for internal register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. The slave receiver address for the W204 is 11010010. Register setting will not be made if the Slave Address is not correct (or is for an alternate slave receiver). 2 Command Code Don’t Care Unused by the W204, therefore bit values are ignored (“Don’t Care”). This byte must be included in the data write sequence to maintain proper byte allocation. The Command Code Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. 3 Byte Count Don’t Care Unused by the W204, therefore bit values are ignored (“Don’t Care”). This byte must be included in the data write sequence to maintain proper byte allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. 4 Data Byte 0 Don’t Care Refer to Cypress SDRAM drivers. 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 Refer to Table 4 8 Data Byte 4 The data bits in these bytes set internal W204 registers that control device operation. The data bits are only accepted when the Address Byte bit sequence is 11010010, as noted above. For description of bit control functions, refer to Table 4, Data Byte Serial Configuration Map. 9 Data Byte 5 10 Data Byte 6 Document #: 38-07264 Rev. *A Bit Sequence Byte Description Page 5 of 16 PRELIMINARY Writing Data Bytes Each bit in the data bytes control a particular device function except for the “reserved” bits which must be written as a logic 0. Bits are written MSB (most significant bit) first, which is bit 7. Table 4 gives the bit formats for registers located in Data Bytes 3–6. W204 Table 5 details additional frequency selections that are available through the serial data interface. Table 6 details the select functions for Byte 3, bits 1 and 0. Table 4. Data Bytes 3–6 Serial Configuration Map Affected Pin Bit(s) Pin No. Pin Name Data Byte 3 7 --6 --5 --4 --3 --2 1–0 Data Byte 4 7 6 5 4 3 2 1 0 Data Byte 5 7 6 5 4 3 2 1 0 Data Byte 6 7 6 5 4 3 2 1 0 Bit Control Control Function SEL_3 SEL_2 SEL_1 SEL_0 BYT3_FS# 1 Refer to Table 5 Refer to Table 5 Refer to Table 5 Refer to Table 5 Frequency Controlled Frequency Controlled by external FS0:1 pins by BYT3 SEL_(3:0) --Function (See Table 6 for function details) Spread Spectrum OFF Test Mode Spread Spectrum ON (default) All Outputs Three-stated Default 0 0 0 0 0 --- --- -23 --35 36 39 40 -24_48MHz --CPU3 CPU2 CPU1 CPU0 (Reserved) Clock Output Disable (Reserved) (Reserved) Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable -Low --Low Low Low Low -Active --Active Active Active Active 0 1 0 0 1 1 1 1 7 17 16 14 13 11 10 8 PCI_F PCI7 PCI6 PCI5 PCI4 PCI3 PCI2 PCI1 Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Low Low Low Low Low Low Low Low Active Active Active Active Active Active Active Active 1 1 1 1 1 1 1 1 --44 45 -47 2 1 --APIC1 APIC0 -REF2 REF1 REF0 (Reserved) (Reserved) Clock Output Disable Clock Output Disable (Reserved) Clock Output Disable Clock Output Disable Clock Output Disable --Low Low -Low Low Low --Active Active -Active Active Active 0 0 1 1 0 1 1 1 Document #: 38-07264 Rev. *A (Reserved) Bit 1 Bit 0 0 0 0 1 1 0 1 1 0 0 10 Page 6 of 16 PRELIMINARY W204 Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes Input Conditions Data Byte 3, Bit [7:4, 1:0] Output Frequency If Spread Is On Bit [1:0] 00 Bit 7 SEL_3 0 Bit 6 SEL_2 0 Bit 5 SEL_1 0 Bit 4 SEL_0 0 CPU, SDRAM Clocks (MHz) 78 PCI Clocks (MHz) 39 Spread Percentage OFF 00 00 0 0 0 0 0 1 1 0 81 113.5 40.5 37.8 OFF OFF 00 00 0 0 0 1 1 0 1 0 66.8 117 33.4 39 OFF OFF 00 00 0 0 1 1 0 1 1 0 118.5 122 39.5 37.3 OFF OFF 00 00 0 1 1 0 1 0 1 0 100 126 33.3 31.5 OFF OFF 00 00 1 1 0 0 0 1 1 0 135 137 33.75 34.25 OFF OFF 00 00 1 1 0 1 1 0 1 0 138.5 142 34.62 35.5 OFF OFF 00 00 1 1 1 1 0 1 1 0 144 155 36 38.75 OFF OFF 00 10 1 0 1 0 1 0 1 0 133.3 124 33.3 41.3 OFF ±0.5% Center 10 10 0 0 0 0 0 1 1 0 75 83.3 37.5 41.65 ±0.5% Center ±0.5% Center 10 10 0 0 0 1 1 0 1 0 66.8 90 33.4 30 ±0.5% Center ±0.5% Center 10 10 0 0 1 1 0 1 1 0 112 95 37.3 31.67 ±0.5% Center ±0.5% Center 10 10 0 1 1 0 1 0 1 0 100 120 33.3 40 ±0.5% Center ±0.5% Center 10 10 1 1 0 0 0 1 1 0 115 110 38.3 36.67 ±0.5% Center ±0.5% Center 10 10 1 1 0 1 1 0 1 0 105 140 35 35 ±0.5% Center ±0.5% Center 10 10 1 1 1 1 0 1 1 0 150 124 37.5 31 ±0.5% Center ±0.5% Center 10 1 1 1 1 133.3 33.3 ±0.5% Center Table 6. Select Function for Data Byte 3, Bits 0:1 Input Conditions Output Conditions Data Byte 3 Function Bit 1 Bit 0 CPU0:3 PCI_F, PCI1:7 REF0:2, IOAPIC0:1 48MHZ 24MHZ Spread Spectrum OFF 0 0 Note 2 Note 2 14.318 MHz 48 MHz 24 MHz Test Mode 0 1 X1/2 CPU/2 or 3 X1 X1/2 X1/4 Spread Spectrum ON (default) 1 0 Note 2 SS%=±0.5 Note 2 SS%=±0.5 14.318 MHz 48 MHz 24 MHz Three-state 1 1 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Note: 2. CPU and PCI frequency selections are listed in Table 1 and Table 5. Document #: 38-07264 Rev. *A Page 7 of 16 PRELIMINARY How To Use the Serial Data Interface Electrical Requirements Figure 5 illustrates electrical characteristics for the serial interface bus used with the W204. Devices send data over the bus with an open drain logic output that can (a) pull the bus line low, or (b) let the bus default to logic 1. The pull-up resistors on the bus (both clock and data lines) establish a default logic 1. All bus devices generally have logic inputs to receive data. W204 Although the W204 is a receive-only device (no data write-back capability), it does transmit an “acknowledge” data pulse after each byte is received. Thus, the SDATA line can both transmit and receive data. The pull-up resistor should be sized to meet the rise and fall times specified in AC parameters, taking into consideration total bus line capacitance. VDD VDD ~ 2kΩ ~ 2kΩ SERIAL BUS DATA LINE SERIAL BUS CLOCK LINE SDCLK CLOCK IN CLOCK OUT DATA IN N DATA OUT CHIP SET (SERIAL BUS MASTER TRANSMITTER) SCLOCK SDATA CLOCK IN N SDATA DATA IN DATA OUT N CLOCK DEVICE (SERIAL BUS SLAVE RECEIVER) Figure 5. Serial Interface Bus Electrical Characteristics Document #: 38-07264 Rev. *A Page 8 of 16 PRELIMINARY W204 Signaling Requirements Sending Data to the W204 As shown in Figure 6, valid data bits are defined as stable logic 0 or 1 condition on the data line during a clock HIGH (logic 1) pulse. A transitioning data line during a clock HIGH pulse may be interpreted as a start or stop pulse (it will be interpreted as a start or stop pulse if the start/stop timing parameters are met). The device accepts data once it has detected a valid start bit and address byte sequence. Device functionality is changed upon the receipt of each data bit (registers are not double buffered). Partial transmission is allowed meaning that a transmission can be truncated as soon as the desired data bits are transmitted (remaining registers will be unmodified). Transmission is truncated with either a stop bit or new start bit (restart condition). A write sequence is initiated by a “start bit” as shown in Figure 7. A “stop bit” signifies that a transmission has ended. As stated previously, the W204 sends an “acknowledge” pulse after receiving eight data bits in each byte as shown in Figure 8. SDATA SCLOCK Valid Data Bit Change of Data Allowed Figure 6. Serial Data Bus Valid Data Bit SDATA SCLOCK Start Bit Stop Bit Figure 7. Serial Data Bus Start and Stop Bit Document #: 38-07264 Rev. *A Page 9 of 16 Document #: 38-07264 Rev. *A 1 SCLOCK 2 1 Figure 8. Serial Data Bus Write Sequence SCLOCK SDATA tSTHD 3 0 tR tLOW Signaling by Clock Device SDATA MSB 1 SDATA 4 1 tF tHIGH 5 0 Slave Address (First Byte) Signaling from System Core Logic Start Condition 6 0 7 LSB 1 tDSU 8 0 A 1 MSB 3 4 5 6 tSP Acknowledgment Bit from Clock Device tDHD 2 Command Code (Second Byte) 7 8 LSB A 1 2 tSPSU MSB 3 4 tSTHD Byte Count (Third Byte) 1 MSB 2 4 tSPSU 3 5 tSPF 6 Last Data Byte (Last Byte) 7 8 LSB A Stop Condition PRELIMINARY W204 Figure 9. Serial Data Bus Timing Diagram Page 10 of 16 PRELIMINARY W204 Absolute Maximum Ratings [3] Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions Parameter above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Description Rating Unit VDD, VIN Voltage on any pin with respect to GND –0.5 to +7.0 V TSTG Storage Temperature –65 to +150 °C TB Ambient Temperature under Bias –55 to +125 °C TA Operating Temperature 0 to +70 °C ESDPROT Input ESD Protection 2 (min.) kV DC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2 = 2.5V±5% Parameter Description Test Condition Min. Typ. Max. Unit 120 mA 60 mA V Supply Current IDDQ3 3.3V Supply Current IDDQ2 2.5V Supply Current CPU0:3 =100 MHz Outputs Loaded[4] Logic Inputs VIL Input Low Voltage GND – 0.3 0.8 2.0 VIH Input High Voltage VDD + 0.3 V IIL Input Low Current[5] –25 µA IIH Input High Current[5] 10 µA Input Low Current (FS0) –5 µA Input High Current (FS0) +5 µA 50 mV Clock Outputs VOL Output Low Voltage IOL = 1 mA VOH Output High Voltage IOH = –1 mA 3.1 V VOH Output High Voltage (CPU, APIC) IOH = –1 mA 2.2 V IOL Output Low Current VOL = 1.25V 27 PCI_F, PCI1:7 VOL = 1.5V 20.5 APIC0:1 VOL = 1.25V 40 REF0:2 VOL = 1.5V 25 48MHz 0:1 VOL = 1.5V 25 CPU0:3 VOL = 1.25V 25 PCI_F, PCI1:7 VOL = 1.5V 31 APIC0:1 VOL = 1.25V 40 REF0:2 VOL = 1.5V 27 48MHz 0:1 VOL = 1.5V 27 IOH Output High Current CPU0:3 57 97 mA 53 139 mA 85 140 mA 37 76 mA 37 76 mA 55 97 mA 55 189 mA 87 155 mA 44 94 mA 44 94 mA Crystal Oscillator VTH X1 Input Threshold Voltage[6] CLOAD Load Capacitance, as seen by External Crystal[7] CIN,X1 X1 Input Capacitance[8] VDDQ3 = 3.3V Pin X2 unconnected 1.65 V 14 pF 28 pF Notes: 3. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 4. All clock outputs loaded with 6” 60Ω transmission lines with 20-pF capacitors. 5. W204 logic inputs have internal pull-up resistors, except FS0 (pull-ups not full CMOS level). 6. X1 input threshold voltage (typical) is VDD/2. 7. The W204 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF; this includes typical stray capacitance of short PCB traces to crystal. 8. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected). Document #: 38-07264 Rev. *A Page 11 of 16 PRELIMINARY W204 DC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2 = 2.5V±5% (continued) Parameter Description Test Condition Min. Typ. Max. Unit 5 pF Pin Capacitance/Inductance CIN Input Pin Capacitance Except X1 and X2 COUT Output Pin Capacitance 6 pF LIN Input Pin Inductance 7 nH AC Electrical Characteristics TA = 0°C to +70°C, VDDQ3 = 3.3V±5%,VDDQ2 = 2.5V± 5%, fXTL = 14.31818 MHz AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output; Spread Spectrum clocking is disabled. CPU Clock Outputs, CPU0:3 (Lump Capacitance Test Load = 20 pF) CPU = 66.8 MHz Parameter Description Test Condition/Comments CPU = 100 MHz Min. Typ. Max. Min. Period Measured on rising edge at 1.25V 15 tH High Time Duration of clock cycle above 2.0V 5.2 3.0 ns tL Low Time Duration of clock cycle below 0.4V 5.0 2.8 ns tR Output Rise Edge Rate Measured from 0.4V to 2.0V 1 4 1 4 V/ns tF Output Fall Edge Rate Measured from 2.0V to 0.4V 1 4 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.25V 45 55 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. 200 200 ps tSK Output Skew Measured on rising edge at 1.25V 250 250 ps fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. Document #: 38-07264 Rev. *A 15.5 Typ. Max. Unit tP 20 10 10.5 20 ns Ω Page 12 of 16 PRELIMINARY W204 PCI Clock Outputs, PCI1:7 and PCI_F (Lump Capacitance Test Load = 30 pF CPU = 66.8/100 MHz Parameter Description Test Condition/Comments Min. Typ. Max. Unit tP Period Measured on rising edge at 1.5V 30 ns tH High Time Duration of clock cycle above 2.4V 12 ns tL Low Time Duration of clock cycle below 0.4V 12 ns tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. 250 ps tSK Output Skew Measured on rising edge at 1.5V 500 ps tO CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output. 4 ns fST Frequency Stabilization Assumes full supply voltage reached within 1 ms from Power-up (cold start) from power-up. Short cycles exist prior to frequency stabilization. 3 ms Zo AC Output Impedance 1 Average value during switching transition. Used for determining series termination value. Ω 30 APIC0:1 Clock Output (Lump Capacitance Test Load = 20 pF) CPU = 66.8/100 MHz Parameter Description Test Condition/Comments Min. Typ. Max. 14.31818 Unit f Frequency, Actual Frequency generated by crystal oscillator MHz tR Output Rise Edge Rate Measured from 0.4V to 2.0V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.0V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.25V 45 fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 55 % 1.5 ms Ω 15 REF0:2 Clock Output (Lump Capacitance Test Load = 20 pF) CPU = 66.8/100 MHz Parameter Description Test Condition/Comments Min. Typ. Max. Frequency, Actual Frequency generated by crystal oscillator tR Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. Document #: 38-07264 Rev. *A 14.318 Unit f 40 MHz Ω Page 13 of 16 PRELIMINARY W204 48-MHz0:1 Clock Output (Lump Capacitance Test Load = 20 pF = 66.6/100 MHz) CPU = 66.8/100 MHz Parameter Description Test Condition/Comments f Frequency, Actual Determined by PLL divider ratio (see m/n below) Min. Typ. Max. Unit 48.008 MHz ppm fD Deviation from 48 MHz (48.008 – 48)/48 +167 m/n PLL Ratio (14.31818 MHz x 57/17 = 48.008 MHz) 57/17 tR Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 40 Ω Ordering Information Ordering Code Package Name W204 Document #: 38-07264 Rev. *A H Package Type 48-pin SSOP (300 mils) Page 14 of 16 PRELIMINARY W204 Package Diagram Summary of nominal dimensions in inches: Body Width: 0.296 Lead Pitch: 0.025 Body Length: 0.625 Body Height: 0.102 Document #: 38-07264 Rev. *A Page 15 of 16 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY W204 Document Title: W204 Spread Spectrum FTG for 440BX and VIA Apollo Pro-133 (Preliminary) Document Number: 38-07264 ECN NO. Issue Date Orig. of Change ** 110529 01/31/02 SZV Change from Spec number: 38-01103 to 38-07264 *A 122862 12/22/02 RBI Added power up requirements to Maximum Ratings. REV. Document #: 38-07264 Rev. *A Description of Change Page 16 of 16