W207B
Spread Spectrum FTG for SiS540 and 630 Chipsets
Features
• Maximized EMI Suppression using Cypress’s Spread
Spectrum technology
• Single-chip system frequency synthesizer for SiS540
and SiS630 core logic chip sets
• Three copies of CPU output
• Seven copies of PCI output
• One 48-MHz output for USB
• One 24-/48-MHz selectable output for SIO
• Two buffered reference outputs
• 14 SDRAM outputs provide support for 3 DIMMs SMBus
interface for programming
Key Specifications
CPU Cycle-to-Cycle Jitter: ......................................... 250 ps
CPU to CPU Output Skew: ........................................ 175 ps
PCI to PCI Output Skew: ............................................ 500 ps
CPU to PCI Output Skew (CPU leads): ................... 1 to 4 ns
CPU to SDRAM Output Skew: .................................... 500 ps
VDDQ3: .................................................................... 3.3V±5%
Table 1. Pin Selectable Frequency
CPU SDRAM
PC
FS3 FS2 FS1 FS0 (MHz) (MHz) (MHz)
0
0
0
0
66.6
100.0
33.3
0
0
0
1
100.2
100.2
33.4
0
0
1
0
150.3
100.2
37.6
0
0
1
1
133.6
100.2
33.4
0
1
0
0
66.8
111.3
33.4
0
1
0
1
100.2
133.6
33.4
0
1
1
0
100.2
150.3
33.4
0
1
1
1
133.3
133.3
33.3
1
0
0
0
66.6
66.6
33.3
1
0
0
1
83.3
83.3
31.2
1
0
1
0
97.0
97.0
32.3
1
0
1
1
95.0
95.0
31.7
1
1
0
0
95.0
126.7
31.7
1
1
0
1
112.0
112.0
37.3
1
1
1
0
122.0
91.5
30.5
1
1
1
1
122.0
122.0
30.5
SS
–0.6%
±0.45%
OFF
±0.45%
OFF
±0.45%
OFF
–0.6%
–0.6%
OFF
–0.6%
±0.45%
OFF
OFF
–0.6%
–0.6%
VDDQ2: .................................................3.3V±5% or 2.5V±5%
Pin Configuration [1]
Block Diagram
VDDQ3
X1
X2
REF0_2X/FS3
XTAL
OSC
PLL Ref Freq
SDRAM0:13
÷
13
VDDQ2
PLL 1
3
÷
CPU0:2
VDDQ3
PCI0/FS1
PCI1/FS2
PCI2
PCI3
{
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
W207B
VDDQ3
REF0_2X/FS3*
GND
X1
X2
VDDQ3
PCI0/FS1*
PCI1/FS2*
PCI2
GND
PCI3
PCI4
PCI5
PCI6
VDDQ3
GND
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
GND
SMBus SDATA
SCLK
REF1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF1
VDDQ2
CPU0
CPU1
GND
CPU2
VDDQ3
SDRAM13
SDRAM12
GND
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
GND
SDRAM7
SDRAM6
VDDQ3
SDRAM5
SDRAM4
VDDQ3
48MHz_2X/FS0*
SIO/CPU3.3#_2.5*
PCI4
SDATA
SCLK
PCI5
PCI6
I2C
Logic
VDDQ3
48MHz_2X/FS0
PLL2
Note:
1. Internal 100-kΩ pull-down resistors present on inputs marked with *.
Design should not rely solely on internal pull-down resistors to set
I/O pins LOW.
x1/÷2
SIO/CPU3.3#_2.5
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134 •
408-943-2600
November 16, 2000, rev. *B
W207B
Pin Definitions
Pin Name
Pin No.
Pin Type
Pin Description
46, 45, 43
O
CPU Clock Outputs: See Tables 1 and 5 for detailed frequency information. Output voltage swing is controlled by voltage applied to VDDQ2.
PCI0/FS1
7
I/O
PCI Clock Outputs 0/Frequency Selection 1: PCI clock outputs. Output voltage
swing is controlled by voltage applied to VDDQ3. Shortly after initial power-up the
pin is sampled as an input to determine CPU, SDRAM, and PCI operating
frequencies.
PCI1/FS2
8
I/O
PCI Clock Outputs 1/Frequency Selection 2: PCI clock outputs. Output voltage
swing is controlled by voltage applied to VDDQ3. Shortly after initial power-up the
pin is sampled as an input to determine CPU, SDRAM, and PCI operating
frequencies.
9, 11, 12, 13,
14
O
PCI Clock Outputs 2 through 6: PCI clock outputs. Output voltage swing is
controlled by voltage applied to VDDQ3.
48MHz_2X/
FS0
26
I/O
48-MHz_2X Output/Frequency Select 0: 48 MHz is provided in normal operation. In standard systems, this output can be used as the reference for the Universal Serial Bus. This output has double drive strength. Upon power-up FS0 input
will be latched, which will set clock frequencies as described in Table 1. This output
does not have Spread Spectrum modulation.
SIO/
CPU3.3#_2.5
25
I/O
Super I/O Output/CPU Voltage Select: This output is used as the clock input for
Super I/O. Upon power-up its input will be latched. If the input is HIGH, CPU0:2
will be configured for 2.5V operations, otherwise they are configured for 3.3V.
REF1
48
O
Fixed 14.318 Output 1: This pin provides a fixed frequency signal determined by
the reference signal provided at the X1/X2 pins.
REF0_2X/FS3
2
I/O
Fixed 14.318 Output 0/Frequency Selection 3: This pin provides a fixed frequency signal determined by the reference signal provided at the X1/X2 pins. It has a
double drive strength output buffer. Shortly after initial power-up the pin is sampled
as an input to determine CPU, SDRAM, and PCI operating frequencies.
17, 18, 20,21,
28, 29, 31, 32,
34, 35, 37, 38,
40, 41
O
SDRAM Clock Outputs: These fourteen dedicated outputs provide the SDRAM
clocks for 3 memory DIMM. The swing is set by VDDQ3.
SCLK
24
I
Clock pin for SMBus circuitry.
SDATA
23
I/O
Data pin for SMBus circuitry.
X1
4
I
Crystal Connection or External Reference Frequency Input: This pin has dual
functions. It can be used as an external 14.318-MHz crystal connection or as an
external reference frequency input.
X2
5
I
Crystal Connection: An input connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
VDDQ3
1, 6, 15, 19,
27, 30, 36, 42
P
Power Connection: Power supply for core logic, PLL circuitry, SDRAM outputs,
PCI outputs, reference outputs, 48-MHz output, and SIO output. Connect to 3.3V
supply.
VDDQ2
47
P
Power Connection: Power supply for CPU0:2 output buffers. Connect to 2.5V, or
3.3V.
3, 10, 16, 22,
33, 39, 44
G
Ground Connections: Connect all ground pins to the common system ground
plane.
CPU0:2
PCI2:6
SDRAM0:13
GND
2
W207B
each l/O pin to pull the pin and its associated capacitive clock
load to either a logic HIGH or LOW state. At the end of the 2ms period, the established logic 0 or 1 condition of each l/O pin
is then latched. Next the output buffer is enabled, converting
all l/O pins into operating clock outputs. The 2-ms timer starts
when VDDQ3 reaches 2.0V. The input bits can only be reset by
turning VDDQ3 off and then back on again.
Overview
The W207B is a spread spectrum system timing generator designed to support SiS540 and 630 core logic chip sets. It is a
highly integrated device, providing clock outputs for CPU, core
logic, super I/O, PCI, and up to three SDRAM DIMMs.
Functional Description
It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive impedance of the clock outputs is < 40Ω (nominal) which is minimally
affected by the 10-kΩ strap to ground or VDDQ3. As with the
series termination resistor, the output strapping resistor should
be placed as close to the l/O pin as possible in order to keep
the interconnecting trace short. The trace from the resistor to
ground or VDDQ3 should be kept less than two inches in length
to prevent system noise coupling during input logic sampling.
I/O Pin Operation
Pins 2, 7, 8, 25, and 26 are dual-purpose l/O pins.
Upon power-up each I/O pin acts as a logic input, allowing the
determination of assigned device functions. A short time after
power-up, the logic state of each pin is latched and each pin
then becomes a clock output. This feature reduces device pin
count by combining clock outputs with input select pins.
When each clock output is enabled following the 2-ms input
period, target (normal) output frequency is delivered assuming
that VDDQ3 has stabilized. If VDDQ3 has not yet reached full
value, output frequency initially may be below target but will
increase to target once VDDQ3 voltage has stabilized. In either
case, a short output clock cycle may be produced from the
CPU clock outputs when the outputs are enabled.
An external 10-kΩ “strapping” resistor is connected between
each l/O pin and ground or VDDQ3. Connection to ground sets
a “0” bit, connection to VDDQ3 sets a “1” bit. Figure 1 and Figure
2 show two suggested methods for strapping resistor connection.
Upon W207B power-up, the first 2 ms of operation is used for
input logic selection. During this period, each clock output buffer is three-stated, allowing the output strapping resistor on
VDD
Output Strapping Resistor
10 kΩ
(Load Option 1)
Clock Load
W207B
Output
Buffer
Power-on
Reset
Timer
Series Termination Resistor
Hold
Output
Low
Output Three-state
Q
10 kΩ
(Load Option 0)
D
Data
Latch
Figure 1. Selection Through Resistor Load Option
3
W207B
Jumper Options
Output Strapping Resistor
VDD
Series Termination Resistor
10 kΩ
W207B
R
Output
Buffer
Power-on
Reset
Timer
Q
Resistor Value R
Hold
Output
Low
Output Three-state
Clock Load
D
Data
Latch
Figure 2. Input Logic Selection Through Jumper Option
pin X1 is used as the clock input and pin X2 is left open. The
input threshold voltage of pin X1 is (VDDQ3)/2.
CPU/PCI Frequency Selection
CPU frequency is selected with I/O pins 26, 7, 8, and 2
(48MHz_2X/FS0, PCI0/FS1, PCI1/FS2, and REF_2X/FS3, respectively). Refer to Table 1 for CPU/PCI frequency programming information. Alternatively, frequency selections are available through the serial data interface. Refer to Table 5 on page
8.
The internal crystal oscillator is used in conjunction with a
quartz crystal connected to device pins X1 and X2. This forms
a parallel resonant crystal oscillator circuit. The device incorporates the necessary feedback resistor and crystal load capacitors. Including typical stray circuit capacitance, the total
load presented to the crystal is approximately 18 pF. For optimum frequency accuracy without the addition of external capacitors, a parallel-resonant mode crystal specifying a load of
18 pF should be used. This will typically yield reference frequency accuracies within ±100 ppm. To achieve similar accuracies with a crystal calling for a greater load, external capacitors must be added such that the total load (internal, external,
and parasitic capacitors) equals that called for by the crystal.
Output Buffer Configuration
Clock Outputs
All clock outputs are designed to drive serial terminated clock
lines. The device outputs are CMOS-type which provide railto-rail output swing. To accommodate the limited voltage swing
required by some processors, the output buffers of CPU0:2
use a special VDDQ2 power supply pin that can be tied to 2.5V
nominal.
Dual Supply Voltage Operation
The device is designed for dual power supply operation. Supply pin VDDQ3 is connected to a 3.3V supply and supply power to the internal core circuit and to the clock output buffers,
except for outputs CPU0:2. Supply pins VDDQ2 may be connected to either a 2.5V or 3.3V supply, although device specifications may not be provided for both configurations.
Crystal Oscillator
The device requires one input reference clock to synthesize all
output frequencies. The reference clock can be either an externally generated clock signal or the clock generated by the
internal crystal oscillator. When using an external clock signal,
4
W207B
Clock device register changes are normally made upon system initialization, if any are required. The interface can also be
used during system operation for power management functions. Table 2 summarizes the control functions of the serial
data interface.
Serial Data Interface
The device features a two-pin, serial data interface that can be
used to configure internal register settings that control particular device functions. Upon power-up, the W207B initializes
with default register settings, therefore the use of this serial
data interface is optional. The serial interface is write-only (to
the clock chip) and is the dedicated function of device pins
SDATA and SCLK. In motherboard applications, SDATA and
SCLK are typically driven by two logic outputs of the chipset.
Operation
Data is written to the device in ten bytes of eight bits each.
Bytes are written in the order shown in Table 3.
Table 2. Serial Data Interface Control Functions Summary
Control Function
Description
Common Application
Clock Output Disable
Any individual clock output(s) can be disabled. Dis- Unused outputs are disabled to reduce EMI
abled outputs are actively held LOW.
and system power. Examples are clock outputs to unused SDRAM DIMM socket or PCI
slot.
CPU Clock Frequency
Selection
Provides CPU/PCI frequency selections beyond the
options that are provided by the frequency selection
pin power-on default selection. Frequency is
changed in a smooth and controlled fashion.
For alternate CPU devices, and power management options. Smooth frequency transition allows CPU frequency change under normal system operation.
Output Three-state
Puts all clock outputs into a high-impedance state.
Production PCB testing.
Test Mode
All clock outputs toggle in relation with X1 input,
internal PLL is bypassed. Refer to Table 4.
Production PCB testing.
(Reserved)
Reserved function for future device revision or pro- No user application. Register bit must be writduction device testing.
ten as 0.
Table 3. Byte Writing Sequence
Byte Sequence
Byte Name
Bit Sequence
Byte Description
1
Slave Address
11010010
Commands the device to accept the bits in Data Bytes 0–6 for internal
register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for
each potential receiver. The slave receiver address for the device is
11010010. Register setting will not be made if the Slave Address is not
correct (or is for an alternate slave receiver).
2
Command
Code
Don’t Care
Unused by the device, therefore bit values are ignored (“Don’t Care”).
This byte must be included in the data write sequence to maintain proper
byte allocation. The Command Code Byte is part of the standard serial
communication protocol and may be used when writing to another addressed slave receiver on the serial data bus.
3
Byte Count
Don’t Care
Unused by the device, therefore bit values are ignored (“Don’t Care”).
This byte must be included in the data write sequence to maintain proper
byte allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed
slave receiver on the serial data bus.
4
Data Byte 0
Refer to Table 4
5
Data Byte 1
6
Data Byte 2
The data bits in these bytes set internal W207B registers that control
device operation. The data bits are only accepted when the Address
Byte bit sequence is 11010010, as noted above. For description of bit
control functions, refer to Table 4, Data Byte Serial Configuration Map.
7
Data Byte 3
8
Data Byte 4
9
Data Byte 5
10
Data Byte 6
5
W207B
Writing Data Bytes
7. Table 4 gives the bit formats for registers located in Data
Bytes 0–6. Table 5 details additional frequency selections that
are available through the serial data interface.
Each bit in the data bytes controls a particular device function
except for the “reserved” bits, which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit
Table 4. Data Bytes 0–6 Serial Configuration Map
Affected Pin
Bit(s)
Pin No.
Pin Name
Bit Control
Control Function
0
1
Default
Data Byte 0
7
--
--
BYTE0_SEL3
Refer to Table 5
0
6
--
--
BYTE0 _SEL2
Refer to Table 5
0
5
--
--
BYTE0 _SEL1
Refer to Table 5
0
Refer to Table 5
0
4
--
--
BYTE0 _SEL0
3
--
--
FS0:3 override
2
--
--
BYTE0_SEL4
1
--
--
(Reserved)
--
--
1
0
--
--
Test Mode
Normal
Three-state all outputs
0
7
--
--
SI0_SEL
48 MHz
24 MHz
1
6
--
--
(Reserved)
--
--
0
5
--
--
(Reserved)
--
--
0
4
--
--
(Reserved)
--
--
0
3
43
CPU2
Clock Output Disable
Low
Active
1
2
45
CPU1
Clock Output Disable
Low
Active
1
1
46
CPU0
Clock Output Disable
Low
Active
1
0
--
--
(Reserved)
--
--
0
7
--
--
(Reserved)
--
--
0
6
14
PCI6
Clock Output Disable
Low
Active
1
5
13
PCI5
Clock Output Disable
Low
Active
1
4
12
PCI4
Clock Output Disable
Low
Active
1
3
11
PCI3
Clock Output Disable
Low
Active
1
2
9
PCI2
Clock Output Disable
Low
Active
1
1
8
PCI1
Clock Output Disable
Low
Active
1
0
7
PCI0
Clock Output Disable
Low
Active
1
7
32
SDRAM7
Clock Output Disable
Low
Active
1
6
31
SDRAM6
Clock Output Disable
Low
Active
1
5
29
SDRAM5
Clock Output Disable
Low
Active
1
4
28
SDRAM4
Clock Output Disable
Low
Active
1
3
21
SDRAM3
Clock Output Disable
Low
Active
1
2
20
SDRAM2
Clock Output Disable
Low
Active
1
1
18
SDRAM1
Clock Output Disable
Low
Active
1
Select operating frequency by FS 3:0
Select operating frequency by BYTE0_SEL
(3:0)
Refer to Table 5
0
0
Data Byte 1
Data Byte 2
Data Byte 3
6
W207B
Table 4. Data Bytes 0–6 Serial Configuration Map (continued)
Affected Pin
Bit(s)
Pin No.
Pin Name
0
17
SDRAM0
7
25
6
Bit Control
Control Function
0
1
Default
Clock Output Disable
Low
Active
1
SIO
Clock Output Disable
Low
Active
1
26
48MHz
Clock Output Disable
Low
Active
1
5
41
SDRAM13
Clock Output Disable
Low
Active
1
4
40
SDRAM12
Clock Output Disable
Low
Active
1
3
38
SDRAM11
Clock Output Disable
Low
Active
1
2
37
SDRAM10
Clock Output Disable
Low
Active
1
1
35
SDRAM9
Clock Output Disable
Low
Active
1
0
34
SDRAM8
Clock Output Disable
Low
Active
1
7
--
--
(Reserved)
--
--
0
5
--
--
(Reserved)
--
--
0
5
--
--
(Reserved)
--
--
0
4
--
--
(Reserved)
--
--
0
3
--
--
(Reserved)
--
--
0
2
--
--
(Reserved)
--
--
0
1
48
REF1
Clock Output Disable
Low
Active
1
0
2
REF0
Clock Output Disable
Low
Active
1
7
--
--
(Reserved)
--
--
0
6
--
--
(Reserved)
--
--
0
5
--
--
(Reserved)
--
--
0
4
--
--
(Reserved)
--
--
0
3
--
--
(Reserved)
--
--
0
2
--
--
(Reserved)
--
--
0
1
--
--
(Reserved)
--
--
0
Data Byte 4
Data Byte 5
Data Byte 6
7
W207B
Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes
Input Conditions
Output Frequency
Data Byte 0 Bit 3 = 1
Bit 2
SEL_4
Bit 7
SEL_3
Bit 6
SEL_2
Bit 5
SEL_1
Bit 4
SEL_0
0
0
0
0
0
66.6
100.0
33.3
–0.6%
0
0
0
0
1
100.2
100.2
33.4
±0.45%
0
0
0
1
0
150.3
100.2
37.6
OFF
0
0
0
1
1
133.6
100.2
33.4
±0.45%
0
0
1
0
0
66.8
111.3
33.4
OFF
0
0
1
0
1
100.2
133.6
33.4
±0.45%
0
0
1
1
0
100.2
150.3
33.4
OFF
0
0
1
1
1
133.3
133.3
33.3
–0.6%
0
1
0
0
0
66.6
66.6
33.3
–0.6%
0
1
0
0
1
83.3
83.3
31.2
OFF
0
1
0
1
0
97.0
97.0
32.3
–0.6%
0
1
0
1
1
95.0
95.0
31.7
±0.45%
0
1
1
0
0
95.0
126.7
31.7
OFF
0
1
1
0
1
112.0
112.0
37.3
OFF
0
1
1
1
0
122.0
91.5
30.5
–0.6%
0
1
1
1
1
122.0
122.0
30.5
–0.6%
1
0
0
0
0
66.8
100.2
33.4
OFF
1
0
0
0
1
100.0
100.0
33.3
–0.6%
1
0
0
1
0
96.2
96.2
32.1
OFF
1
0
0
1
1
133.3
100.0
33.3
–0.6%
1
0
1
0
0
75.0
100.0
37.5
OFF
1
0
1
0
1
83.3
124.9
41.6
OFF
1
0
1
1
0
105.0
140.0
35.0
OFF
1
0
1
1
1
133.6
133.6
33.4
OFF
1
1
0
0
0
110.0
146.7
36.7
OFF
1
1
0
0
1
166.0
110.7
33.2
OFF
1
1
0
1
0
166.0
120.0
33.2
OFF
1
1
0
1
1
95.0
95.0
31.7
–0.6%
1
1
1
0
0
140.0
140.0
35.0
OFF
1
1
1
0
1
145.0
145.0
36.2
OFF
1
1
1
1
0
97.0
129.3
32.33
–0.6%
1
1
1
1
1
160.0
160.0
32.0
OFF
CPU
8
SDRAM
PCI
Spread
Spectrum
W207B
Absolute Maximum Ratings
above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability.
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
.
Parameter
Description
Rating
Unit
V
VDD, VIN
Voltage on any pin with respect to GND
–0.5 to +7.0
–65 to +150
°C
0 to +70
°C
–55 to +125
°C
2 (min.)
kV
TSTG
Storage Temperature
TA
Operating Temperature
TB
Ambient Temperature under Bias
ESDPROT
Input ESD Protection
3.3V DC Electrical Characteristics (CPU3.3#_2.5 Input = 0)
TA = 0°C to +70°C, VDDQ3 = VDDQ2 = 3.3V±5% (3.135–3.465V)
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Supply Current
IDD
Combined 3.3V Supply Current
CPU0:2 =133 MHz
Outputs Loaded[2]
350
Logic Inputs (All referenced to VDDQ3 = 3.3V)
Input Low Voltage
VIL
mA
0.8
V
VIH
Input High Voltage
IIL
Input Low Current[3]
10
µA
IIH
Input High Current[3]
10
µA
50
mV
mA
2.0
V
Clock Outputs
VOL
Output Low Voltage
VOH
Output High Voltage
IOL
Output Low Current
IOL = 1 mA
IOH = –1 mA
3.1
VOL = 1.5V
55
75
105
SDRAM0:13
80
110
155
PCI0:6
55
75
105
REF0
60
75
90
REF1
45
60
75
55
75
105
55
85
125
SDRAM0:13
80
120
175
PCI0:6
55
85
125
REF0
60
85
110
CPU0:2
48 MHZ
IOH
Output High Current
CPU0:2
VOH = 1.5V
V
REF1
45
65
90
48 MHz
55
85
125
mA
Crystal Oscillator
VTH
X1 Input Threshold Voltage[4]
CLOAD
Load Capacitance, Imposed on
External Crystal[5]
CIN,X1
X1 Input Capacitance[6]
Pin X2 unconnected
1.65
V
18
pF
28
pF
Notes:
2. All clock outputs loaded with 6" 60Ω transmission lines with 22-pF capacitors.
3. W207B logic inputs have internal pull-up devices (pull-ups not full CMOS level).
4. X1 input threshold voltage (typical) is VDDQ3 /2.
5. The W207B contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is
18 pF; this includes typical stray capacitance of short PCB traces to crystal.
6. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
9
W207B
3.3V DC Electrical Characteristics (CPU3.3#_2.5 Input = 0)
TA = 0°C to +70°C, VDDQ3 = VDDQ2 = 3.3V±5% (3.135–3.465V) (continued)
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
5
pF
Pin Capacitance/Inductance
CIN
Input Pin Capacitance
Except X1 and X2
COUT
Output Pin Capacitance
6
pF
LIN
Input Pin Inductance
7
nH
0.3VDD
V
Serial Input Port
VIL
Input Low Voltage
VIH
Input High Voltage
IIL
Input Low Current
No internal pull-up/
down on SCLK
10
µA
IIH
Input High Current
No internal pull-up/
down on SCLK
10
µA
IOL
Sink Current into SDATA or SCLK,
Open Drain N-Channel Device On
IOL = 0.3VDD
CIN
Input Capacitance of SDATA and SCLK
10
pF
CSDATA
Total Capacitance of SDATA Bus
400
pF
CSCLOCK
Total Capacitance of SCLK Bus
400
pF
Max.
Unit
0.7VDD
V
6
mA
2.5V DC Electrical Characteristics (CPU3.3#_2.5 Input = 1)
TA = 0°C to +70°C, VDDQ3 = 3.3V±5% (3.135–3.456V), V DDQ2 = 2.5V±5% (2.375–2.625V)
Parameter
Description
Test Condition
Min.
Typ.
Supply Current
IDD-3.3V
Combined 3.3V Supply Current
CPU0:2 = 133 MHz
Outputs Loaded[2]
300
mA
IDD-2.5
Combined 2.5V Supply Current
CPU0:2= 133 MHz
Outputs Loaded[2]
50
mA
Logic Inputs
VIL
Input Low Voltage
VIH
Input High Voltage
0.8
2.0
V
V
IIL
[3]
Input Low Current
10
µA
IIH
Input High Current[3]
10
µA
50
mV
Clock Outputs
VOL
Output Low Voltage
IOL = 1 mA
VOH
Output High Voltage
IOH = –1 mA
3.1
VOH
Output High Voltage
CPU0:2
IOH = –1 mA
2.2
IOL
Output Low Current
CPU0:2
VOL = 1.25V
55
75
105
SDRAM0:13
VOL = 1.5V
60
75
90
PCI0:6
VOL = 1.5V
45
60
75
REF0
VOL = 1.5V
55
75
105
REF1
VOL = 1.5V
40
65
95
SIO
VOL = 1.5V
80
120
175
10
V
V
mA
W207B
2.5V DC Electrical Characteristics (CPU3.3#_2.5 Input = 1) (continued)
TA = 0°C to +70°C, VDDQ3 = 3.3V±5% (3.135–3.456V), V DDQ2 = 2.5V±5% (2.375–2.625V)
Parameter
IOH
Description
Output High Current
Min.
Typ.
Max.
Unit
CPU0:2
VOH = 1.25V
Test Condition
55
85
125
mA
SDRAM0:13
VOH = 1.5V
60
85
110
PCI0:6
VOH = 1.5V
45
65
90
REF0
VOH = 1.5V
55
85
125
REF1
VOH = 1.5V
45
70
105
SIO
VOH = 1.5V
80
110
155
3.3V AC Electrical Characteristics (CPU3.3#_2.5 Input = 0)
TA = 0°C to +70°C, VDDQ3 = VDDQ2 = 3.3V±5% (3.135–3.465V), fXTL = 14.31818 MHz
Spread Spectrum function turned off
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.
CPU Clock Outputs, (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/
Comments
CPU = 66.6 MHz
CPU = 100 MHz
CPU = 133 MHz
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
Unit
tP
Period
Measured on rising edge at
1.5V
15
10.0
7.5
ns
tH
High Time
Duration of clock cycle
above 2.4V
5.2
3.0
1.87
ns
tL
Low Time
Duration of clock cycle
below 0.4V
5
2.8
1.67
ns
tR
Output Rise
Edge Rate
Measured from 0.4V to
2.4V
1
4
1
4
1
4
V/ns
tF
Output Fall
Edge Rate
Measured from 2.4V to
0.4V
1
4
1
4
1
4
V/ns
tD
Duty Cycle
Measured on rising and
falling edge at 1.5V
45
55
45
55
45
55
%
tJC
Jitter,
Cycle-to-Cycle
Measured on rising edge at
1.5V. Maximum difference
of cycle time between two
adjacent cycles.
250
250
250
ps
tSK
Output Skew
Measured on rising edge at
1.5V
175
175
175
ps
fST
Frequency
Stabilization
from Power-up
(cold start)
Assumes full supply
voltage reached within 1
ms from power-up. Short
cycles exist prior to frequency stabilization.
3
3
3
ms
Zo
AC Output
Impedance
Average value during
switching transition. Used
for determining series
termination value.
30
Ω
15
11
20
30
15
20
30
15
20
W207B
SDRAM Clock Outputs, (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Test Condition/
Comments
SDRAM =
66.6 MHz
Min.
SDRAM =
100 MHz
Typ. Max. Min.
SDRAM =
133 MHz
Typ. Max. Min.
10.0
Typ. Max. Unit
tP
Period
Measured on rising edge at
1.5V
15
7.5
tR
Output Rise
Edge Rate
Measured from 0.4V to
2.4V
1
4
1
4
1
4
V/ns
tF
Output Fall
Edge Rate
Measured from 2.4V to
0.4V
1
4
1
4
1
4
V/ns
tD
Duty Cycle
Measured on rising and
falling edge at 1.5V
45
55
45
55
45
55
%
tJC
Jitter,
Cycle-to-Cycle
Measured on rising edge at
1.5V. Maximum difference
of cycle time between two
adjacent cycles.
250
ps
tSK
Output Skew
Measured on rising edge at
1.5V
tSK
CPU to SDRAM Covers all CPU/SDRAM
Clock Skew
outputs. Measured on
rising edge at 1.5V.
fST
Frequency
Stabilization
from Power-up
(cold start)
Assumes full supply
voltage reached within 1
ms from power-up. Short
cycles exist prior to frequency stabilization.
Zo
AC Output
Impedance
Average value during
switching transition. Used
for determining series
termination value.
250
250
175
10
12
15
ns
175
175
ps
500
500
500
ps
3
3
3
ms
20
Ω
20
10
15
20
10
15
W207B
PCI Clock Outputs, PCI0:6 (Lump Capacitance Test Load = 30 pF)
PCI = 33.3 MHz
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
30
Unit
tP
Period
Measured on rising edge at 1.5V
ns
f
Frequency, Actual
Determined by PLL divider ratio
tH
High Time
Duration of clock cycle above 2.4V
12
tL
Low Time
Duration of clock cycle below 0.4V
12
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
1
4
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
1
4
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
%
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two adjacent cycles.
500
ps
tSK
Output Skew
Measured on rising edge at 1.5V
500
ps
tO
CPU to PCI Clock Skew
Covers all 3V66/PCI outputs. Measured on rising
edge at 1.5V. CPU leads PCI output.
4
ns
fST
Frequency Stabilization
from Power-up (cold
start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequency
stabilization.
3
ms
Zo
AC Output Impedance
Average value during switching transition. Used for
determining series termination value.
20
30
Ω
Typ.
Max.
33.3
1
15
MHz
ns
ns
2
REF0_2X Clock Output (Lump Capacitance Test Load = 45 pF)
Parameter
Description
Test Condition/Comments
Min.
14.318
Unit
f
Frequency, Actual
Frequency generated by crystal oscillator
MHz
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
1
4
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
1
4
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
45
fST
Frequency Stabilization from
Power-up (cold start)
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
55
%
1.5
ms
17
20
25
Ω
Min.
Typ.
Max.
Unit
REF1 Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
f
Frequency, Actual
Frequency generated by crystal oscillator
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
1
4
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
1
4
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
%
fST
Frequency Stabilization from
Power-up (cold start)
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
1.5
ms
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
35
Ω
13
14.318
20
25
MHz
W207B
SIO Clock Outputs (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
f
Frequency, Actual
Determined by PLL divider ratio (see m/n below)
fD
Deviation from 48 MHz
m/n
Min.
Typ.
Max.
Unit
48.008
MHz
(48.008 – 48)/48
+167
ppm
PLL Ratio
(14.31818 MHz x 57/17 = 48.008 MHz)
57/17
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
fST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within 1
ms from power-up. Short cycles exist prior to
frequency stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
1
4
V/ns
1
4
V/ns
40
55
%
3
ms
30
Ω
15
20
Serial Input Port
Parameter
Description
Test Condition/Comments
Normal Mode
Min.
0
Typ.
Max.
Unit
100
kHz
fSCLOCK
SCLOCK Frequency
tSTHD
Start Hold Time
4.0
µs
tLOW
SCLOCK Low Time
4.7
µs
tHIGH
SCLOCK High Time
4.0
µs
tDSU
Data Set-up Time
250
ns
tDHD
Data Hold Time
(Transmitter should provide a 300-ns hold
time to ensure proper timing at the receiver.)
0
ns
tR
Rise Time, SDATA and
SCLOCK
From 0.3VDD to 0.7V DD
1000
ns
tF
Fall Time, SDATA and
SCLOCK
From 0.7VDD to 0.3V DD
300
ns
tSTSU
Stop Set-up Time
4.0
µs
tSPF
Bus Free Time between
Stop and Start Condition
4.7
µs
tSP
Allowable Noise Spike
Pulse Width
50
14
ns
W207B
2.5V AC Electrical Characteristics (CPU3.3#_2.5 Input = 1)
TA = 0°C to +70°C, VDDQ3 = 3.3V±5% (3.135–3.465V), V DDQ2= 2.5V±5% (2.375–2.625V),
fXTL = 14.31818 MHz
Spread Spectrum function turned off
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.
CPU Clock Outputs, (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/
Comments
CPU = 66.6 MHz
CPU = 100 MHz
CPU = 133 MHz
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
Unit
tP
Period
Measured on rising edge at
1.25V
15
10.0
7.5
ns
tH
High Time
Duration of clock cycle
above 2.0V
5.2
3.0
1.87
ns
tL
Low Time
Duration of clock cycle
below 0.4V
5
2.8
1.67
ns
tR
Output Rise
Edge Rate
Measured from 0.4V to
2.0V
0.8
3
0.8
3
0.8
3
V/ns
tF
Output Fall
Edge Rate
Measured from 2.0V to
0.4V
0.8
3
0.8
3
0.8
3
V/ns
tD
Duty Cycle
Measured on rising and
falling edge at 1.25V
45
55
45
55
45
55
%
tJC
Jitter,
Cycle-to-Cycle
Measured on rising edge at
1.25V. Maximum difference of cycle time between
two adjacent cycles.
250
250
250
ps
tSK
Output Skew
Measured on rising edge at
1.25V
175
175
175
ps
fST
Frequency Stabilization from
Power-up (cold
start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequency stabilization.
3
3
3
ms
Zo
AC Output
Impedance
Average value during
switching transition. Used
for determining series termination value.
30
Ω
12
20
30
12
20
30
12
Ordering Information
Ordering Code
W207B
Package Name
Package Type
H
48-pin SSOP (300 mils)
Document #: 38-00847-B
15
20
W207B
Package Diagram
48-Pin Small Shrink Outline Package (SSOP, 300 mils)
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.