PRELIMINARY W233 Spread Spectrum FTG for VIA Mobile K7 Chipset Features Table 1. Pin Selectable Frequency • Maximized EMI Suppression using Cypress’s Spread Spectrum technology • Single-chip system frequency synthesizer for VIA Mobile K7 chipset • Two copies of CPU output • Seven copies of PCI output • One 48-MHz output for USB • One 24-MHz or 48-MHz output for SIO • Three buffered reference outputs • Six SDRAM outputs provide support for three SODIMMs • Supports frequencies up to 166 MHz • SMBus interface for programming • Power management control inputs • Available in 48-pin SSOP Key Specifications Input Address FS3 FS2 FS1 FS0 CPU (MHz) PCI (MHz) Spread Spectrum 1 1 1 1 133.3 33.3 OFF 1 1 1 0 100.0 33.3 OFF 1 1 0 1 133.3 33.3 ±0.5% 1 1 0 0 100.0 33.3 ±0.5% 1 0 1 1 133.3 33.3 –0.5% 1 0 1 0 100.0 33.3 –0.5% 1 0 0 1 133.3 33.3 ±0.25% 1 0 0 0 100.0 33.3 ±0.25% 0 1 1 1 95.0 31.7 OFF 0 1 1 0 102.0 34.0 OFF 0 1 0 1 104.0 34.6 OFF CPU to CPU Output Skew: ......................................... 175 ps 0 1 0 0 106.0 35.3 OFF PCI to PCI Output Skew: ............................................ 500 ps 0 0 1 1 108.0 36.0 OFF VDD: .........................................................................3.3V±5% 0 0 1 0 110.0 36.6 OFF SDRAMIN to SDRAM0:5 Delay: ............................2.0 ns typ. 0 0 0 1 111.0 37.0 OFF 0 0 0 0 112.0 37.3 OFF Pin Configuration[1] Block Diagram VDD_REF X1 X2 XTAL OSC REF0_2X Stop Clock Control REF1 REF2/FS3* I/O Pin Control CPU_STOP# VDD_CPU CPU_CS CPUT0_F CPUC0_F PLL 1 VDD_PCI PCI_F/FS2 PCI0/FS1 PCI1 PCI2 PCI3 ÷2,3,4 Stop Clock Control PCI4 PCI_STOP# SDATA SCLK PCI5 PCI6 SMBus Logic VDD_48MHz 48MHz/FS0 PLL2 ÷2 SDRAM_STOP# SDRAMIN *SEL24_48#/24_48MHz Stop Clock Control 7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 W233 Stop Clock Control CLK_STOP# VDD_REF X1 X2 *FS2/PCI_F *FS1/PCI0 VDD_PCI GND_PCI PCI1 PCI2 PCI3 PCI4 PCI5 GND_PCI VDD_PCI PCI6 *SDRAM_STOP# *PCI_STOP# SDRAMIN VDD_CORE GND_CORE GND_48MHz *FS0/48MHz *SEL24_48#/24_48MHz VDD_48MHz 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 REF0_2X REF1 REF2/FS3* GND_REF GND_CPU VDD_CPU CPU_CS CPUT0_F CPUC0_F CPU_STOP#* STOP_CLK#* SDRAM0 SDRAM1 VDD_SDRAM GND_SDRAM SDRAM2 SDRAM3 GND_SDRAM VDD_SDRAM SDRAM4 SDRAM5 SDRAM_F SCLK SDATA Note: 1. Internal pull-up resistors should not be relied upon for setting I/O pins HIGH. VDD_SDRAM SDRAM0:5 SDRAM_F Cypress Semiconductor Corporation Document #: 38-07250 Rev. *A • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 21, 2002 PRELIMINARY W233 Pin Definitions Pin Name Pin No. Pin Type Pin Description 40, 41 O (opendrain) CPU Clock Output 0: CPUT0_F and CPUC0_F are the differential CPU clock outputs for the K7 processor. 42 O CPU Clock Output for Chipset: CPU_CS is the push-pull clock output for the chipset. It has the same phase relationship as CPUT0_F. 8, 9, 10, 11, 12, 15 O PCI Clock Outputs 1 through 6: These six PCI clock outputs are controlled by the PCI_STP# control pin. Frequency is set by FS0:3 inputs or through serial input interface, see Tables 1 and 5 for details. Output voltage swing is controlled by voltage applied to VDDQ3. FS1/PCI0 5 I/O Fixed PCI Clock Output/Frequency Select 1: As an output, frequency is set by FS0:3 inputs or through serial input interface. This pin also serves as a PCI_STP# strap option to determine device operating frequency as described in Table 1. FS2/PCI_F 4 I/O Fixed PCI Clock Output/Frequency Select 2: As an output, frequency is set by the FS0:3 inputs or through serial input interface, see Tables 1 and 5. This output is controlled by the STOP_CLK# input. This pin also serves as a poweron strap option to determine device operating frequency as described in Table 2. STOP_CLK# 38 I STOP_CLK# Input: LVTTL-compatible input that places the device in stopclock mode when held LOW. In stop-clock mode, CPUT0_F and CPUC0_F will be active and all the other output clocks will be driven LOW. STOP_CLK# is an asynchronous input. W233 will not complete the current clock cycle when STOP_CLK# is being driven LOW. 48MHz/FS0 22 I/O 48-MHz Output/Frequency Select 0: 48 MHz is provided in normal operation. In standard PC systems, this output can be used as the reference for the Universal Serial Bus host controller. This pin also serves as a power on strap option to determine device operating frequency as described in Table 1. SEL24_48#/24_ 48MHz 23 I/O 24_48-MHz Output/Frequency Select 24 or 48 MHz: In standard PC systems, this output can be used as the clock input for a Super I/O chip. The output frequency is controlled by Configuration Byte 3 bit[6] or SEL 24_48 MHz stop option. The default output frequency is 24 MHz. This pin also serves as a power-on strap option to determine device operating frequency. CPUC0_F, CPUT0_F, CPU_CS PCI1:6 REF1 47 I/O Reference Clock Output 1: 3.3V 14.318-MHz output clock. REF2/FS3 46 I/O Reference Clock Output 2/Frequency Select 3: 3.3V 14.318-MHz output clock. This pin also serves as a power-on strap option to determine device operating frequency. REF0_2X 48 O Reference Clock Output 0: 3.3V 14.318-MHz output clock with double drive strength. SDRAMIN 18 I Buffered Input Pin: The signal provided to this input pin is buffered to seven outputs (SDRAM0:5 & SDRAM_F). 37, 36, 33, 32, 29, 28, 27 O Buffered Outputs: These seven dedicated outputs provide copies of the signal provided at the SDRAMIN input. The swing is set by VDD, and they are deactivated when SDRAM_STOP# input is set LOW, except SDRAM_F. SCLK 26 I Clock pin for SMBus circuitry. SDATA 25 I/O Data pin for SMBus circuitry. X1 2 I Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. X2 3 O Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. SDRAM_STOP# 16 I SDRAM Stop Input: LVTTL compatible input that disables the SDRAM output clocks, except SDRAM_F. SDRAM0:5, SDRAM_F Document #: 38-07250 Rev. *A Page 2 of 16 PRELIMINARY W233 Pin Definitions (continued) Pin No. Pin Type Pin Description PCI_STOP# Pin Name 17 I PCI Stop Input: LVTTL compatible input that disables the PCI output clocks, except PCI_F. CPU_STOP# 39 I CPU Stop Input: LVTTL compatible input that disables the CPU output clocks, except CPUT0_F and CPUC0_F. VDD_REF, VDD_PCI, VDD_CORE, VDD_48MHz, VDD_SDRAM, VDD_CPU 1, 6, 14, 19, 24, 30, 35, 43 P Power Connection: Power supply for core logic, PLL circuitry, SDRAM outputs, PCI outputs, reference outputs, 48-MHz output, and 24_48-MHz output. Connect to 3.3V supply GND_PCI, GND_CORE, GND_48MHz, GND_SDRAM, GND_CPU, GND_REF 7, 13, 20, 21, 31, 34, 44, 45 G Ground Connections: Connect all ground pins to the common system ground plane. Document #: 38-07250 Rev. *A Page 3 of 16 PRELIMINARY Overview The W233 was developed as a single-chip device to meet the clocking needs of VIA K7 core logic chip sets. In addition to the typical outputs provided by a standard FTG, the W233 adds a seventh output buffer, supporting SDRAM DIMM modules in conjunction with the chipset. Cypress’s proprietary spread spectrum frequency synthesis technique is a feature of the CPU and PCI outputs. When enabled, this feature reduces the peak EMI measurements of not only the output signals and their harmonics, but also of any other clock signals that are properly synchronized to them. Functional Description I/O Pin Operation Pins 4, 5, 22, 23, and 46 are dual-purpose l/O pins. Upon power-up these pins act as logic inputs, allowing the determination of assigned device functions. A short time after powerup, the logic state of each pin is latched and the pins become clock outputs. This feature reduces device pin count by combining clock outputs with input select pins. An external 10-kΩ “strapping” resistor is connected between the l/O pin and ground or VDD. Connection to ground sets a latch to “0,” connection to VDD sets a latch to “1.” Figure 1 and Figure 2 show two suggested methods for strapping resistor connections. W233 Upon W233 power-up, the first 2 ms of operation is used for input logic selection. During this period, the five I/O pins (4, 5, 22, 23, 46) are three-stated, allowing the output strapping resistor on the l/O pins to pull the pins and their associated capacitive clock load to either a logic HIGH or LOW state. At the end of the 2-ms period, the established logic “0” or “1” condition of the l/O pin is latched. Next the output buffer is enabled converting the l/O pins into operating clock outputs. The 2-ms timer starts when VDD reaches 2.0V. The input bits can only be reset by turning VDD off and then back on again. It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive impedance of clock outputs is <40Ω (nominal), which is minimally affected by the 10-kΩ strap to ground or VDD. As with the series termination resistor, the output strapping resistor should be placed as close to the l/O pin as possible in order to keep the interconnecting trace short. The trace from the resistor to ground or VDD should be kept less than two inches in length to prevent system noise coupling during input logic sampling. When the clock outputs are enabled following the 2-ms input period, the specified output frequency is delivered on the pin, assuming that VDD has stabilized. If VDD has not yet reached full value, output frequency initially may be below target but will increase to target once VDD voltage has stabilized. In either case, a short output clock cycle may be produced from the CPU clock outputs when the outputs are enabled. VDD Output Strapping Resistor Series Termination Resistor 10 kΩ (Load Option 1) W233 Power-on Reset Timer Hold Output Low Output Three-state Q Clock Load R Output Buffer 10 kΩ (Load Option 0) D Data Latch Figure 1. Input Logic Selection Through Resistor Load Option Jumper Options Output Strapping Resistor VDD Series Termination Resistor 10 kΩ W233 R Output Buffer Power-on Reset Timer Hold Output Low Output Three-state Q Clock Load Resistor Value R D Data Latch Figure 2. Input Logic Selection Through Jumper Option Document #: 38-07250 Rev. *A Page 4 of 16 PRELIMINARY W233 Spread Spectrum Frequency Timing Generator Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured. The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 3. The output clock is modulated with a waveform depicted in Figure 4. This waveform, as discussed in “Spread Spectrum Clock Generation for the Reduction of Radiated Emissions” by Bush, Fessler, and Hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. The deviation selected for this chip is specified in Table 5. Figure 4 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices. As shown in Figure 3, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is: dB = 6.5 + 9*log10(P) + 9*log10(F) Spread Spectrum clocking is activated or deactivated by selecting the appropriate data bytes of the SMBus data stream. Refer to Table 5 for more details. EMI Reduction Typical Clock Amplitude (dB) Amplitude (dB) SSFTG Spread Spectrum Enabled NonSpread Speactrum Frequency Span (MHz) Down Spread Frequency Span (MHz) Center Spread Figure 3. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% FREQUENCY MAX (0%) MIN (–0.5%) Figure 4. Typical Modulation Profile Document #: 38-07250 Rev. *A Page 5 of 16 PRELIMINARY Serial Data Interface The W233 features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Upon power-up, the W233 initializes with default register settings, therefore the use of this serial data interface is optional. The serial interface is write-only (to the clock chip) and is the dedicated function of device pins SDATA and SCLOCK. In motherboard applications, SDATA and SCLOCK are typically driven by two logic outputs of the W233 chipset. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. Table 2 summarizes the control functions of the serial data interface. Operation Data is written to the W233 in eleven bytes of eight bits each. Bytes are written in the order shown in Table 3. Table 2. Serial Data Interface Control Functions Summary Control Function Description Common Application Clock Output Disable Any individual clock output(s) can be disabled. Dis- Unused outputs are disabled to reduce EMI abled outputs are actively held LOW. and system power. Examples are clock outputs to unused PCI slots. CPU Clock Frequency Selection Provides CPU/PCI frequency selections through software. Frequency is changed in a smooth and controlled fashion. For alternate microprocessors and power management options. Smooth frequency transition allows CPU frequency change under normal system operation. Spread Spectrum Enabling Enables or disables spread spectrum clocking. For EMI reduction. Output Three-state Puts clock output into a high impedance state. Production PCB testing. (Reserved) Reserved function for future device revision or pro- No user application. Register bit must be writduction device testing. ten as 0. Table 3. Byte Writing Sequence Byte Sequence Byte Name 1 Slave Address 11010010 Commands the W233 to accept the bits in Data Bytes 0–6 for internal register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. The slave receiver address for the W233 is 11010010. Register setting will not be made if the Slave Address is not correct (or is for an alternate slave receiver). 2 Command Code Don’t Care Unused by the W233, therefore bit values are ignored (“Don’t Care”). This byte must be included in the data write sequence to maintain proper byte allocation. The Command Code Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. 3 Byte Count Don’t Care Unused by the W233, therefore bit values are ignored (“Don’t Care”). This byte must be included in the data write sequence to maintain proper byte allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. 4 Data Byte 0 Refer to Table 4 5 Data Byte 1 6 Data Byte 2 The data bits in Data Bytes 0–7 set internal W233 registers that control device operation. The data bits are only accepted when the Address Byte bit sequence is 11010010, as noted above. For description of bit control functions, refer to Table 4, Data Byte Serial Configuration Map. 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 10 Data Byte 6 11 Data Byte 7 Document #: 38-07250 Rev. *A Bit Sequence Byte Description Page 6 of 16 PRELIMINARY Writing Data Bytes Each bit in the data bytes controls a particular device function except for the “reserved” bits, which must be written as a logic 0. Bits are written MSB (Most Significant Bit) first, which is bit W233 7. Table 4 gives the bit formats for registers located in Data Bytes 0–7. Table 5 details additional frequency selections that are available through the serial data interface. Table 4. Data Bytes 0–7 Serial Configuration Map Affected Pin Bit(s) Pin No. Bit Control Pin Name Control Function 0 1 Default -- -- 0 Data Byte 0 7 -- -- (Reserved) 6 -- -- SEL_2 See Table 5 0 5 -- -- SEL_1 See Table 5 0 4 -- -- SEL_0 3 -- -- Hardware/Software Frequency Select 2 -- -- SEL_4 See Table 5 1 1 -- -- SEL_3 See Table 5 0 0 -- -- 7 -- -- 6 -- -- 5 -- 4 -- See Table 5 Hardware 0 Software 0 Normal Three-stated 0 (Reserved) -- -- 0 (Reserved) -- -- 0 -- (Reserved) -- -- 0 -- (Reserved) -- -- 0 (Reserved) Data Byte 1 3 -- -- -- -- 0 2 42 CPU_CS Clock Output Disable Low Active 1 1 40 CPUC0_F Clock Output Disable High Active 1 0 41 CPUT0_F Clock Output Disable Low Active 1 7 15 PCI6 Clock Output Disable Low Active 1 6 12 PCI5 Clock Output Disable Low Active 1 5 11 PCI4 Clock Output Disable Low Active 1 4 10 PCI3 Clock Output Disable Low Active 1 3 9 PCI2 Clock Output Disable Low Active 1 2 8 PCI1 Clock Output Disable Low Active 1 1 5 PCI0 Clock Output Disable Low Active 1 0 4 PCI_F Clock Output Disable Low Active 1 7 -- -- -- -- 0 6 -- 24-MHz 48-MHz 0 5 22 48MHz Clock Output Disable Low Active 1 4 23 24_48MHz Clock Output Disable Low Active 1 Data Byte 2 Data Byte 3 (Reserved) SEL_24MHz SEL 24MHz as the output frequency for 24_48MHz 3 27 SDRAM_F Clock Output Disable Low Active 1 2 29, 28 SDRAM4:5 Clock Output Disable Low Active 1 1 33, 32 SDRAM2:3 Clock Output Disable Low Active 1 Document #: 38-07250 Rev. *A Page 7 of 16 PRELIMINARY W233 Table 4. Data Bytes 0–7 Serial Configuration Map (continued) Affected Pin Bit(s) Pin No. Pin Name 0 37, 36 SDRAM0:1 Bit Control Control Function Clock Output Disable 0 1 Default Low Active 1 Data Byte 4 7 -- -- (Reserved) -- -- 0 6 -- -- (Reserved) -- -- 0 5 -- -- (Reserved) -- -- 0 4 -- -- (Reserved) -- -- 0 3 -- -- (Reserved) -- -- 0 2 -- -- (Reserved) -- -- 0 1 -- -- (Reserved) -- -- 0 0 -- -- (Reserved) -- -- 0 7 -- -- (Reserved) -- -- 0 6 -- -- (Reserved) -- -- 0 5 -- -- (Reserved) -- -- 0 4 -- -- (Reserved) -- -- 0 3 -- -- (Reserved) -- -- 0 2 46 REF2 Low Active 1 1 47 REF1 Clock Output Disable Low Active 1 0 48 REF0_2X Clock Output Disable Low Active 1 7 -- -- (Reserved) -- -- 0 6 -- -- (Reserved) -- -- 0 5 -- -- (Reserved) -- -- 0 4 -- -- (Reserved) -- -- 0 3 -- -- (Reserved) -- -- 0 2 -- -- (Reserved) -- -- 0 1 -- -- (Reserved) -- -- 0 0 -- -- (Reserved) -- -- 0 7 -- -- (Reserved) -- -- 0 6 -- -- (Reserved) -- -- 0 5 -- -- (Reserved) -- -- 0 4 -- -- (Reserved) -- -- 0 3 -- -- (Reserved) -- -- 0 2 -- -- (Reserved) -- -- 0 1 -- -- (Reserved) -- -- 0 0 -- -- (Reserved) -- -- 0 Data Byte 5 Clock Output Disable Data Byte 6 Data Byte 7 Document #: 38-07250 Rev. *A Page 8 of 16 PRELIMINARY W233 Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes Input Conditions Output Frequency Data Byte 0, Bit 3 = 1 Bit 2 SEL_4 Bit 1 SEL_3 Bit 6 SEL_2 Bit 5 SEL_1 Bit 4 SEL_0 CPU PCI Spread Spectrum 1 1 1 1 1 133.3 33.3 OFF 1 1 1 1 0 100.0 33.3 OFF 1 1 1 0 1 133.3 33.3 ±0.5% 1 1 1 0 0 100.0 33.3 ±0.5% 1 1 0 1 1 133.3 33.3 –0.5% 1 1 0 1 0 100.0 33.3 –0.5% 1 1 0 0 1 133.3 33.3 ±0.25% 1 1 0 0 0 100.0 33.3 ±0.25% 1 0 1 1 1 95.0 31.7 OFF 1 0 1 1 0 102.0 34.0 OFF 1 0 1 0 1 104.0 34.6 OFF 1 0 1 0 0 106.0 35.3 OFF 1 0 0 1 1 108.0 36.0 OFF 1 0 0 1 0 110.0 36.6 OFF 1 0 0 0 1 111.0 37.0 OFF 1 0 0 0 0 112.0 37.3 OFF 0 1 1 1 1 113.0 37.6 OFF 0 1 1 1 0 114.0 38.0 OFF 0 1 1 0 1 115.0 38.3 OFF 0 1 1 0 0 116.0 38.6 OFF 0 1 0 1 1 118.0 39.3 OFF 0 1 0 1 0 120.0 40.0 OFF 0 1 0 0 1 124.0 31.0 OFF 0 1 0 0 0 127.0 31.7 OFF 0 0 1 1 1 130.0 32.5 OFF 0 0 1 1 0 136.0 34.0 OFF 0 0 1 0 1 140.0 35.0 OFF 0 0 1 0 0 145.0 36.2 OFF 0 0 0 1 1 150.0 37.5 OFF 0 0 0 1 0 155.0 38.7 OFF 0 0 0 0 1 160.0 40.0 OFF 0 0 0 0 0 166.0 41.6 OFF Document #: 38-07250 Rev. *A Page 9 of 16 PRELIMINARY W233 Absolute Maximum Ratings[2] Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. . Parameter Description Rating Unit VDD, VIN Voltage on any pin with respect to GND –0.5 to +7.0 V TSTG Storage Temperature –65 to +150 °C TB Ambient Temperature under Bias –55 to +125 °C TA Operating Temperature 0 to +70 °C ESDPROT Input ESD Protection 2 (min.) kV DC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V±5% Parameter Description Test Condition Min. Typ. Max. Unit Supply Current IDD 3.3V Supply Current CPUT0_F, CPUC0_F, CPU_CS =100 MHz Outputs Loaded[3] 260 mA IDD 2.5V Supply Current CPUT0_F, CPUC0_F, CPU_CS =100 MHz Outputs Loaded[3] 25 mA Logic Inputs VIL Input Low Voltage GND – 0.3 0.8 2.0 V VIH Input High Voltage VDD + 0.3 V IIL Input Low Current[4] –25 µA IIH Input High Current[4] 10 µA 50 mV Clock Outputs VOL Output Low Voltage IOL = 1 mA VOH Output High Voltage IOH = –1 mA VOL Output Low Voltage CPU_CS, CPUT0_F, CPUC0_F Termination to V pull-up (external) 0 0.3 V VOH Output High Voltage CPU_CS, CPUT0_F, CPUC0_F Termination to V pull-up (external) 1.0 1.2 V IOL Output Low Current PCI0:6, PCI_F VOL = 1.5V 70 110 135 mA REF0:2 VOL = 1.5V 50 70 100 mA 48 MHz VOL = 1.5V 50 70 100 mA 24 MHz VOL = 1.5V 50 70 100 mA SDRAM0:5, SDRAM_F VOL = 1.5V 70 110 135 mA PCI0:6, PCI_F VOH = 1.5V 70 110 135 mA REF0:2 VOH = 1.5V 50 70 100 mA 48 MHz VOH = 1.5V 50 70 100 mA 24 MHz VOH = 1.5V 50 70 100 mA SDRAM0:5, SDRAM_F VOH = 1.5V 70 110 135 mA IOH Output High Current 3.1 V Notes: 2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 3. All clock outputs loaded with 6" 60Ω transmission lines with 20-pF capacitors. 4. W233 logic inputs (except FS3) have internal pull-up devices (pull-ups not full CMOS level). Logic input FS3 has an internal pull-down device. Document #: 38-07250 Rev. *A Page 10 of 16 PRELIMINARY W233 DC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V±5% (continued) Parameter Description Test Condition Min. Typ. Max. Unit Crystal Oscillator VTH X1 Input Threshold Voltage[5] CLOAD Load Capacitance, Imposed on External Crystal[6] CIN,X1 X1 Input Capacitance[7] VDDQ3 = 3.3V Pin X2 unconnected 1.65 V 14 pF 28 pF Pin Capacitance/Inductance CIN Input Pin Capacitance Except X1 and X2 5 pF COUT Output Pin Capacitance 6 pF LIN Input Pin Inductance 7 nH AC Electrical Characteristics TA = 0°C to +70°C, VDD = 3.3V±5%, fXTL = 14.31818 MHz AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output; Spread Spectrum is disabled. CPU Clock Outputs (CPU_CS)[8] CPU = 100 MHz Parameter Description Test Condition/Comments Min. Typ. Max. CPU = 133 MHz Min. Typ. Max. Unit tR Output Rise Edge Rate 1.0 1.0 V/ns tF Output Fall Edge Rate 1.0 1.0 V/ns tD Duty Cycle 50 50 % tJC Jitter, Cycle to Cycle 200 200 ps fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 3 ms Zo AC Output Impedance VO = VX 50 50 Ω Measured at 50% point Notes: 5. X1 input threshold voltage (typical) is VDD/2. 6. The W233 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF; this includes typical stray capacitance of short PCB traces to crystal. 7. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected). 8. Refer to Figure 5 for K7 operation clock driver test circuit. Document #: 38-07250 Rev. *A Page 11 of 16 PRELIMINARY W233 PCI Clock Outputs (Lump Capacitance Test Load = 30 pF Parameter Description Test Condition/Comments Min. Typ. Max. Unit tP Period Measured on rising edge at 1.5V 30 ns tH High Time Duration of clock cycle above 2.4V 12 ns tL Low Time Duration of clock cycle below 0.4V 12 ns tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 tF Output Fall Edge Rate Measured from 2.4V to 0.4V tD Duty Cycle Measured on rising and falling edge at 1.5V tJC Jitter, Cycle-to-Cycle tSK 4 V/ns 1 4 V/ns 45 55 % Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. 250 ps Output Skew Measured on rising edge at 1.5V 500 ps tO CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output. 4 ns fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 1.0 1.7 Ω 30 REF Clock Outputs (Lump Capacitance Test Load = 20 pF) Parameter Description f Frequency, Actual Test Condition/Comments Min. Frequency generated by crystal oscillator Typ. Max. 14.318 Unit MHz tR Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. Ω 40 48-MHz Clock Output (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments f Frequency, Actual Determined by PLL divider ratio (see m/n below) fD Deviation from 48 MHz (48.008 – 48)/48 Min. Typ. Max. Unit 48.008 MHz +167 ppm m/n PLL Ratio (14.31818 MHz x 57/17 = 48.008 MHz) tR Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. Document #: 38-07250 Rev. *A 57/17 40 Ω Page 12 of 16 PRELIMINARY W233 24-MHz Clock Output (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments Min. f Frequency, Actual Determined by PLL divider ratio (see m/n below) fD Deviation from 24 MHz (24.004 – 24)/24 Typ. Max. Unit 24.004 MHz +167 ppm m/n PLL Ratio (14.31818 MHz x 57/34 = 24.004 MHz) tR Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 57/34 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 40 Ω VDD + V1 1.5V 3.3 Z0 = 52Ω Length = 5” T1 R1 68 Z0 = 52Ω Length = 3” T2 R8 CPUCLK_T 47 20p 1.5V Clock Chip CPUDriver R3 68 Z0 = 52Ω Length = 5” T4 Z0 = 52Ω Length = 3” T5 R9 CPUCLK_C 47 20p Figure 5. K7 Open Drain Clock Driver Test Circuit Ordering Information Ordering Code Package Name W233 Document #: 38-07250 Rev. *A H Package Type 48-pin SSOP (300 mils) Page 13 of 16 PRELIMINARY W233 Layout Diagram +3.3V Supply FB VDDQ3 C4 G G G 3.3 V 10Ω C5 G 10 µF G G C3 V 1 VCore G 2 3 G 4 5 G 6 V 7 G 8 9 G 10 11 12 13 G 14 V 15 G 16 17 18 G 19 V 20 G 21 G 22 23 24 G DDQ3 48 47 46 45 G 44 V 43 G 42 41 40 39 38 37 G 36 V 35 G 34 33 32 G 31 V 30 G 29 28 27 26 G 25 G W233 G 0.005 µF G G G G C6 FB = Dale ILB1206 - 300 (300Ω @ 100 MHz) or TDK ACB2012L-120 Ceramic Caps C3 & C5 = 10–22 µF C4 = 0.005 µF G = VIA to GND plane layer C6 = 0.1 µF V =VIA to respective supply plane layer Note: Each supply plane or strip should have a ferrite bead and capacitors. All VDD by passes = 0.1 µF Document #: 38-07250 Rev. *A Page 14 of 16 PRELIMINARY W233 Package Diagram 48-Pin Small Shrink Outline Package (SSOP, 300 mils) Summary of nominal dimensions in inches: Body Width: 0.296 Lead Pitch: 0.025 Body Length: 0.625 Body Height: 0.102 Document #: 38-07250 Rev. *A Page 15 of 16 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY W233 Document Title: W233 Spread Spectrum FTG for VIA Mobile K7 Chipset Document Number: 38-07250 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 110515 01/07/02 SZV Change from Spec number: 38-01037 to 38-07250 *A 122855 12/21/02 RBI Add Power up Requirements to Absolute Maximum Ratings Information. Document #: 38-07250 Rev. *A Page 16 of 16