W58300 Voice Synthesizer (ROM-LESS High Fidelity PowerSpeechTM) GENERAL DESCRIPTION The High Fidelity PowerSpeechTM family is a new member of the PowerSpeechTM synthesizer series, with voice quality which is even better than before. The W58300 is a ROMless chip that can support up to maximal 16M bits memory size; the voice length can reach 8.5 minutes. Combined with flash memory W55Fxx, this chip can be used to demonstrate real chip function before mass-production. This family has adopted the same architecture as the PowerSpeechTM synthesizers while replacing the 4-bit ADPCM algorithm with Winbond′s high fidelity synthesis algorithm to produce better quality voice. W58300 provides hardware Infrared(IR) circuit, CPU interface and voice output in D/A converter (DAC) or PWM type. FEATURES • Programmable voice synthesizer • Proprietary synthesis algorithm • Direct drive speaker by PWM output or by 8-bit DAC with external transistor • Wide operating voltage range: 2.4−5.5 Volts • Addressing capability up to 16M bits • IR interface for command Transmission and Receiving • TX, INC and MV instruction provided • 8 trigger inputs - with separate control of falling/rising edge trigger • 8 STOP outputs • Supports CPU interface operation • Pad option for Ring or Crystal oscillator • Symbolic compiler supported • Instruction cycle ≤ 400 µS typically • Section control − Variable frequency: 4.8/6/8/12 KHz − LED: ON/OFF • Eight general-purpose registers R0−R7 • Number of interrupt vector/label up to 2,048 -1- Publication Release Date: March 1999 Revision A2 W58300 BLOCK DIAGRAM RESET OSC/X IN OSCO/X OUT SEL V DDE TIMING GENERATOR EXTERNAL MEMORY INTERFACE CIRCUIT TG1 : WRP RDP DISOTP TG3/IRIN : TG8 MDPCM SYNTHESIZER STPA/BUSY DATA CONTROLLER STPB LED2/STPC : STPH D/A CONVERTER LED1 PWM DRIVER IROUT VDD VSS TEST AUD/SPK+ SPK- PIN CONFIGURATION RDP DATA WRP V DDE TG1 TG2 TG3/IRIN TG4 TG5 1 2 3 4 5 6 7 8 9 TG6 TG7 TG8 OSC/XIN 10 11 12 13 OSCO/XOUT SEL VDD 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 -2- DISOTP TEST RESET IROUT STPA/BUSY STPB LED2/STPC STPD STPE STPF STPG STPH LED1 Vss SPKAUD/SPK+ W58300 PIN DESCRIPTION NAME I/O DESCRIPTION TG1 TG2 I I Direct trigger input 1, internally pulled high Direct trigger input 2, internally pulled high TG3/IRIN I TG4 TG5 TG6 I I I Direct trigger input 3 or IR input, internally pulled high. Once this pin is pulled low, the oscillation circuit will be active, even in the standby mode. Direct trigger input 4, internally pulled high Direct trigger input 5, internally pulled high Direct trigger input 6, internally pulled high TG7 TG8 I I Direct trigger input 7, internally pulled high Direct trigger input 8, internally pulled high LED1 STPA/BUSY O O LED1 output Stop signal A or Busy signal STPB LED2/STPC STPD STPE STPF STPG STPH IROUT O O O O O O O O Stop signal B LED2 output or Stop signal C Stop signal D Stop signal E Stop signal F Stop signal G Stop signal H IR signal output pin, active low VSS RESET I Negative power supply Reset all, functions as POR, internally pulled high AUD/SPK+ SPK- O O Current type output or PWM output for speaker PWM output VDDE VDD OSC/XIN I Positive power supply for serial interface Positive power supply Ring oscillator input or crystal input OSCO/XOUT SEL O I TEST RDP I O Ring oscillator clock output or crystal clock output Ring/Crystal oscillator select, internally pulled high. Floating for Ring and grounded for crystal. Test pin, internally pulled low READ pulse clock output for serial interface DATA WRP I/O O I DATA pin for the serial interface WRITE pulse clock output for serial interface Disable all of the serial interface pins DISOTP FUNCTIONAL DESCRIPTION -3- Publication Release Date: March 1999 Revision A2 W58300 The High Fidelity PowerSpeechTM is a derivative of Winbond's PowerSpeechTM synthesizers, which are becoming dominant in the consumer market, especially for toy applications. There are 8 trigger inputs and 8 STOP outputs in W58300. The maximal number of software key pad by scanning matrix is up to 8 × 9 = 72 keys. There are 8 general purpose registers, R0−R7. R0−R7 can apply not only for "LD" and "JP" instruction but also for "MV" instruction. Only R0 can apply for "INC" instruction. CPU interface is the same as the W581xx series. IR interface is a new feature in PowerSpeechTM. You can use IR interface to transmit and receive a command. For example, when X chip executes the "TX R1" instruction, the Pulse Position Modulation waveform (with 38 KHz carrier) outputs from IROUT pin to drive a photo diode. Y chips within a certain distance will receive the IR signal through an IR receiver module to TG3 pin and execute a "JP" to the interrupt vector/label pointed by R1 of X chip. There are two kinds of events that can cause the W58300 to enter the POI (Power On Initialization) process: one is power on, and the other is direct trigger from RESET pin. The interrupt vector "32" is allocated for this special event, and has the 1st priority, i.e., no triggers can override the POI process if they all happen simultaneously. So the user can write a program in this interrupt vector to set the power on initial state. If the user does not wish to execute a program on power on, he should write an "END" instruction in interrupt vector "32". During the POI process, triggers can then override it successfully; if the EN0, EN1 and MODE0, MODE1 registers are set properly. If more than two events happen simultaneously, the priority that is set by the internal H/W is: POI > TG1F > TG1R > TG2F > TG2R > TG3F > TG3R > TG4F > TG4R > TG5F > TG5R > TG6F > TG6R > TG7F > TG7R > TG8F > TG8R > "JP" instruction. Register Definition and Control The register file of the W58300 is composed of 14 registers, including 8 general purpose registers and 6 special purpose registers. They are defined to facilitate the operations for various purposes. The default setting values of the registers are given in the following table. REGISTER General Register Special Register NAME DEFAULT SETTING R0−R7 00100000B EN0, EN1 11111111B MODE0, MODE1 11111111B STOP 11111111B PAGE 00000000B 1. MODE0 Register BIT 7 DESCRIPTION LED Mode DEFINITION 1: Flash 0: DC -4- W58300 1. MODE0 Register, continued BIT 6 5 DESCRIPTION DEFINITION LED2/STPC 1: LED2 Output Pin Selection 0: STPC Output IR Output Source 1: Hardware Control IR Output 0: STPC Control IR Output 4 Debounce Time 1: Long 0: Short 3, 1, 0 2 Reserved - STPA/BUSY 1: STPA Output Pin Selection 0: BUSY Output MODE0.7 controls the output type of LED1 (and LED2) pin. MODE0.6 controls the configuration of LED2/STPC pin. MODE0.5 controls the output source of IR. If hardware control IR output is selected, IR output can have signal with carrier or without carrier which is selected by MODE1.0. MODE0.4 controls the trigger pin debounce time. MODE0.2 controls the behavior of the STPA/BUSY pin which is usually used as Busy signal in CPU mode. 2. MODE1 Register BIT 7, 6, 1 5 DESCRIPTION DEFINITION Reserved - LED Flash Type 1: Alternate 0: Synchronous 4 3 LED1 Section 1: YES Control 0: NO LED2 Control 1: Section Control 0: STPC Control 2 0 LED1 Volume 1: OFF Control 0: ON IR Output Format 1: IR Output Carrier with Duty Cycle 75% 0: IR Output Without Carrier MODE1.5 is for LED flash type control. MODE1.4 is for LED1 section control ON/OFF. MODE1.3 is for LED2 Section/STPC control. MODE1.2 is for LED1 volume control. MODE1.0 is for IR output with or without carrier and this bit is useful only MODE0.5 is "1". For STPC control IR output (MODE0.5 is 0), the IR output always has 38 KHz carrier signal no matter what the setting of MODE1.0 is. -5- Publication Release Date: March 1999 Revision A2 W58300 3. PAGE Register BIT 7 6 5 4 3 2 1 0 PAGE - - - PG4 PG3 PG2 PG1 PG0 Bits 5−7 of PAGE register are reserved; bits 0−4 are used for page selection. The user must set the page mode configuration described in the Option Control declaration. Once the page mode is decided, the working page is selected by the bits 0−4 of PAGE register. Hence, the user can execute "LD PAGE, value" instruction to change the working page of the interrupt vector/label. Not all of the bits 0−4 of PAGE register are used in different page mode; they are listed below. PAGE MODE PG4 PG3 PG2 PG1 PG0 1-page × × × × × 8-page × × √ √ √ 16-page × √ √ √ √ 32-page √ √ √ √ √ Where "×" means don′t care and "√" means must be set properly. 4. EN0, EN1 Registers BIT 7 6 5 4 3 2 1 0 EN0 TG4R TG3R TG2R TG1R TG4F TG3F TG2F TG1F EN1 TG8R TG7R TG6R TG5R TG8F TG7F TG6F TG5F A "1" means "enabled", while a "0" means "disabled" for that edge of the particular TG pin. For example, the instruction "LD EN0, 0x0F" enables all the falling edge triggers of TG1−TG4, while disabling all the rising edge triggers of TG1−TG4. The user can modify the EN0 and EN1 registers during operation of the W58300 to achieve various kinds of trigger functions, like retriggerable or not, one shot or level hold play mode, etc. That is to say, users can change the contents of EN0, EN1 register during synthesis at will to determine which trigger pin is to be enabled or disabled for its falling/rising edge. 5. STOP Register BIT 7 6 5 4 3 2 1 0 STOP STH STG STF STE STD STC STB STA The STOP register is used to control the status of the STPA−STPH pins. For example, STB = 1 means that pin is in high state and STB = 0 means low state. 6. R0− − R7 Registers These eight registers are general purpose registers. They can be used to hold interrupt vector/label. R0 is a special register which can be incremented by "INC" instruction. -6- W58300 Option Control Function There are four types of option that can be determined by a declaration in the user′s program file, but can not be controlled by register. FUNCTION OPTION CONTROL DECLARATION DEFPAGE 1 DEFINITION Operation Mode Oscillator NORMAL CPU OSC_3MHz 256 interrupt vector/label for 1 page, 1 page in total (1page mode) 256 interrupt vector/label for 1 page, 8 pages in total (8page mode) 128 interrupt vector/label for 1 page, 16 pages in total (16page mode) 64 interrupt vector/label for 1 page, 32 pages in total (32page mode) Normal mode operation CPU mode operation 3 MHz oscillator Frequency Voice Output Type OSC_1.5MHz VOUT_DAC VOUT_PWM 1.5 MHz oscillator DAC (AUD) output PWM output Page Mode DEFPAGE 8 Configuration DEFPAGE 16 DEFPAGE 32 "DEFPAGE" decides the page operation mode of W58300. The default setting of the page mode is 1page mode. The 8-page, 16-page or 32-page mode must be declared in order to reach the interrupt vector/label from 256 to 2047 when the interrupt vector/label is beyond 0−255. The W58300 can communicate with an external microprocessor through the simple serial CPU interface, which is the same as the W581xx series. The CPU interface consists of the TG1, TG2, and STPA/BUSY pins. "NORMAL" and "CPU" decide whether the operation mode of W58300 will be normal mode or CPU mode. "OSC_3MHz" and "OSC_1.5MHz" select the frequency of the system clock. "VOUT_DAC" and "VOUT_PWM" select the voice output type. OSC_1.5MHz is recommended. Interrupt Vector Allocation The W58300 provides a total of 8 trigger inputs to communicate with the outside world. Each trigger pin can invoke 2 dedicate interrupt vectors depending on TG pin status. The table below show the relationship between TG pin status and interrupt vectors. INTERRUPT VECTORS 0 1 2 3 TRIGGER STATUS TG1F TG2F TG3F TG4F INTERRUPT VECTORS 8 9 10 11 TRIGGER STATUS TG5F TG6F TG7F TG8F Continued -7- Publication Release Date: March 1999 Revision A2 W58300 INTERRUPT VECTORS 4 5 6 7 32 INTERRUPT VECTORS 12 13 14 15 - TRIGGER SOURCE TG1R TG2R TG3R TG4R POI TRIGGER SOURCE TG5R TG6R TG7R TG8R - Instruction Set There are two types of instruction in W58300, unconditional and conditional instructions. The first type of instructions are executed immediately after they are issued. The second type of instructions are executed only when the conditions specified in the instruction are satisfied. All the instructions are listed in the following table. The cycle time for each instruction is 2/Sampling Frequency(Fs). For Fs = 6.0 KHz, the cycle time is 333 µS. UNCONDITIONAL CONDITIONAL JP G JP G @STS JP Rn JP Rn @STS LD ENi, Value LD ENi, Value @STS LD MODEi, Value LD MODEi, Value @STS LD STOP, Value LD STOP, Value @STS LD PAGE, Value LD PAGE, Value @STS LD Rn, Value LD Rn, Value @STS END MV END Rn, Rm INC TX MV @STS Rn, Rm INC Rn TX @STS @STS Rn @STS Legend: G: Interrupt vector/label Rn: R0−R7 Rm: R0−R7 ENi: EN0, EN1 MODEi: MODE0, MODE1 Value: 8-bit data @STS can be the following: @TGn_HIGH for n = 1−8, @TGn_LOW for n = 1−8, @LAST. ABSOLUTE MAXIMUM RATINGS -8- W58300 PARAMETER Power Supply Input Voltage Storage Temp. Operating Temp. SYMBOL VDD−VSS VIN TSTG TOPR CONDITIONS All Inputs - RATED VALUE UNIT V V -0.3 − +7.0 VSS -0.3 − VDD +0.3 -55 − +150 0 − +70 °C °C Note: Operating the device under conditions beyond those indicated above may cause permanent damage or affect device reliability. ELECTRICAL CHARACTERISTICS (TA = 25°C, VSS = 0V, VDD = 4.5V unless otherwise specified.) DC Characteristics PARAMETER Operating Voltage Input Voltage Standby Current SYM. VDD VIL VIH ISB1 CONDITIONS MIN. 2.4 VSS -0.3 0.7 × VDD TYP. 3.0 - MAX. 5.5 0.3 × VDD VDD 1 UNIT V V 1 µA 500 1 600 1.2 -8 µA mA µA mA µA µA IOP1 IOP2 IOP3 IOP4 IIN1 VDD = 3V, All I/O Pins Unconnected, No Playing VDD = 5V, All I/O Pins Unconnected, No Playing VDD = 3V, No Load VDD = 5V, No Load VDD = 3V, No Load VDD = 5V, No Load VDD = 3V, VIN = 0V IIN2 VDD = 3V, VIN = 3V 50 µA IIN3 VDD = 3V, VIN = 0V -8 µA SEL, RESET and DISOTP SPK (D/A Full Scale) IDAC -6.0 mA Output Current of STPA−STPH Output Current of IOL1 IOH1 IOL2 VDD = 4.5V, Rl = 100 Ω VDD = 3V, VOUT = 0.4V VDD = 3V, VOUT = 2.7V SPK+, SPKOutput Current of WRP, RDP and DATA IOH2 IOL3 IOH3 ISB2 Operating Current ( Ring type ) Operating Current ( Crystal type ) Input Current of TG1−TG8 Pins Input Current of TEST Pin Input Current of -4.0 -5.0 VDD = 3V, Rl = 8 Ω 0.8 -0.8 100 mA mA mA VDD = 3V, VOUT = 0.4V VDD = 3V, VOUT = 2.7V -100 0.8 -0.8 mA mA mA AC Characteristics -9- Publication Release Date: March 1999 Revision A2 W58300 PARAMETER 1 Oscillation Frequency SYM. CONDITIONS MIN. TYP. MAX. UNIT Fosc Ring Oscillator, Rosc = 270 KΩ 2.7 3 3.3 MHz Ring Oscillator, Rosc = 560 KΩ 1.3 1.5 1.7 Oscillation Frequency Deviation by Voltage Drop ∆Fosc F(3V)−F(2.4V) Fosc F(3V) Instruction Cycle Time TINS Fosc = 3 MHz, SR = 6 KHz 1/3 mS POI Delay Time TPD Fosc = 3 MHz 160 mS Long Debounce Time TDEBL 2 Short Debounce Time 7.5 Fosc = 3 MHz, SR = 6 KHz TDEBS 50 mS 400 µS 1. This parameter is different from that of W583xxx. 2. For ring oscillator only. TYPICAL APPLICATION CIRCUIT VCC STPA/BUSY STPB LED2/STPC STPD STPE STPF STPG STPH VDD V DDE IROUT TG1 W58300 TG2 TG3/IRIN DISOTP TG4 LED1 TG5 TG6 TG7 AUD/SPK+ TG8 SPKOSC/X IN 20P 20P Crystal Serial Flash Memory (W55Fxx) WRP RDP DATA VCC 330 TEST OSCO/XOUT SEL Vss RESET (PWM type voice output) - 10 - % W58300 BONDING PAD DIAGRAM V DDE WRP DATA RDP DISOTP TEST RESET IROUT TG1 STPA/BUSY TG2 STPB LED2/STPC TG3/IRIN STPD TG4 (0, 0) TG5 STPE TG6 STPF TG7 STPG TG8 STPH OSC/X IN X OUT SEL VDD AUD/SPK+ SPK- Vss LED1 REVISION HISTORY Revision A1 to A2 1. FEATURE Change operating voltage range to 2.4-5.5 Volts 2. PIN DESCRIPTION Add description on TG3/IRIN 3. MODE0 Register Reserve bit MODE0.0 Revise definition of MODE0.4 Add description on bit MODE0.5 4. MODE1 Register Add description on bit MODE1.0 5. Instruction Set Add instruction cycle time 6. DC CHARACTERISTIC Revise Operating Voltage parameter - 11 - Publication Release Date: March 1999 Revision A2 W58300 Revise Output Current of SPK+, SPK- parameter 7. AC CHARACTERISTIC Revise Oscillation Frequency parameter Revise Oscillation Frequency Deviation by Voltage Drop parameter Revise Long Debounce Time parameter Revise Short Debounce Time parameter Headquarters Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5792697 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change without notice. - 12 - Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798