ETC W925E625

W925E/C625
8-bit CID Microcontroller
1
GENERAL DESCRIPTION...................................................................................................................... 3
2
FEATURES .................................................................................................................................................. 3
3
PIN CONFIGURATION............................................................................................................................ 5
4
PIN DESCRIPTION ................................................................................................................................... 6
5
BLOCK DIAGRAM ................................................................................................................................... 8
6
FUNCTIONAL DESCRIPTION .............................................................................................................. 9
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
7
MEMORY ORGANIZATION ................................................................................................................... 10
SPECIAL FUNCTION REGISTERS ........................................................................................................... 13
INITIAL STATE OF REGISTERS.............................................................................................................. 31
INSTRUCTION ....................................................................................................................................... 32
POWER MANAGEMENT ........................................................................................................................36
RESET ................................................................................................................................................... 37
INTERRUPT ........................................................................................................................................... 37
PROGRAMMABLE TIMERS/COUNTERS ................................................................................................ 39
SERIAL PORT 1 .....................................................................................................................................44
COMPARATOR ...................................................................................................................................... 45
DTMF GENERATOR............................................................................................................................. 45
FSK GENERATOR ................................................................................................................................ 46
I/O PORTS.............................................................................................................................................48
DIVIDER................................................................................................................................................48
LCD...................................................................................................................................................... 48
CALLING IDENTITY DELIVERY (CID) .................................................................................................52
ELECTRICAL CHARACTERISTICS .................................................................................................65
7.1
MAXIMUM RATINGS* .......................................................................................................................... 65
7.2
RECOMMENDED OPERATING CONDITIONS ......................................................................................... 65
7.3
DC ELECTRICAL CHARACTERISTICS .................................................................................................. 65
ELECTRICAL CHARACTERISTICS - GAIN CONTROL OP-AMPLIFIER ...............................................................67
7.4
AC ELECTRICAL CHARACTERISTICS .................................................................................................. 67
8
PACKAGE.................................................................................................................................................. 70
9
VERSION STATEMENT ........................................................................................................................71
-1-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
FIGURE 3-1 W925E/C625 PIN CONFIGURATION .................................................................................................. 5
FIGURE 6-1 PROGRAM MEMORY MAP ................................................................................................................10
FIGURE 6-2 MEMORY MAP .................................................................................................................................. 11
FIGURE 6-3 SCRATCHPAD RAM/REGISTER ADDRESSING .................................................................................. 12
FIGURE 6-4 THE STRUCTURE OF CID FLAGS ...................................................................................................... 38
FIGURE 6-5 MODE 0 & MODE 1 OF TIMER/COUNTER 0 & 1.............................................................................. 40
FIGURE 6-6 MODE 2 OF TIMER/COUNTER 0 & 1 ................................................................................................ 41
FIGURE 6-7 WATCHDOG TIMER ...........................................................................................................................42
FIGURE 6-8 TIMING OF THE SERIAL PORT 1 INPUT FUNCTION ........................................................................... 44
FIGURE 6-9 TIMING OF THE SERIAL PORT 1 OUTPUT FUNCTION ....................................................................... 45
FIGURE 6-10 THE CONFIGURATION OF COMPARATOR ....................................................................................... 45
FIGURE 6-11 THE RELATION BETWEEN DTMF AND KEYPAD ........................................................................... 46
FIGURE 6-12 FSK MODULATOR .......................................................................................................................... 47
FIGURE 6-13 13/14-BIT DIVIDER ......................................................................................................................... 48
FIGURE 6-14 LCD ALTERNATING FREQUENCY (FLCD) CIRCUIT DIAGRAM...................................................... 49
FIGURE 6-15 1/5 BIAS LCD POWER CONNECTION ............................................................................................. 51
FIGURE 6-16 LCD WAVEFORM FOR 1/5 BIAS ...................................................................................................... 51
FIGURE 6-17 THE CID BLOCK DIAGRAM ........................................................................................................... 52
FIGURE 6-18 APPLICATION CIRCUIT OF THE RING DETECTOR ........................................................................... 53
FIGURE 6-19 DIFFERENTIAL INPUT GAIN CONTROL CIRCUIT ............................................................................54
FIGURE 6-20 SINGLE-ENDED INPUT GAIN CONTROL CIRCUIT........................................................................... 54
FIGURE 6-21 GUARD TIME WAVEFORM OF ALERT TONE SIGNAL DETECTION ................................................55
FIGURE 6-22 THE WAVEFORM OF DTMF DETECTION ....................................................................................... 56
FIGURE 6-23 FSK DETECTION ENABLE AND FSK CARRIER PRESENT AND ABSENT TIMING .......................... 56
FIGURE 6-24 SERIAL DATA INTERFACE TIMING OF FSK DEMODULATION ....................................................... 57
FIGURE 6-25 INTERNAL CID GAIN CONTROL REGISTER SETTING WAVEFORM ............................................... 58
FIGURE 6-26 APPLICATION CIRCUIT OF CID ...................................................................................................... 59
FIGURE 6-27 INPUT AND OUTPUT TIMING OF BELLCORE O N-HOOK DATA TRANSMISSION ............................. 60
FIGURE 6-28 INPUT AND OUTPUT TIMING OF BELLCORE O FF-HOOK D ATA TRANSMISSION ............................61
FIGURE 6-29 INPUT AND OUTPUT TIMING OF BT IDLE STATE (ON-HOOK) DATA TRANSMISSION .................. 62
FIGURE 6-30 INPUT AND OUTPUT TIMING OF BT LOOP STATE (OFF-HOOK) DATA TRANSMISSION ............... 63
FIGURE 6-31 INPUT AND OUTPUT TIMING OF CCA CALLER DISPLAY SERVICE DATA TRANSMISSION .......... 64
-2-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
1
GENERAL DESCRIPTION
The W925E/C625 is an all-in-1 single 8-bit micro-controller with widely used Calling Identity
Delivery (CID) function. The 8-bit CPU core is based on the 8051 family; therefore, all the
instructions are compatible to the Turbo 8051 series. The CID part consists FSK decoder, DTMF
receiver, CPE* Alert Signal (CAS) detector and Ring detector. Also built-in DTMF generator and
FSK generator with baud rate 1200 bps (bits/sec). Using W925E/C625 can easily implement the
CID adjunct box and the feature phone or Short Message Service (SMS) phone with CID
function. The main features are listed in the next section.
2
FEATURES
• APPLICATION: The SMS phone with CID function and CID adjunct box.
• CPU: 8-bit micro-controller is similar to the 8051 family.
- Operating voltage:
µC: 2.2 to 5.5 volt.
CID: 3.0 to 5.5 volt.
• Dual-clock operation:
- Main oscillator: 3.58MHz crystal for CID and DTMF function. And built-in RC oscillator.
- Sub oscillator: 32768Hz crystal.
- Main and sub oscillators are enable/disable by bit control individually.
• ROM: 64K bytes internal flash EEPROM/MASK ROM type.
- up 64K bytes for program ROM.
- total 64K bytes for look-up table ROM.
• RAM:
- 256 bytes on chip scratch-pad RAM.
- 4K bytes on chip RAM for MOVX instruction.
- 224 bytes on chip LCD RAM.
• LCD: dot matrix control method.
- 1792 dots: 56 Segments x 32 Common, 1/5 bias.
• CID:
- Compatible with Bellcore TR-NWT-000030 & SR-TSV-002476, British Telecom(BT)
SIN227, U.K. Cable Communication Association(CCA) specification.
- FSK modulator/demodulator: for Bell 202 and ITU-T V.23 FSK with 1200 baud rate.
- CAS detector: for dual tones of Bellcore CAS and BT Idle State and Loop State Dual
Tone Alert Signal (DTAS).
- DTMF generator/receiver; DTMF receiver can be programmed as a tone detector.
- Ring detector: for line reversal for BT, ring burst for CCA or ring signal for Bellcore.
- Two independent OP amps with adjustable gain for Tip/Ring and Telephone Hybrid
connections.
• I/O: 40 I/O pins.
- P0: Bit and byte addressable. I/O mode can be bit controlled. Open drain type.
- P1~P3: Bit and byte addressable. Pull high and I/O mode can be bit controlled.
- P4 : Byte addressable . Pull high and I/O mode can be bit controlled.
note: ”CPE*” Customer Premises Equipment
-3-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
• Power mode:
- Normal mode: Normal operation
- Dual-clock slow operation mode: System is operated by the sub-oscillator (Fosc=Fs
and Fm is stopped)
- Idle mode: CPU hold. The clock to the CPU is halted, but the interrupt, timer and
watchdog timer block work normally but CID function is disabled.
- Power down mode: All activity is completely stopped and power consumption is less
than 1 µA.
• Timer: 2 13/16-bit timers, or 8-bit auto-reload timers, that are Timer0 and Timer1.
• Watchdog timer: WDT can be programmed by the user to serve as a system monitor.
• Interrupt: 11 interrupt sources with two levels of priority.
- 4 interrupts from INT0, INT1, INT2 and INT3.
- 2 interrupts from Timer0, Timer1.
- 1 interrupt from Serial port.
- 1 interrupt from CID.
- 1 interrupt from 13/14-bit Divider.
- 1 interrupt from Comparator.
- 1 interrupt from Watch Dog Timer.
• Divider: 13/14 bit divider, clock source from sub-oscillator, therefore, DIVF set every 0.25/0.5
Sec.
• Comparator:
- Comparator: 1 analog inputs from VNEG pin, 2 reference input pins, one is from VPOS
pin and another is from internal 1.0v regulator output.
• Serial port:
- An 8-bit serial transceiver with SCLK and SDATA.
.• Package:
- 160pin QFP
-4-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
3
PIN CONFIGURATION
P40
P37
P36
P35
P34
P33
P32
P31
P30
BUZ
VDD
VSS
P27
P26
P25
P24
P23
P22
P21
P20
P17
P16
P15
P14
P13
P12
P11
P10
DTMF/FSK
EA/DATA
XOUT2
XIN2
VDD
XIN1
XOUT1
P07
P06
P05
P04
P03
W925E/C625
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
VAD
INP2
INN2
GCFB2
VAS
GCFB1
INN1
INP1
VREF
CAP
RNGDI
RNGRC
VSS
P00
P01
P02
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
U?
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
VLCD5
VLCD4
VLCD3
VLCD2
VLCD1
DH1
DH2
RESET/VPP
TEST/MODE
P47
P46
P45
P44/VPOS
P43
P42/VNEG
P41
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
Figure 3-1 shows the pin assignment. The package type is 160pin QFP.
Figure 3-1 W925E/C625 Pin Configuration
-5-
Release Date : 2002/7/2
Revision : A6
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
W925E/C625
8-bit CID Microcontroller
4
PIN DESCRIPTION
TEST/MODE
I/O
EA /DATA
I,I/O
RESET /VPP
I
RNGDI
I
RNGRC
O
CAP
VREF
O
O
GCFB1
O
INN1
INP1
GCFB2
I
I
O
INN2
INP2
VAD
VAS
VDD
VSS
XOUT1
I
I
I
I
I
I
O
XIN1
I
XOUT2
O
XIN2
I
DTMF/FSK
O
TEST pin. In E version, it works as Mode pin to select programming
mode. In C version(Mask type), this pin with internal pull-low resistor for
test mode.
Set high for normal function. In E version, it works as Data pin. In C
version, this pin with internal pull-high resistor.
RESET pin. A low pulse causes the whole chip reset. In E version, this
pin work as Vpp pin which is a supply programming voltage. In C version,
this pin with internal pull-high resistor.
Ring Detect Input (Schmitt trigger input). Used for ring detection and line
reversal detection. Must maintain a voltage between VAD and VAS.
Ring RC (Open drain output and Schmitt trigger input). Used to set the
time interval from the end of RNGDI pin to the inactive condition of the
RNGON pin. An external resistor must connected to VAD and a capacitor
connected to VSS, the time interval is the RC time constant.
Must be connected 0.1µF capacitor to VSS.
Reference Voltage. Nominally, VDD/2 is used to bias the input of the gain
control op-amp.
Op-amp1 Feed-back Gain Control signal. Select the input gain by
connecting this pin and the INN1 pin with feed-back resistor. It is
recommended that the op-amp1 be set to unity gain.
Inverting Input of the gain control op-amp1.
Non-inverting Input of the gain control op-amp1.
Op-amp2 Feed-back Gain Control signal. Select the input gain by
connecting this pin and the INN2 pin with feed-back resistor. It is
recommended that the op-amp2 be set to unity gain.
Inverting Input of the gain control op-amp2.
Non-inverting Input of the gain control op-amp2.
Analog voltage supply.
Analog ground.
Digital voltage supply.
Digital ground.
Output pin for main-oscillator. Connected to 3.58MHz crystal for CID
function.
Input pin for main-oscillator. Connected to 3.58MHz crystal for CID
function.
Output pin for sub-oscillator. Connected to 32.768KHz crystal only.
Suggest to add an external capacitor about 10~30pF to ground(VSS) for
the accuracy of the oscillator.
Input pin for sub-oscillator. Connected to 32.768KHz crystal only. Suggest
to add an external capacitor about 10~30pF to ground(VSS) for the
accuracy of the oscillator.
FTE=0, Dual-Tone Multi-Frequency(DTMF) signal output
FTE=1, FSK signal output
-6-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
BUZ
P00-P07
O
I/O
P10-P17
I/O
P20-P27
I/O
P30-P37
I/O
P40-P47
I/O
VPOS,
VNEG
DH1,DH2
VLCD1-5
SEG0SEG55
COM0COM31
I
Buzzer output pin. If buzzer function is disabled, BUZ pin is in floating state.
Input/Output port0. Port0 data can be bit controlled. The I/O mode is
controlled by P0IO register. Port0 is open drain type when it is configured
as output mode.
Input/Output port1 with pull high resistors. Port1 data can be bit controlled.
The I/O mode is controlled by P1IO register. The P10-P13 and P14-P17
indicates the external interrupt pins(INT2 and INT3)
Input/Output port2 with pull high resistors. Port2 data can be bit controlled.
The I/O mode is controlled by P2IO register.
Input/Output port3 with pull high resistors. Port3 data can be bit controlled.
The I/O mode is controlled by P3IO register. The special function of port3 is
referred to the description of P3 register.
Contents are byte controlled. Pull high and I/O mode can be bit controlled.
The special function of P4 is referred to the description of P4 register.
The comparator V+, V- analog input pins. Share pin with P4.2 and P4.4
I
I
O
Connection terminals for LCD voltage doublers capacitor.
Positive LCD voltage supply terminals.
LCD segment output pins.
O
LCD common output pins.
-7-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
5
BLOCK DIAGRAM
Internal CID and uC interface
RNGDI
RNGRC
INP1
INN1
GCFB1
INP2
INN2
GCFB2
VREF
CAP
FSK,CAS
(W91030)
P4
DTMFD
DTMFPT
DTMFAT
8
DCLK
DATA
DTMFH
DTMFL
RST
S/P
DTMF
RECEIVER
DTMFE
CASPT
CASAT
CIDE
FSKE
CASE
P0
P1
P2
P3
RNG
ALGO
FDR
FCD
CASH,CASL
DD3~DD0
FM
DCLK
FDATA
FD7~FD0
8
RNGF
ALGOF
FDRF
DTMFDF
FSF
D-latch
8
Fosc
ck
8
8
8-bit µC
FSK
modulator
5
TEST/MODE
X
I
N
1
X
O
U
T
1
X
I
N
2
X V V V V
O D s A A
U D S D S
T
2
SEG00
~
SEG55
COM00
~
COM31
-8-
D D
H H
1 2
VLCD1
~
VLCD5
B
U
Z
D
T
M
F
/
F
S
K
R
E
S
E
T
/
V
P
P
E
A
/
D
A
T
A
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
6
FUNCTIONAL DESCRIPTION
The W925E/C625 is an 8-bit micro-controller with CID function. The 8-bit micro-control has the
same instruction set as the 8051 family, with one addition: DEC DPTR (op-code A5H, the DPTR
is decreased by 1). In addition, the W925E/C625 contains on-chip 4K + 224 bytes MOVX RAM.
ROM:
There are 64K bytes EEPROM/MASK ROM. The total 64K bytes EEPROM/MASK ROM is used
for program code. The completely 64K bytes EEPROM/MASK ROM can be used for the look-up
table memory.
On-chip Data RAM:
The W925E/C625 has 4K normal RAM + 224 Bytes of discontinuity LCD RAM which address is
from 0000H to 0FFFH + 2000H to 20FEH. It only can be accessed by MOVX instruction; this onchip RAM is optional under software control. The 224 bytes of RAM, which no appends to the 4K
bytes RAM, are used for LCD RAM. The on-chip data RAM is not used for executable program
memory. There is no conflict or overlap among the 256 bytes scratchpad RAM and the 4K Bytes
MOVX RAM as they use different addressing modes and separate instructions.
CID:
The CID functions include the FSK decoder, tone alert signal detector, DTMF decoder and ring
detector.
FSK modulator:
Support ITU-T V.23 and Bellcore 202 FSK transmit modulate signal
DTMF modulator:
The W925E/C625 built-in Dual tone multi-frequency generator.
I/O Ports:
The W925E/C625 has five 8-bit I/O ports giving a total of 37 lines. Port0 to Port3 can be used as
an 8-bit general I/O port with bit-addressable. The I/O mode of each port are controlled by PxIO
registers. Port 1 to Port 4 have internal pull high resistors enabled/disabled by PxH registers.
Port0 is open-drain type in output mode.
Serial I/O port:
The serial port, through P4.0 (SCLK) and P4.1 (SDATA), is an 8-bit synchronous serial I/O
interface.
Timers:
The W925E/C625 has two 13/16-bit timers or 8 bits auto-reload timers. An independent watchdog
timer is used as a System Monitor or as a very long time period timer. A divider can produce the
divider interrupt in every period of 0.5S or 0.25S.
Comparator:
The W925E/C625 has an internal comparator with one external analog signal input path VNEG
and an external path VPOS or a regulator voltage for the reference input REF1.
LCD:
The LCD display of 1792 dots is 1/5 bias with 56 segments and 32 commons. The LCD display of
The LCD voltage is from internal regulator or external voltage source.
Interrupts:
The W925E/C625 provides 11 interrupt resources with two priority level, including 4 external
interrupt sources, 2 timer interrupts, 1 CID interrupt, 1 divider interrupt, 1 serial port interrupt, 1
comparator interrupt and 1 watchdog timer interrupt.
Power Management:
-9-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
The W925E/C625 has IDLE and POWER DOWN modes of operation. In the IDLE mode, the
clock to the CPU core is stopped however the functions of the timers, divider, CID and interrupts
are active continuously. In the POWER DOWN mode, both of the system clock stop oscillating
and the chip operation is completely stopped. POWER DOWN mode is the state of the lowest
power consumption.
6.1
Memory Organization
The W925E/C625 separates the memory into two separate sections, the Program Memory and
the Data Memory. The Program Memory is used to store the instruction op-codes and look-up
table data, while the Data Memory is used to store data or for memory mapped devices.
Program Memory:
The Program Memory on the W925E/C625 can be up to 64K bytes. The total 64K bytes
EEPROM/MASK ROM are used to store the op-codes and the whole 64K can be used to store
look-up table data.
00000
64K bytes
EEPROM /
MASK ROM
0FFFF
Figure 6-1 Program Memory Map
Data Memory:
The W925E/C625 contains on-chip 4K + 224 bytes MOVX RAM of Data Memory, which can only
be accessed by MOVX instructions from the address 0000H to 0FFFH and from 2000H to 20FEH.
In addition, the W925E/C625 has 256 bytes of on-chip scratchpad RAM. This can be accessed
either by direct addressing or by indirect addressing. There are also Special Function Registers
(SFRs), which can only be accessed by direct addressing. Since the scratchpad RAM is only 256
bytes, it can be used only when data contents are small. In the event that larger data contents are
present, the only one selection is on-chip MOVX RAM. The on-chip MOVX RAM can only be
accessed by a MOVX instruction. However, the on-chip RAM has the fastest access times. The
memory map is shown Figure 6-2 and Figure 6-3 shows the scratchpad RAM/Register
addressing.
-10-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
FFH
80H
7FH
00H
20FEH
2000H
Indirect
Addressing
RAM
SFRs Direct
Addressing
only
Direct &
Indirect
Addressing
RAM
LCDRAM0FE
|
|
LCDRAM000
0FFFH
4K byte SRAM On chip
0000H
Figure 6-2 Memory Map
-11-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
FFh
Indirect RAM
80h
7Fh
30h
2Fh
2Eh
2Dh
2Ch
2Bh
2Ah
29h
28h
27h
26h
25h
24h
23h
22h
21h
20h
1Fh
18h
17h
10h
0Fh
08h
07h
00h
Direct RAM
7F
77
6F
67
5F
57
4F
47
3F
37
2F
27
1F
17
0F
07
7E
76
6E
66
5E
56
4E
46
3E
36
2E
26
1E
16
0E
06
7D
75
6D
65
5D
55
4D
45
3D
35
2D
25
1D
15
0D
05
7C
74
6C
64
5C
54
4C
44
3C
34
2C
24
1C
14
0C
04
7B
73
6B
63
5B
53
4B
43
3B
33
2B
23
1B
13
0B
03
7A
72
6A
62
5A
52
4A
42
3A
32
2A
22
1A
12
0A
02
79
71
69
61
59
51
49
41
39
31
29
21
19
11
09
01
78
70
68
60
58
50
48
40
38
30
28
20
18
10
08
00
Bit Addressable
20H- 2FH
Bank 3
Bank 2
Bank 1
Bank 0
Figure 6-3 Scratchpad RAM/Register Addressing
-12-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
6.2
Special Function Registers
The W925E/C625 uses Special Function Registers (SFRs) to control and monitor peripherals and
their Modes.
The SFRs reside in the register locations 80-FFh and are accessed by direct addressing only.
Some of the SFRs are bit addressable. This is very useful in cases where one wishes to modify a
particular bit without changing the others. The SFRs that are bit addressable are those whose
addresses end in 0 or 8. The list of SFRs is as follows. The table is condensed with eight
locations per row. Empty locations indicate that there are no registers at these addresses. The
content of reserved bits or registers is not guaranteed.
Table 1 Special Function Register Location Table
F8 EIP
CIDGD
CIDGA
F0 B
E8 EIE
E0 ACC
D8 WDCON
D0 PSW
C8 DIVC
C0 SCON1
SBUF1
REGVC
PMR
STATUS FSKTC
FSKTB
B8 IP
DTMFG
COMPR
IRC1
IRC2
CASPT
CASAT
B0 P3
CIDR
CIDFG
CIDPCR FSKDR
DTMFDR DTMFPT DTMFAT
A8 IE
P4IO
A0 P2
HB
P4H
P4
98
P1EF
P1H
P2H
P3H
90 P1
EXIF
P1SR
P0IO
P1IO
P2IO
P3IO
88 TCON
TMOD
TL0
TL1
TH0
TH1
CKCON1 CKCON2
80 P0
SP
DPL
DPH
DPL1
DPH1
DPS
PCON
Note: The SFRs in the column with dark borders are bit-addressable.
A brief description of the SFRs now follows.
PORT 0
(initial=FFh, input mode)
Bit:
7
P0.7
6
P0.6
5
P0.5
4
P0.4
3
P0.3
Mnemonic: P0
2
P0.2
1
P0.1
0
P0.0
Address: 80h
P0: P0 can be selected as input or output mode by the P0IO register, At initial reset, P0IO is
set to FFH, P0 is used as input mode. When P0IO is set to 0, the P0 is used as CMOS
open drain mode.
STACK POINTER
Bit:
(initial=07H)
7
SP.7
6
SP.6
5
SP.5
4
SP.4
Mnemonic: SP
3
SP.3
2
SP.2
1
SP.1
0
SP.0
Address: 81h
-13-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
SP:
The Stack Pointer stores the scratchpad RAM address where the stack begins. In other
words, it always points to the top of the stack.
DATA POINTER LOW
Bit:
(initial=00H)
7
DPL.7
6
DPL.6
5
DPL.5
4
DPL.4
3
DPL.3
Mnemonic: DPL
2
DPL.2
1
DPL.1
0
DPL.0
Address: 82h
DPL: This is the low byte of the standard 8052 16-bit data pointer.
DATA POINTER HIGH
Bit:
(initial=00H)
7
DPH.7
6
DPH.6
5
DPH.5
4
DPH.4
3
DPH.3
Mnemonic: DPH
2
DPH.2
1
DPH.1
0
DPH.0
Address: 83h
DPH: This is the high byte of the standard 8052 16-bit data pointer.
DATA POINTER LOW1
Bit:
DPL1:
(initial=00H)
7
6
5
4
3
2
1
0
DPL1.7 DPL1.6 DPL1.5 DPL1.4 DPL1.3 DPL1.2 DPL1.1 DPL1.0
Mnemonic: DPL1
Address: 84h
This is the low byte of the new additional 16-bit data pointer that has been added to the
W925E/C625. The user can switch between DPL, DPH and DPL1, DPH1 simply by
setting register DPS.0 = 1. The instructions that use DPTR will now access DPL1 and
DPH1 in place of DPL and DPH. If they are not required they can be used as
conventional register locations by the user.
DATA POINTER HIGH1
Bit:
(initial=00H)
7
6
5
4
3
2
1
0
DPH1.7 DPH1.6 DPH1.5 DPH1.4 DPH1.3 DPH1.2 DPH1.1 DPH1.0
Mnemonic: DPH1
DPH1:
Address: 85h
This is the high byte of the new additional 16-bit data pointer that has been added to the
W925E/C625. The user can switch between DPL, DPH and DPL1, DPH1 simply by
setting register DPS = 1. The instructions that use DPTR will now access DPL1 and
DPH1 in place of DPL and DPH. If they are not required they can be used as
conventional register locations by the user.
DATA POINTER SELECT
Bit:
7
-
(initial=00H)
6
-
5
-
4
-
3
-
2
-
1
-
0
DPS.0
Mnemonic: DPS
Address: 86h
This bit is used to select either the DPL,DPH pair or the DPL1,DPH1 pair as the active
Data Pointer. When set to 1, DPL1,DPH1 will be selected, otherwise DPL,DPH will be
selected.
DPS.1-7:These bits are reserved, but will read 0.
DPS.0:
POWER CONTROL
-14-
(initial=00H)
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
Bit:
IDLT:
GF1-0:
PD:
IDL:
7
-
6
-
5
-
4
IDLT
3
GF1
2
GF0
1
PD
0
IDL
Mnemonic: PCON
Address: 87h
This bit controls the idle mode type. In idle mode when idle mode is released by any
interrupt, if IDLT=1 it will not jump to the corresponding interrupt; if IDLT=0 it will jump to
the corresponding interrupt.
These two bits are general purpose user flags.
Setting this bit causes the W925E/C625 to go into the POWER DOWN mode. In this
mode all the clocks are stopped and program execution is frozen. Power down mode
can be released by INT0~INT3 and ring detection of CID interrupt.
Setting this bit causes the W925E/C625 to go into the IDLE mode. The type of idle
mode is selected by IDLT. In this mode the clocks to the CPU are stopped, so program
execution is frozen. But the clock path to the timers blocks and interrupt blocks is not
stopped, and these blocks continue operating.
TIMER CONTROL
Bit:
(initial=00H)
7
TF1
6
TR1
5
TF0
4
TR0
3
IE1
2
IT1
1
IE0
0
IT0
Mnemonic: TCON
Address: 88h
TF1: Timer 1 overflow flag. This bit is set when Timer 1 overflows. It is cleared automatically
when the program does a timer 1 interrupt service routine. Software can also set or clear
this bit.
TR1: Timer 1 run control. This bit is set or cleared by software to turn timer on or off.
TF0: Timer 0 overflow flag. This bit is set when Timer 0 overflows. It is cleared automatically
when the program does a timer 0 interrupt service routine. Software can also set or clear
this bit.
TR0: Timer 0 run control. This bit is set or cleared by software to turn timer on or off.
IE1:
IT1:
IE0:
IT0:
Interrupt 1 edge detect: Set by hardware when an edge/level is detected on INT1. This bit
is cleared by hardware when the service routine is vectored to only if the interrupt was
edge triggered. Otherwise it follows the pin.
Interrupt 1 type control: Set/cleared by software to specify falling edge/ low level triggered
external inputs.
Interrupt 0 edge detect: Set by hardware when an edge/level is detected on INT0 . This bit
is cleared by hardware when the service routine is vectored to only if the interrupt was
edge triggered. Otherwise it follows the pin.
Interrupt 0 type control. Set/cleared by software to specify falling edge/ low level triggered
external inputs.
TIMER MODE CONTROL
Bit:
7
GATE
(initial=00H)
6
C/ T
5
M1
4
M0
3
GATE
2
1
M1
C/ T
Address: 89h
0
M0
Mnemonic: TMOD
Bit7~4 control timer 1, bit3~0 control timer0
GATE: Gating control. When this bit is set, Timer x is enabled only while INTx pin is high and
TRx control bit is set. When cleared, Timer x is enabled whenever TRx control bit is set.
-15Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
C/ T :
Timer or Counter Select. When cleared, the timer is incremented by internal clocks. When
set, the timer counts high-to-low edges of the Tx pin.
Note: X is either 0 or 1.
M1, M0: Mode Select bits:
M1
0
0
1
1
M0
0
1
0
1
Mode
Mode 0: 13-bits timer
Mode 1: 16-bits timer
Mode 2: 8-bits with auto-reload from Thx
Reserved
TIMER 0 LOW BYTE
Bit:
(initial=00H)
7
TL0.7
6
TL0.6
5
TL0.5
4
TL0.4
3
TL0.3
Mnemonic: TL0
2
TL0.2
1
TL0.1
0
TL0.0
Address: 8Ah
TL0.7-0: Timer 0 low byte register.
TIMER 1 LOW BYTE
Bit:
7
TL1.7
6
TL1.6
5
TL1.5
4
TL1.4
3
TL1.3
Mnemonic: TL1
(initial=00H)
2
1
TL1.2
TL1.1
0
TL1.0
Address: 8Bh
TL1.7-0: Timer 1 low byte register.
TIMER 0 HIGH BYTE
Bit:
(initial=00H)
7
TH0.7
6
TH0.6
5
TH0.5
4
TH0.4
3
TH0.3
Mnemonic: TH0
TH0.7-0: Timer 0 high byte register.
1
TH0.1
0
TH0.0
Address: 8Ch
TIMER 1 HIGH BYTE
Bit:
2
TH0.2
(initial=00H)
7
TH1.7
6
TH1.6
5
TH1.5
4
TH1.4
Mnemonic: TH1
3
TH1.3
2
TH1.2
1
TH1.1
0
TH1.0
Address: 8Dh
TH1.7-0: Timer 1 high byte register.
-16-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
CLOCK CONTROL1
Bit:
7
WD1
6
WD0
5
T1S1
4
T1S0
3
T0S1
Mnemonic: CKCON1
(initial=00H)
2
1
T0S0
DIVS
0
M /S
Address: 8Eh
WD1-0: Watchdog timer mode select bits: These bits determine the time-out period for the
watchdog timer. In all four time-out options the reset time-out is 512 clocks more than the
interrupt time-out period.
WD1
WD0
Interrupt time-out
Reset time-out
0
0
Fosc/212
Fosc/212 + 512
15
15
0
1
Fosc/2
Fosc/2 + 512
18
18
1
0
Fosc/2
Fosc/2 + 512
21
21
1
1
Fosc/2
Fosc/2 + 512
T0S0-1&T1S0-1: Timer0 & Timer1 clock source mode select bits. These bits determine the timer0
& timer1 clock source.
T0S1
T0S0
Prescale clock
(T1S1) (T1S0)
source
2
0
0
Fosc/2
6
0
1
Fosc/2
10
1
0
Fosc/2
1
1
Fs
DIVS: Divider clock source control bit 1:
13
DIVS = 0 : Fs/2
14
DIVS= 1 : Fs/2
M /S: System clock source control bit :
M /S = 0 : Fosc = XIN1 ( FM)
M /S = 1 : Fosc = XIN2 ( Fs)
CLOCK CONTROL2
Bit:
(initial=00H)
7
6
ENBUZ BUZSL
5
KT1
4
KT0
3
-
2
-
1
-
0
-
Mnemonic: CKCON2
Address: 8Fh
ENBUZ: When ENBUZ=1 the BUZ pin works as buzzer output, otherwise BUZ pin is in floating
state.
BUZSL: Buzzer output selection. When BUZSL=0 BUZ is the output of octave tone. When
BUZZL=1, BUZ is the output of key tone.
KT1-0: Key tone frequency sources from divider. When divider is enable, KT1 and KT0
determines the key tone frequency.
key tone
KT1
KT0
frequency
0
0
Low
0
1
512Hz
1
0
1024Hz
1
1
2048Hz
-17-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
PORT 1
Bit:
7
P1.7
6
P1.6
5
P1.5
4
P1.4
3
P1.3
Mnemonic: P1
(initial=FFh, input mode)
2
1
0
P1.2
P1.1
P1.0
Address: 90h
P1.7-0: P1 can be selected as input or output mode by the P1IO register , At initial reset , P1IO is
set to 1, so P1 is used as input mode . When P1IO is set to 0 , the P1 is used as
CMOS output mode . When P1EF are set and P1IO are set as input mode , P1 can be
used as external interrupt source. The functions are listed below .
P1.0 : INT2.0
P1.1 : INT2.1
P1.2 : INT2.2
P1.3 : INT2.3
P1.4 : INT3.0
P1.5 : INT3.1
P1.6 : INT3.2
P1.7 : INT3.3
External Interrupt 2
External Interrupt 2
External Interrupt 2
External Interrupt 2
External Interrupt 3
External Interrupt 3
External Interrupt 3
External Interrupt 3
EXTERNAL INTERRUPT FLAG
Bit:
7
-
(initial=00H)
6
-
5
-
4
COMPF
3
DIVF
2
CIDF
1
IE3
0
IE2
Mnemonic: EXIF
Address: 91h
COMPF: Comparator flag. Set by hardware when RESC bit is from low to high.
DIVF: Divider overflow flag.
CIDF: CID interrupt flag. Set by hardware when at least one of CID flags is set.
IE3:
External Interrupt 3 flag. Set by hardware when a falling edge is detected on INT3.
IE2:
External Interrupt 2 flag. Set by hardware when a falling edge is detected on INT2.
P1 PINS STATUS
Bit:
(initial=00H)
7
6
5
4
3
2
1
0
P1.7SR P1.6SR P1.5SR P1.4SR P1.3SR P1.2SR P1.1SR P1.0SR
Mnemonic: P1SR
Address: 93h
P1SR: Set when a falling edge is detected on the corresponding P1 pin, clear by software.
P0 I/O PORT CONTROL
Bit:
7
P0.7IO
(initial=FFH)
6
P0.6IO
5
P0.5IO
4
P0.4IO
Mnemonic: P0IO
P0IO: P0 pins I/O control.
1: input mode
0: output mode
3
P0.3IO
2
P0.2IO
1
P0.1IO
0
P0.0IO
Address: 94h
-18-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
P1 I/O PORT CONTROL
Bit:
7
P1.7IO
(initial=FFH)
6
P1.6IO
5
P1.5IO
4
P1.4IO
3
P1.3IO
Mnemonic: P1IO
P1IO: P1 pins I/O control.
1: input mode
0: output mode
7
P2.7IO
6
P2.6IO
5
P2.5IO
4
P2.4IO
3
P2.3IO
1
P2.1IO
0
P2.0IO
(initial=FFH)
6
P3.6IO
5
P3.5IO
4
P3.4IO
3
P3.3IO
Mnemonic: P3IO
P3IO: P3 pins I/O control.
1: input mode
0: output mode
2
P3.2IO
1
P3.1IO
0
P3.0IO
Address: 97h
P1 PINS INTERRUPT EABLE
Bit:
2
P2.2IO
Address: 96h
P3 I/O PORT CONTROL
7
P3.7IO
0
P1.0IO
(initial=FFH)
Mnemonic: P2IO
P2IO: P2 pins I/O control.
1: input mode
0: output mode
Bit:
1
P1.1IO
Address: 95h
P2 I/O PORT CONTROL
Bit:
2
P1.2IO
(initial=00H)
7
6
5
4
3
2
1
0
P1.7EF P1.6EF P1.5EF P1.4EF P1.3EF P1.2EF P1.1EF P1.0EF
Mnemonic: P1EF
P1EF: P1 pins interrupt function enabled/disabled register
Address: 9Bh
0: disable
1: enable
P1 PULL-HIGH CONTROL
Bit:
P1H:
7
P1.7H
(initial=00H)
6
P1.6H
5
P1.5H
4
P1.4H
Mnemonic: P1H
Port1 pins pull-high resistor enable/disable
1: enable
0: disable
P2 PULL-HIGH CONTROL
3
P1.3H
2
P1.2H
1
P1.1H
0
P1.0H
Address: 9Dh
(initial=00H)
-19-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
Bit:
P2H:
7
P2.7H
6
P2.6H
5
P2.5H
4
P2.4H
3
P2.3H
Mnemonic: P2H
Port1 pins pull-high resistor enable/disable
1: enable
0: disable
P3H:
7
P3.7H
1
P2.1H
0
P2.0H
Address: 9Eh
P3 PULL-HIGH CONTROL
Bit:
2
P2.2H
(initial=00H)
6
P3.6H
5
P3.5H
4
P3.4H
3
P3.3H
Mnemonic: P3H
Port1 pins pull-high resistor enable/disable
1: enable
0: disable
2
P3.2H
1
P3.1H
0
P3.0H
Address: 9Fh
PORT 2
(initial=FFh, input mode)
Bit:
7
P2.7
6
P2.6
5
P2.5
4
P2.4
3
P2.3
Mnemonic: P2
2
P2.2
1
P2.1
0
P2.0
Address: A0h
P2.7-0: Port 2 is a I/O port with internal pull-high resistor. P2 can be selected as input or output
mode by the P2IO register. At initial reset, P2 is used as input mode. When P2IO is set to
0, P2 is used as CMOS output mode.
HIGH BYTE REGISTER
Bit:
7
HB.7
(initial=00H)
6
HB.6
5
HB.5
4
HB.4
3
HB.3
Mnemonic: HB
2
HB.2
1
HB.1
0
HB.0
Address: A1h
This register contains the high byte address during execution of " MOVX @Ri, " instructions.
P4 PULL-HIGH CONTROL
Bit:
P4H:
7
P4.7H
(initial=00H)
6
P4.6H
5
P4.5H
4
P4.4H
Mnemonic: P4H
Port4 pins pull-high resistor enable/disable
1: enable
0: disable
-20-
3
P4.3H
2
P4.2H
1
P4.1H
0
P4.0H
Address: A2h
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
PORT 4
(initial=FFh, input mode)
Bit:
7
P4.7
Mnemonic: P4
6
P4.6
5
P4.5
4
P4.4
3
P4.3
2
1
P4.2
P4.1
Address: A6h
0
P4.0
P4.7-0: Port 4 is a I/O port with internal pull-high resistor. P4 can be selected as input or output
mode by the P4IO register, At initial reset, P4IO is set to 0FFh, P4 is used as input
mode. When P4IO is set to 00h, P4 is used as CMOS output mode. Special function of
P4 is described below.
P4.4
VPOS
Positive input of the comparator
P4.2
VNEG
Negative input of the comparator
P4.1
SDATA
Serial port data I/O
P4.0
SCLK
Serial port clock I/O
INTERRUPT ENABLE
Bit:
EA:
ES1:
ET1:
EX1:
ET0:
EX0:
(initial=00H)
7
EA
6
ES1
5
-
4
-
3
ET1
Mnemonic: IE
Global enable. Enable/disable all interrupts.
Enable Serial port interrupt
Enable Timer 1 interrupt
Enable external interrupt 1
Enable Timer 0 interrupt
Enable external interrupt 0
7
P4.7IO
1
ET0
0
EX0
Address: A8h
P4 I/O PORT CONTROL
Bit:
2
EX1
(initial=FFH)
6
P4.6IO
5
P4.5IO
4
P4.4IO
Mnemonic: P4IO
P4IO: P4 pins I/O control.
1: input mode
0: output mode
3
P4.3IO
2
P4.2IO
1
P4.1IO
0
P4.0IO
Address: AEh
-21-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
PORT 3
(initial=FFh, input mode)
Bit:
7
P3.7
6
P3.6
5
P3.5
4
P3.4
3
P3.3
2
P3.2
1
P3.1
0
P3.0
Mnemonic: P3
Address: B0h
P3.7-0: P3 can be selected as input or output mode by the P3IO register, At initial reset, P3IO is
set to 0FFH, P3 is used as input mode. When P3IO is set to 00h, the P3 is used as
CMOS output mode. Special function of P3 is described below.
P3.5
T1
Timer/Counter 1 external count input
P3.4
T0
Timer/Counter 0 external count input
P3.3
External
interrupt 1
INT1
P3.2
External interrupt 0
INT0
CID REGISTER
(initial=00H,read only)
Bit:
7
6
5
4
3
2
1
0
FCLK FDATA FCD DTMFD FDR
ALGO
RNG
Mnemonic: CIDR
Address: B1h
This SFR indicates the CID signal immediately. Register data is set or cleared by hardware only.
FCLK: FSK serial clock with the baud rate of 1200Hz.
FDATA: FSK serial bit data.
FCD: Set when FSK carrier is detected. Cleared when FSK carrier is disappeared.
DTMFD: Set when DTMF decoded data is ready. Cleared when DTMF signal ends.
FDR: Set when FSK 8 bits data is ready. Cleared before next FSK start bit comes
ALGO: Dual tone Alert signal Guard time detect signal. Set when a guard time qualified dual tone
alert signal has been detected. Cleared when the guard time qualified dual tone alert
signal is absent.
RNG: Ring detection bit. High to indicate the detection of line reversal and/or ringing.
CID FLAG GENERATOR
(initial=00H)
Bit:
7
6
5
4
3
2
1
FSF DTMFDF FDRF ALGOF
Mnemonic: CIDFG
Address: B2h
FSF: Set when FSK Latch clock low to high. Cleared by software
DTMFDF: Set when DTMFD low to high. Cleared by software
FDRF: Set when FDR low to high. Cleared by software.
ALGOF: Set when ALGO low to high. Cleared by software.
RNGF: Set when RNG low to high. Cleared by software.
CID POWER CONTROL REGISTER
0
RNGF
(initial=00H)
Bit:
7
6
5
4
3
2
1
CIDE
FSKE
CASE
Mnemonic: CIDPCR
Address: B3h
CIDE: Global enable CID function. Low to disable all functions of CID parts.
-22-
0
DTMFE
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
FSKE: Enable FSK demodulation circuit.
CASE: Enable Dual Tone Alert Signal detection circuit.
DTMFE: Enable DTMF demodulation circuit.
FSK DATA REGISTER
Bit:
FD7-0:
7
6
FD7
FD6
Mnemonic: FSKDR
8 bits FSK demodulated data.
(initial=XXH)
5
FD5
4
FD4
3
FD3
DTMF DATA REGISTER
2
1
FD2
FD1
Address: B4h
0
FD0
(initial=XXH)
Bit:
7
6
5
4
3
CASH CASL DTMFH DTMFL
DD3
Mnemonic: DTMFDR
CASH: Set when Dual Tone Alert Signal high tone is detected.
CASL: Set when Dual Tone Alert Signal low tone is detected.
DTMFH: Set when DTMF high tone is detected.
DTMFL: Set when DTMF low tone is detected.
DD3-0: 4 bits DTMF demodulated data.
DTMF PRESENT TIME REGISTER
2
1
DD2
DD1
Address: B5h
0
DD0
(initial=19H)
Bit:
7
6
5
4
3
2
1
0
DPT6
DPT5
DPT4
DPT3
DPT2
DPT1
DPT0
DPT7
Mnemonic: DTMFPT
Address: B6h
The clock period of guard-time timer is 0.8582mS. The default DTMF present time is 21.45mS.
DPT7-0: The pre-set data register for counting DTMF present time. When DTMF is detected(Est
low to high), the guard timer starts to up-count from 00H. As the guard timer is equal to
the value of DTMFPT, the exist of the DTMF is accepted. Est changes to low state to
stop and reset the counter.
DTMF ABSENT TIME REGISTER
(initial=19H)
Bit:
7
6
5
4
3
2
1
0
DAT7
DAT6
DAT5
DAT4
DAT3
DAT2
DAT1
DAT0
Mnemonic: DTMFAT
Address: B7h
The clock period of guard-time timer is 0.8582mS. The default DTMF absent time is 21.45mS.
DAT7-0:The pre-set data register for counting DTMF absent time. When DTMF is absent(Est high
to low), the guard timer starts to up-count from 00H. As the guard timer is equal to the value of
DTMFAT, the finish of DTMF is recognized. Est changes to low state to stop and reset the
counter.
INTERRUPT PRIORITY
(initial=00H)
-23-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
Bit:
IP.7:
PS1:
PT1:
PX1:
PT0:
PX0:
7
-
6
PS1
5
-
4
-
3
PT1
2
PX1
1
PT0
0
PX0
Mnemonic: IP
Address: B8h
This bit is un-implemented and will read high.
This bit defines the Serial port interrupt priority. PS1 = 1 sets it to higher priority level
This bit defines the Timer 1 interrupt priority. PT1 = 1 sets it to higher priority level.
This bit defines the External interrupt 1 priority. PX1 = 1 sets it to higher priority level.
This bit defines the Timer 0 interrupt priority. PT0 = 1 sets it to higher priority level.
This bit defines the External interrupt 0 priority. PX0 = 1 sets it to higher priority level.
DTMF GENERATOR REGISTER
(initial=00H)
Bit:
7
6
DTGE
Mnemonic: DTMFG
5
HE
4
LE
3
L1
2
1
L0
H1
Address: BAh
0
H0
L1
L0
H1
H0
Selected tone
x
x
0
0
1209Hz
x
x
0
1
1336Hz
x
x
1
0
1477Hz
x
x
1
1
1633Hz
0
0
x
x
697Hz
0
1
x
x
770Hz
1
0
x
x
852Hz
1
1
x
x
941Hz
LE: Enable low group frequency output.
HE: Enable high group frequency output.
DTGE: Enable dual tone output to DTMF pin.
COMPARATOR REGISTER
Bit:
RESC:
7
-
6
-
(initial=00H)
5
-
4
-
3
RESC
2
REF
1
-
0
COMPEN
Mnemonic: COMPR
Address: BBh
Result of the comparator. Set when positive analog input voltage is(VPOS or
1.0v internal regular output) higher than negative analog input voltage(VNEG)
RESC is a read only bit.
REF:
REF=0 reference input from analog input voltage(VPOS/P4.4) pin.
REF=1 reference input from the internal regulator output.
COMPEN:
COMPEN=0 Disable comparator
COMPEN=1 Enable comparator
IDLE RELEASED CONDITION REGISTER 1
(initial=00H)
-24-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
Bit:
7
-
6
IRCS1
5
-
4
-
3
IRCT1
2
IRCX1
1
IRCT0
0
IRCX0
Mnemonic: IRC1
Address: BCh
One of the bit of IRC1 and IRC2 will be set by hardware to record the idle released condition
when the idle mode is released. IRC1 and IRC2 can be set by hardware and can be R/W by
software.
IRCS1: Idle mode released by Serial port interrupt flag.
IRCT1: Idle mode released by Timer 1 interrupt flag.
IRCX1: Idle mode released by external interrupt 1 flag.
IRCT0: Idle mode released by Timer 0 interrupt flag.
IRCX0: Idle mode released by external interrupt 0 flag.
IDLE RELEASED CONDITION REGISTER 2
Bit:
7
-
6
-
(initial=00H)
5
4
3
2
IRCWDI IRCCOMP IRCDIV IRCCID
1
IRCX3
0
IRCX2
Mnemonic: IRC2
Address: BDh
One of the bit of IRC1 and IRC2 will be set by hardware to record the idle released condition
when the idle mode is released. IRC1 and IRC2 can be set by hardware and can be R/W by
software.
IRCWDI: Idle mode released by Watchdog timer interrupt flag.
IRCCOMP: Idle mode released by comparator interrupt flag.
IRCDIV: Idle mode released by Divider interrupt flag.
IRCCID: Idle mode released by CID interrupt flag.
IRCX3: Idle mode released by External Interrupt 3 flag.
IRCX2: Idle mode released by External Interrupt 2 flag.
CAS TONE PRESENT TIME REGISTER
(initial=0FH)
Bit:
7
6
5
4
3
2
1
0
CASPT7 CASPT6 CASPT5 CASPT4 CASPT3 CASPT2 CASPT1 CASPT0
Mnemonic: CASPT
Address: BEh
The clock period of guard-time timer is 0.8582mS. The default alert tone present time is 12.87mS.
CASPT7-0: The pre-set data register for counting CAS tone present time. When CAS tone is
detected (ALGR low to high), the guard timer starts to up-count from 00H. As the
guard timer is equal to the value of CASPT, the exist of the CAS tone is accepted.
ALGR changes to low state to stop and reset the counter.
CAS TONE ABSENT TIME REGISTER
(initial=0FH)
Bit:
7
6
5
4
3
2
1
0
CASAT7 CASAT6 CASAT5 CASAT4 CASAT3 CASAT2 CASAT1 CASAT0
Mnemonic: CASAT
Address: BFh
The clock period of guard-time timer is 0.8582mS. The default alert tone absent time is 12.87mS.
CASAT7-0: The pre-set data register for counting CAS tone absent time. When CAS tone is
absent (ALGR high to low), the guard timer starts to up-count from 00H. As the
guard timer is equal to the value of CASAT, the finish of CAS tone is recognized.
ALGR changes to high state to stop and reset the counter.
SERIAL PORT CONTROL
(initial=00H)
-25-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
Bit:
7
SF1
6
LCDON
5
REGON
4
REN1
3
SFQ
2
SEDG
1
CLKIO
0
SIO
Mnemonic: SCON1
Address: C0h
SF1: Serial port interrupt flag. When 8-bits data is transceived completely, SF1 is set by
hardware. SF1 is cleared when serial interrupt routine is executed or cleared by software.
LCDON: LCD waveform enable control. 0 to Disable LCD display, 1 to Enable LCD display.
REGON: Regulator on/off control. 0 to disable regulator, 1 to regulator.
REN1: Set REN1 from 0 to 1 to start the serial port1 to receive 8-bit serial data.
SFQ: SFQ=0 Serial clock output frequency is equal to fOSC /2
SFQ=1 Serial clock output frequency is equal to fOSC /256
SEDG: SEDG=0 Serial data latched at falling edge of clock, SCLK=Low initially.
SEDG=1 Serial data latched at rising edge of clock, SCLK=High initially.
CLKIO: CLKIO=0 P4.0(SCLK) work as output mode
CLKIO=1 P4.0(SCLK) work as input mode
SIO:
SIO=0 P4.0 & P4.1 work as normal I/O pin
SIO=1 P4.0 & P4.1 work as Serial port1 function
SERIAL DATA BUFFER 1
Bit:
(initial=00H) Read Only
7
6
5
4
3
2
1
0
SBUF1.7 SBUF1.6 SBUF1.5 SBUF1.4 SBUF1.3 SBUF1.2 SBUF1.1 SBUF1.0
Mnemonic: SBUF1
Address: C1h
SBUF1.7-0: Serial data on the serial port 1 is read from or written to this location. It actually
consists of two separate internal 8-bit registers. One is the receive register, and the
other is the transmit buffer. Any read access gets data from the receive data buffer,
while write access is to the transmit data buffer.
REGULATOR VOLTAGE CONTROL REGISTER
Bit:
7
-
6
-
5
-
4
-
(initial=00H)
3
2
1
0
REGVC.3 REGVC.2 REGVC.1 REGVC.0
Mnemonic: REGVC
Address: C2h
REGVC.3-0: 4 bits to tune the regulator output voltage.
POWER MANAGEMENT REGISTER
Bit:
7
XT/RG
6
RGMD
5
RGSL
(initial=XXX00XX1B)
4
X2OFF
3
X1OFF
2
-
1
-
0
-
Mnemonic: PMR
Address: C4h
XT/RG :Crystal/RC Oscillator Select. Setting this bit selects crystal or external clock as system
clock source. Clearing this bit selects the on-chip RC oscillator as clock source. X1UP
(STATUS.4) must be set to 1 and X1OFF (PMR.3) must be cleared before this bit can be
set. Attempts to set this bit without obeying these conditions will be ignored. This bit is
set to 1 after a power-on or reset pin reset and unchanged by WDT reset.
RGMD: RC Mode Status. This bit indicates the current clock source of micro-controller. When
cleared, CPU is operating from the external crystal or oscillator. When set, CPU is
-26Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
operating from the on-chip RC oscillator. This bit is cleared to 0 after a power-on or
reset pin reset and unchanged by WDT reset.
RGSL: RC Oscillator Select. This bit selects the clock source following a resume from Power
Down Mode. Setting this bit allows device operating from RC oscillator when a resume
from Power Down Mode. When this bit is cleared, the device will hold operation until the
crystal oscillator has warmed-up following a resume from Power Down Mode. This bit is
cleared to 0 after a power-on or reset pin reset and unchanged by WDT reset.
X2OFF: Set to disable sub-oscillator (32KHz oscillator)
X1OFF:Crystal Oscillator Disable. Setting this bit disables the external crystal oscillator. This bit
can only be set to 1 while the micro-controller is operating from the RC oscillator. Clearing
this bit restarts the crystal oscillator, the X1UP (STATUS.4) bit will be set after crystal
oscillator warmed-up has completed.
Note: The bit0 of this SFR must be set to 1.
STATUS REGISTER
Bit:
7
X2UP
(initial=00H)
6
HIP
5
LIP
4
X1UP
3
-
2
1
-
-
0
-
Mnemonic: STATUS
Address: C5h
X2UP:Sub-crystal oscillator warm-up status. When set, this bit indicates the crystal oscillator has
completed the warm-up delay. When X2OFF bit is set, hardware will clear this bit. There
are two options which are selected by option code for warm-up delay, one is 1024 clocks
warm-up delay, other is 65536 clocks warm-up delay.
HIP: High Priority Interrupt Status. When set, it indicates that software is servicing a high priority
interrupt. This bit will be cleared when the program executes the corresponding RETI
instruction.
LIP: Low Priority Interrupt Status. When set, it indicates that software is servicing a low priority
interrupt. This bit will be cleared when the program executes the corresponding RETI
instruction.
X1UP:Crystal Oscillator Warm-up Status. when set, this bit indicates the crystal oscillator has
completed the 65536 clocks warm-up delay. Each time the crystal oscillator is restarted by
exit from power down mode or the X1OFF bit is set, hardware will clear this bit. This bit is
set to 1 after a power-on reset. When this bit is cleared, it prevents software from setting
the XT/RG bit to enable CPU operation from crystal oscillator. There are two options
which is selected by option code for warm-up delay, one is 4096 clocks warm-up delay,
other is 65536 clocks warm-up delay.
FSK TRANSIMT CONTROL REGISTER
Bit:
7
FTE
6
FTM
(initial=00H)
5
FDS
4
-
Mnemonic: FSKTC
FTE: FSK transmit Enable; Enable:1, Disable=0
FTM: FSK signal Standard; Bellcore:1, V.23=0
FDS: FSK data sending status
LO0, LO1: FSK transmit level option
FSK output level
LO1
-27-
3
-
2
-
1
LO1
0
LO0
Address: C6h
LO0
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
150mV
120mV
95mV
75mV
0
0
1
1
0
1
0
1
FSK TRANSMIT DATA BUFFER
Bit:
(initial=00H)
7
6
5
4
3
2
1
0
FSKTB.7 FSKTB.6 FSKTB.5 FSKTB.4 FSKTB.3 FSKTB.2 FSKTB.1 FSKTB.0
Mnemonic: FSKTB
FSKTB.0:Only This bit will be latched and send out as FSK signal
DIVIDER CONTROL
Bit:
Address: C7h
(initial=01H)
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
DIVA
Mnemonic: DIVC
Address: C8h
DIVA: Divider available control bit. This bit is set or cleared by software to enable/disable divider.
DIVA=1 to enable the divider. DIVA=0 to disable the divider. DIVA is reset after reset.
PROGRAM STATUS WORD
Bit:
7
CY
(initial=00H)
6
AC
5
F0
4
RS1
Mnemonic: PSW
3
RS0
2
OV
1
F1
0
P
Address: D0h
CY:
Carry flag. Set for an arithmetic operation which results in a carry being generated from
the ALU. It is also used as the accumulator for the bit operations.
AC:
Auxiliary carry. Set when the previous operation resulted in a carry from the high order
nibble.
F0:
User flag 0. General purpose flag that can be set or cleared by the user.
RS.1-0: Register bank select bits:
RS1 RS0 Register bank Address
0
0
0
00-07h
0
1
1
08-0Fh
1
0
2
10-17h
1
1
3
18-1Fh
OV:
F1:
P:
Overflow flag. Set when a carry was generated from the seventh bit but not from the 8th bit
as a result of the previous operation, or vice-versa.
User Flag 1. General purpose flag that can be set or cleared by the user by software.
Parity flag. Set/cleared by hardware to indicate odd/even number of 1's in the accumulator.
-28-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
WATCHDOG CONTROL
Bit:
7
-
(initial: note)
6
POR
5
-
4
WFS
3
WDIF
2
WTRF
1
EWT
0
RWT
Mnemonic: WDCON
Address: D8h
POR: Power-on reset flag. Hardware will set this flag when system is powered on and this flag is
cleared only by software.
WFS: Watchdog Timer Frequency Select. Set to select FS as WDT clock input. Clear to select
FOSC as WDT clock input.
WDIF: Watchdog Timer Interrupt flag. This bit is set whenever the time-out occurs in the
watchdog timer. If the Watchdog interrupt is enabled (EIE.5), then an interrupt will occur
(if the global interrupt enable is set and other interrupt requirements are met). Software or
any reset can clear this bit.
WTRF: Watchdog Timer Reset Flag. Hardware will set this bit when the watchdog timer causes a
reset. Software can read it but must clear it manually. A power-fail reset will also clear the
bit. This bit helps software in determining the cause of a reset. If EWT = 0, the
watchdog timer will have no effect on this bit.
EWT: Enable Watchdog timer Reset. Setting this bit will enable the Watchdog timer Reset
function.
RWT: Reset Watchdog Timer. This bit helps in putting the watchdog timer into a known state. It
also helps in resetting the watchdog timer before a time-out occurs. Failing to set the EWT
before time-out will cause an interrupt, if EWDI (EIE.5) is set, and 512 clocks after that a
watchdog timer reset will be generated if EWT is set. This bit is self-clearing by hardware.
Note:
The WDCON SFR is set to a 0x000xx0b on an external reset. WTRF is set to a 1 on a Watchdog
timer reset, but to a 0 on power on/down resets. WTRF is not altered by an external reset. POR is
set to 1 by a power-on reset. EWT is set to 0 on a Power-on reset and unaffected by other resets.
ACCUMULATOR
Bit:
(initial=00H)
7
ACC.7
6
ACC.6
5
ACC.5
4
ACC.4
3
ACC.3
Mnemonic: ACC
2
ACC.2
1
ACC.1
0
ACC.0
Address: E0h
ACC.7-0:The ACC register.
EXTENDED INTERRUPT ENABLE
Bit:
7
-
6
-
(initial=00H)
5
EWDI
4
ECOMP
Mnemonic: EIE
EIE.7-6:Reserved bits.
EWDI: Enable Watchdog timer interrupt.
ECOMP: Enable comparator interrupt.
EDIV: Enable Divider interrupt.
ECID: Enable CID interrupt.
EX3: Enable External Interrupt 3.
EX2: Enable External Interrupt 2.
3
EDIV
2
ECID
1
EX3
0
EX2
Address: E8h
-29-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
B REGISTER
(initial=00H)
Bit:
7
B.7
6
B.6
5
B.5
4
B.4
3
B.3
Mnemonic: B
2
B.2
1
B.1
0
B.0
Address: F0h
B.7-0:The B register serves as a second accumulator.
EXTENDED INTERRUPT PRIORITY
Bit:
7
-
6
-
(initial=00H)
5
PWDI
4
PCOMP
3
PDIV
2
PCID
1
PX3
0
PX2
Mnemonic: EIP
Address: F8h
PWDI: Watchdog timer interrupt priority. 0 = Low priority, 1 = High priority.
PCOMP: Comparator interrupt priority. 0 = Low priority, 1 = High priority.
PDIV: Divider Interrupt Priority. 0 = Low priority, 1 = High priority.
PCID: CID Interrupt Priority. 0 = Low priority, 1 = High priority.
PX3: External Interrupt 3 Priority. 0 = Low priority, 1 = High priority.
PX2: External Interrupt 2 Priority. 0 = Low priority, 1 = High priority.
CID GAIN CONTROL DATA
Bit:
7
BIT7
(initial=00H)
6
BIT6
5
BIT5
4
BIT4
3
BIT3
2
BIT2
1
BIT1
0
BIT0
Mnemonic: CIDGD
Address: F9h
CIDGD.7-0: The data value of programmable CID input filter gain and hysteresis.
CID GAIN CONTROL ADDRESS
Bit:
7
-
(initial=00H)
6
-
5
-
4
-
Mnemonic: CIDGA
3
BIT3
2
BIT2
1
BIT1
0
BIT0
Address: FAh
CIDGA.3:
The CIDGD latch control signal. Rising high pulse to latch CIDGD into CID gain
control register.
CIDGA.2-0: The address to indicate CID input gain control registers.
-30-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
6.3
Initial State of Registers
The following table lists the initial state of registers after different reset functions.
WDT Reset
SFR item
Reset initial
POR
value
ACC, B, STATUS, PSW,
00h
00h
00h
SP,
07h
07h
07h
P0, P1, P2, P3, P4, P0IO, P1IO, P2IO, P3IO,
ffh
ffh
ffh
P4IO
DPL, DPH, DPL1, DPH1, DPS
00h
00h
00h
PCON, TCON, TMOD,
00h
00h
00h
TL0, TL1, TH0, TH1,
00h
00h
00h
CKCON1, CKCON2, SCON1, SBUF1,
00h
00h
00h
REGVC,
EIF, IE, HB, IP, EIE, EIP
00h
00h
00h
P1SR, P1EF, P1H, P2H, P3H, P4H,
00h
00h
00h
CIDR, CIDFG, CIDPCR, CIDGD, CIDGA,
00h
00h
00h
FSKDR, DTMFDR,
******** B
******** B
******** B
DTMFPT, DTMFAT,
19h
19h
19h
DTMFG, COMPR, IRC1, IRC2, FSKTC,
00h
00h
00h
FSKTB,
CASPT, CASAT,
0fh
0fh
0fh
PMR
10000xx1B
10000xx1B uuu00xx1B
DIVC,
01h
01h
01h
WDCON
0u000uu0B
01000000B 0u0001u0B
x: Un-used
u: unchanged
*: Depend on circuit detection
-31-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
6.4
Instruction
The W925E/C625 executes all the instructions of the standard 8032 family. However, timing of
these instructions is different. In the W925E/C625, each machine cycle consists of 4 clock
periods, while in the standard 8032 it consists of 12 clock periods. Also, in the W925E/C625 there
is only one fetch per machine cycle i.e. 4 clocks per fetch, while in the standard 8032 there can
be two fetches per machine cycle, which works out to 6 clocks per fetch.
Table 2 Instructions that affect Flag settings
Instruction
Carry
Overflow
INC,DEC
ADD
ADDC
SUBB
MUL
DIV
DA A
RRC A
RLC A
X
X
X
0
0
X
X
X
X
X
X
X
X
Auxiliary
Carry
X
X
X
Instruction
Carry
SETB C
CLR C
CPL C
ANL C, bit
ANL C, bit
ORL C, bit
ORL C, bit
MOV C, bit
CJNE
1
0
X
X
X
X
X
X
X
Overflow
Auxiliary
Carry
A "X" indicates that the modification is as per the result of instruction.
A "-" indicates that the flag is not effected by the instruction.Table 3 Instruction Timing for
W925E/C625
Instruction
HEX
Op-Code
Bytes
Machine
Cycles
Instruction
HEX
Op-Code
Bytes
Machine
Cycles
NOP
00
1
1
ANL A, R0
58
1
1
ADD A, R0
28
1
1
ANL A, R1
59
1
1
ADD A, R1
29
1
1
ANL A, R2
5A
1
1
ADD A, R2
2A
1
1
ANL A, R3
5B
1
1
ADD A, R3
2B
1
1
ANL A, R4
5C
1
1
ADD A, R4
2C
1
1
ANL A, R5
5D
1
1
ADD A, R5
2D
1
1
ANL A, R6
5E
1
1
ADD A, R6
2E
1
1
ANL A, R7
5F
1
1
ADD A, R7
2F
1
1
ANL A, @R0
56
1
1
ADD A, @R0
26
1
1
ANL A, @R1
57
1
1
ADD A, @R1
27
1
1
ANL A, direct
55
2
2
ADD A, direct
25
2
2
ANL A, #data
54
2
2
ADD A, #data
24
2
2
ANL direct, A
52
2
2
ADDC A, R0
38
1
1
ANL direct, #data
53
3
3
ADDC A, R1
39
1
1
ANL C, bit
82
2
2
ADDC A, R2
3A
1
1
ANL C, /bit
B0
2
2
ADDC A, R3
3B
1
1
CJNE A, direct, rel
B5
3
4
ADDC A, R4
3C
1
1
CJNE A, #data, rel
B4
3
4
ADDC A, R5
3D
1
1
CJNE @R0, #data, rel
B6
3
4
ADDC A, R6
3E
1
1
CJNE @R1, #data, rel
B7
3
4
ADDC A, R7
3F
1
1
CJNE R0, #data, rel
B8
3
4
ADDC A, @R0
36
1
1
CJNE R1, #data, rel
B9
3
4
ADDC A, @R1
37
1
1
CJNE R2, #data, rel
BA
3
4
ADDC A, direct
35
2
2
CJNE R3, #data, rel
BB
3
4
ADDC A, #data
34
2
2
CJNE R4, #data, rel
BC
3
4
ACALL addr11
71,91,B1,
11,31,51,
2
3
CJNE R5, #data, rel
BD
3
4
-32-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
D1,F1
AJMP ADDR11
01,21,41,
61,81,A1,
C1,E1
2
3
CJNE R6, #data, rel
-33-
BE
3
4
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
Table 3. Instruction Timing for W925E/C625, continued
Instruction
HEX
Op-Code
Bytes
Machine
Cycles
Instruction
HEX
Op-Code
Bytes
Machine
Cycles
CJNE R7, #data, rel
BF
3
4
JC rel
40
2
3
CLR A
E4
1
1
JNC rel
50
2
3
CPL A
F4
1
1
JB bit, rel
20
3
4
CLR C
C3
1
1
JNB bit, rel
30
3
4
CLR bit
C2
2
2
JBC bit, rel
10
3
4
CPL C
B3
1
1
LCALL addr16
12
3
4
CPL bit
B2
2
2
LJMP addr16
02
3
4
DEC A
14
1
1
MUL AB
A4
1
5
DEC R0
18
1
1
MOV A, R0
E8
1
1
DEC R1
19
1
1
MOV A, R1
E9
1
1
DEC R2
1A
1
1
MOV A, R2
EA
1
1
DEC R3
1B
1
1
MOV A, R3
EB
1
1
DEC R4
1C
1
1
MOV A, R4
EC
1
1
DEC R5
1D
1
1
MOV A, R5
ED
1
1
DEC R6
1E
1
1
MOV A, R6
EE
1
1
DEC R7
1F
1
1
MOV A, R7
EF
1
1
DEC @R0
16
1
1
MOV A, @R0
E6
1
1
DEC @R1
17
1
1
MOV A, @R1
E7
1
1
DEC direct
15
2
2
MOV A, direct
E5
2
2
DEC DPTR
A5
1
2
MOV A, #data
74
2
2
DIV AB
84
1
5
MOV R0, A
F8
1
1
DA A
D4
1
1
MOV R1, A
F9
1
1
DJNZ R0, rel
D8
2
3
MOV R2, A
FA
1
1
DJNZ R1, rel
D9
2
3
MOV R3, A
FB
1
1
DJNZ R5, rel
DD
2
3
MOV R4, A
FC
1
1
DJNZ R2, rel
DA
2
3
MOV R5, A
FD
1
1
DJNZ R3, rel
DB
2
3
MOV R6, A
FE
1
1
DJNZ R4, rel
DC
2
3
MOV R7, A
FF
1
1
DJNZ R6, rel
DE
2
3
MOV R0, direct
A8
2
2
DJNZ R7, rel
DF
2
3
MOV R1, direct
A9
2
2
DJNZ direct, rel
D5
3
4
MOV R2, direct
AA
2
2
INC A
04
1
1
MOV R3, direct
AB
2
2
INC R0
08
1
1
MOV R4, direct
AC
2
2
INC R1
09
1
1
MOV R5, direct
AD
2
2
INC R2
0A
1
1
MOV R6, direct
AE
2
2
INC R3
0B
1
1
MOV R7, direct
AF
2
2
INC R4
0C
1
1
MOV R0, #data
78
2
2
INC R5
0D
1
1
MOV R1, #data
79
2
2
INC R6
0E
1
1
MOV R2, #data
7A
2
2
INC R7
0F
1
1
MOV R3, #data
7B
2
2
INC @R0
06
1
1
MOV R4, #data
7C
2
2
INC @R1
07
1
1
MOV R5, #data
7D
2
2
INC direct
05
2
2
MOV R6, #data
7E
2
2
INC DPTR
A3
1
2
MOV R7, #data
7F
2
2
JMP @A+DPTR
73
1
2
MOV @R0, A
F6
1
1
JZ rel
60
2
3
MOV @R1, A
F7
1
1
JNZ rel
70
2
3
MOV @R0, direct
A6
2
2
-34-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
Table 3. Instruction Timing for W925E/C625, continued
Instruction
HEX
Op-Code
Bytes
Machine
Cycles
Instruction
HEX
Op-Code
Bytes
Machine
Cycles
1
MOV @R1, direct
A7
2
2
RL A
23
1
MOV @R0, #data
76
2
2
RLC A
33
1
1
MOV @R1, #data
77
2
2
RR A
03
1
1
MOV direct, A
F5
2
2
RRC A
13
1
1
MOV direct, R0
88
2
2
SETB C
D3
1
1
MOV direct, R1
89
2
2
SETB bit
D2
2
2
MOV direct, R2
8A
2
2
SWAP A
C4
1
1
MOV direct, R3
8B
2
2
SJMP rel
80
2
3
MOV direct, R4
8C
2
2
SUBB A, R0
98
1
1
MOV direct, R5
8D
2
2
SUBB A, R1
99
1
1
MOV direct, R6
8E
2
2
SUBB A, R2
9A
1
1
MOV direct, R7
8F
2
2
SUBB A, R3
9B
1
1
MOV direct, @R0
86
2
2
SUBB A, R4
9C
1
1
MOV direct, @R1
87
2
2
SUBB A, R5
9D
1
1
MOV direct, direct
85
3
3
SUBB A, R6
9E
1
1
MOV direct, #data
75
3
3
SUBB A, R7
9F
1
1
MOV DPTR, #data 16
90
3
3
SUBB A, @R0
96
1
1
MOVC A, @A+DPTR
93
1
2
SUBB A, @R1
97
1
1
MOVC A, @A+PC
83
1
2
SUBB A, direct
95
2
2
MOVX A, @R0
E2
1
2-9
SUBB A, #data
94
2
2
MOVX A, @R1
E3
1
2-9
XCH A, R0
C8
1
1
MOVX A, @DPTR
E0
1
2-9
XCH A, R1
C9
1
1
MOVX @R0, A
F2
1
2-9
XCH A, R2
CA
1
1
MOVX @R1, A
F3
1
2-9
XCH A, R3
CB
1
1
MOVX @DPTR, A
F0
1
2-9
XCH A, R4
CC
1
1
MOV C, bit
A2
2
2
XCH A, R5
CD
1
1
MOV bit, C
92
2
2
XCH A, R6
CE
1
1
ORL A, R0
48
1
1
XCH A, R7
CF
1
1
ORL A, R1
49
1
1
XCH A, @R0
C6
1
1
ORL A, R2
4A
1
1
XCH A, @R1
C7
1
1
ORL A, R3
4B
1
1
XCHD A, @R0
D6
1
1
ORL A, R4
4C
1
1
XCHD A, @R1
D7
1
1
ORL A, R5
4D
1
1
XCH A, direct
C5
2
2
ORL A, R6
4E
1
1
XRL A, R0
68
1
1
ORL A, R7
4F
1
1
XRL A, R1
69
1
1
ORL A, @R0
46
1
1
XRL A, R2
6A
1
1
ORL A, @R1
47
1
1
XRL A, R3
6B
1
1
ORL A, direct
45
2
2
XRL A, R4
6C
1
1
ORL A, #data
44
2
2
XRL A, R5
6D
1
1
ORL direct, A
42
2
2
XRL A, R6
6E
1
1
ORL direct, #data
43
3
3
XRL A, R7
6F
1
1
ORL C, bit
72
2
2
XRL A, @R0
66
1
1
ORL C, /bit
A0
2
2
XRL A, @R1
67
1
1
PUSH direct
C0
2
2
XRL A, direct
65
2
2
POP direct
D0
2
2
XRL A, #data
64
2
2
RET
22
1
2
XRL direct, A
62
2
2
RETI
32
1
2
XRL direct, #data
63
3
3
-35-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
6.5
Power Management
The W925E/C625 has 3 operation mode, normal mode, idle mode and power down mode to
manage the power consumption.
Normal Mode
Normal mode is used in the normal operation status. All functions can be worked in the normal
mode.
Idle Mode
The user can put the device into idle mode by writing 1 to the bit PCON.0. The instruction that
sets the idle bit is the last instruction that will be executed before the device goes into Idle Mode.
In the Idle mode, the clock to the CPU is halted, but not to the Interrupt, Timer, Watchdog timer,
Divider, Comparator and CID blocks. This forces the CPU state to be frozen; the Program
counter, the Stack Pointer, the Program Status Word, the Accumulator and the other registers
hold their contents. The port pins hold the logical states they had at the time Idle was activated.
The Idle mode can be terminated in two ways. Since the interrupt controller is still active, the
activation of any enabled interrupt can wake up the processor. This will automatically terminate
the Idle mode and clear the Idle bit. And if bit IDLT(PCON.4) is cleared the Interrupt Service
Routine(ISR) will be executed, else the idle mode is released directly without any execution of
ISR. After the ISR, execution of the program will continue from the instruction, which put the
device into Idle mode.
The Idle mode can also be exited by activating the reset. The device can be put into reset either
by applying a low on the external RESET pin or a power on/fail reset condition or a Watchdog
timer reset. The external reset pin has to be held low for at least two machine cycles i.e. 8 clock
periods to be recognized as a valid reset. In the reset condition the program counter is reset to
0000h and all the SFRs are set to the reset condition. Since the clock is still running in the period
of external reset therefore the instruction is executed immediately. In the Idle mode, the
Watchdog timer continues to run, and if enabled, a time-out will cause a watchdog timer interrupt
which will wake up the device. The software must reset the Watchdog timer in order to preempt
the reset which will occur after 512 clock periods of the time-out.
Power Down Mode
The device can be put into Power Down mode by writing 1 to bit PCON.1. The instruction that
does this will be the last instruction to be executed before the device goes into Power Down
mode. In the Power Down mode, all the clocks are stopped and the device comes to a halt. All
activity is completely stopped and the power consumption is reduced to the lowest possible value.
The port pins output the values held by their respective SFRs.
The W925E/C625 will exit the Power Down mode by reset or external interrupts or ring detected.
An external reset can be used to exit the Power down state. The low on RESET pin terminates
the Power Down mode, and restarts the clock. The on-chip hardware will now provide a delay of
65536 clock, which is used to provide time for the oscillator to restart and stabilize. Once this
delay is complete, an internal reset is activated and the program execution will restart from
0000h. In the Power down mode, the clock is stopped, so the Watchdog timer cannot be used to
provide the reset to exit Power down mode.
The W925E/C625 can be woken from the Power Down mode by forcing an external interrupt pin
activated and ring detected, provided the corresponding interrupt is enabled, while the global
enable(EA) bit is set. While the power down is released, the device will experience a warm-up
delay of 65536 clock cycles to ensure the stabilization of oscillation. Then device executes the
interrupt service routine for the corresponding external interrupt or CID interrupt. After the
interrupt service routine is completed, the program returns to the instruction after the one, which
put the device into Power Down mode and continues from there. When RGSL(PMR.5) bit is set to
1, the CPU will use the internal RC oscillator instead of crystal to exit Power Down mode. The
-36Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
micro-controller will automatically switch from RC oscillator to crystal after a warm-up delay of
65536 crystal clocks. The RC oscillator runs at approximately 2−4 MHz. Using RC oscillator to
exit from Power Down mode saves the time for waiting crystal start-up. It is useful in the low
power system which usually be awakened from a short operation then returns to Power Down
mode.
6.6
Reset
The user has several hardware related options for placing the W925E/C625 into reset condition.
In general, most register bits go to their reset value irrespective of the reset condition, but there
are few flags that initial states are dependant on the source of reset. User can recognize the
cause of reset by reading the flags. There are three ways of putting the device into reset state.
They are External reset, Power on reset and Watchdog reset.
External Reset
The device continuously samples the RESET pin at state C4 of every machine cycle. Therefore,
the RESET pin must be held for at least 2 machine cycles to ensure detection of a valid RESET
low. The reset circuitry then synchronously applies the internal reset signal. Thus, the reset is a
synchronous operation and requires the clock to be running to cause an external reset.
Once the device is in reset condition, it will remain so as long as RESET is 0. Even after RESET
is deactivated, the device will continue to be in reset state for up to two machine cycles, and then
begin program execution from 0000h. There is no flag associated with the external reset
condition. However, since some flags indicate the cause of other two reset, the external reset can
be considered as the default reset if those two flags are cleared.
Watchdog Timer Reset
The Watchdog timer is a free running timer with programmable time-out intervals. The user can
reset the watchdog timer at any time to avoid producing the flag WDIF. If the Watchdog reset is
enabled and the flag WDIF is set high, the watchdog timer reset is performed after the additional
512 clocks come. This places the device into the reset condition. The reset condition is
maintained by hardware for two machine cycles. Once the reset is removed the device will begin
execution from 0000h.
6.7
Interrupt
The W925E/C625 has a two priority levels interrupt structure with 11 interrupt sources. Each of
the interrupt sources has an individual priority bit, flag, interrupt vector and enable bit. In addition,
the interrupts can be globally enabled or disabled.
Interrupt Sources
The External Interrupts INT0 and INT1 can be either edge triggered or level triggered,
depending on bits IT0 and IT1. The bits IE0 and IE1 in the TCON register are the flags which are
checked to generate the interrupt. In the edge triggered mode of the INT0 and the INT1 inputs
are sampled in every machine cycle. If the sample is high in one cycle and low in the next, then a
high to low transition is detected and the interrupts request flag IEx in TCON is set. The flag bit
requests the interrupt. Since the external interrupts are sampled every machine cycle, they have
to be held high or low for at least one complete machine cycle. The IEx flag is automatically
cleared when the service routine is called. If the level triggered mode is selected, then the
requesting source has to hold the pin low until the interrupt is serviced. The IEx flag will not be
cleared by the hardware on entering the service routine. If the interrupt continues to be held low
even after the service routine is completed, then the processor may acknowledge another
interrupt request from the same source. Note that the external interrupts INT2 to INT3 are edge
triggered only.
-37-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
The TF0, TF1 flags generate the Timer 0, 1 Interrupts. These flags are set by the overflow in the
Timer 0, Timer 1. The TF0 and TF1 flags are automatically cleared by the hardware when the
timer interrupt is serviced.
The Watchdog timer can be used as a system monitor or a simple timer. In either case, when the
time-out count is reached, the Watchdog timer interrupt flag WDIF (WDCON.3) is set. If the
enable bit EIE.5 enables the interrupt, then an interrupt will occur.
The Serial block can generate interrupts on reception or transmission. There are one interrupt
sources from the Serial block, which are obtained by SF1 in the SCON1. SF1 is cleared
automatically when the serial port interrupt is serviced.
The divider interrupt is generated by DIVF that is set when divider overflows. DIVF is set by
hardware and cleared when divider interrupt is serviced. The divider interrupt is enable/disable if
the bit EDIV is high/low.
The comparator interrupt is produced by COMPF, which is set when the RESC bit is changed
from low to high. RESC, which is the real-time result of comparator, is set when the voltage of
reference input is higher than the voltage of analog input.
The CID interrupt is generated by CIDF. The CIDF is a logic OR output of all CID flags which are
set by hardware and cleared by software. The structure of the CID flags is shown in Figure 6-4.
Each of the individual interrupts can be enabled or disabled by setting or clearing the
corresponding bits in the IE and EIE SFR. A bit EA, which is located in IE.7, is a global control bit
to enable/disable the all interrupt. When bit EA is zero all interrupts are disable and when bit EA
is high each interrupt is enable individually by the corresponding bit.
RNGF
FDRF
ALGOF
DTMFDF
FSF
CIDF
D
System clock
R
Clear by software
Figure 6-4 The Structure of CID Flags
Priority Level Structure
There are two priority levels for the interrupts, high and low. The interrupt sources can be
individually set to either high or low levels. Naturally, a higher priority interrupt cannot be
interrupted by a lower priority interrupt. However there exists a pre-defined hierarchy amongst the
interrupts themselves. This hierarchy comes into play when the interrupt controller has to resolve
simultaneous requests having the same priority level. This hierarchy is defined as shown below;
the interrupts are numbered starting from the highest priority to the lowest.
Interrupt
External interrupt 0
Flag
Name
IE0
Table 4 Interrupt table.
Flag
EN Bit
EN Bit
Location
Location
TCON.1
EX0
IE.0
Priority
1
(highest)
Timer0 overflow
TF0
TCON.5
ET0
IE.1
2
External interrupt 1
IE1
TCON.3
EX1
IE.2
3
Timer1 overflow
TF1
TCON.7
ET1
IE.3
4
-38-
Flag Cleared
by
hardware +
software
hardware +
software
hardware +
software
hardware +
software
Release Date : 2002/7/2
Revision : A6
Interrupt
Vector
03h
0Bh
13h
1Bh
W925E/C625
8-bit CID Microcontroller
Serial port
SF1
SCON1.7
ES1
IE.6
5
External interrupt 2
IE2
EXIF.0
EX2
EIE.0
6
External interrupt 3
IE3
EXIF.1
EX3
EIE.1
7
CID
CIDF
EXIF.2
ECID
EIE.2
8
Divider overflow
DIVF
EXIF.3
EDIV
EIE.3
9
Compare difference
COMPF
EXIF.4
ECOMP
EIE.4
10
Watchdog timer
WDIF
WDCON.3
EWDI
EIE.5
hardware
software
hardware
software
hardware
software
3Bh
+
43h
+
4Bh
53h
software
hardware
software
hardware
software
11
(lowest)
+
+
5Bh
+
63h
6Bh
software
Ps: The flags marked as the italic font are not bit-addressable.
The interrupt flags are sampled every machine cycle. In the same machine cycle, the sampled
interrupts are polled and their priority is resolved. If certain conditions are met then the hardware
will execute an internally generated LCALL instruction which will vector the process to the
appropriate interrupt vector address. The conditions for generating the LCALL are
1. An interrupt of equal or higher priority is not currently being serviced.
2. The current polling cycle is the last machine cycle of the instruction currently being executed.
3. The current instruction does not involve a write to IP, IE, EIP or EIE registers and is not a
RETI.
If any of these conditions is not met, then the LCALL will not be generated. The polling cycle is
repeated every machine cycle, with the interrupts being sampled in the same machine cycle. If an
interrupt flag is active in one cycle but not responded to, and is not active when the above
conditions are met, the denied interrupt will not be serviced. This means that active interrupts are
not remembered. Note that every polling cycle is new.
Execution continues from the vectored address until an RETI instruction is executed. On
execution of the RETI instruction, the processor pops out the top content of Stack to the PC. The
processor is not notified anything if the content of stack was changed. Note that a RET instruction
would perform exactly the same process as a RETI instruction, but it would not inform the
Interrupt Controller that the interrupt service routine is completed, and would leave the controller
still thinking that the service routine is underway.
6.8
Programmable Timers/Counters
The W925E/C625 has 2 16-bit timer/counters. There are two 8-bit registers to perform a 16-bit
counting register in every timer/counter. In timer/counter 0, TH0 is the upper 8 bits register and
TL0 is the lower 8 bits register. Similarly timer/counter 1 have two 8-bit registers, TH1 and TL1.
Each timer/counter has 4 kind of clock sources which are Fosc/4, Fosc/64, Fosc/1024 and Fs.
There are 3 operating modes in each timer/counter 0 and 1. The operating modes of timer/
counter0 is identical to timer/counter1. The overflow signal of each timer/counter is sampled at
phase 2 in every system machine cycle, therefore when the system clock and the timer/counter
clock both are from sub-oscillator, if the overflow frequency is higher than Fs/4 the overflow flag
can not be sampled correctly. Only one overflow flag can be sampled in a machine cycle others
will be missed.
MODE 0
-39-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
In Mode 0, the timer/counters act as 13-bit timer/counters. The 13 bits consist of 8 bits of THx and
lower 5 bits of TLx. The upper 3 bits of TLx are ignored.
The negative edge of the clock causes the content of the TLx register to increase one. When the
fifth bit in TLx moves from 1 to 0, then the count in the THx register is incremented. When the
count in THx moves from FFh to 00h, then the overflow flag TFx is set. The counted input is
enabled only if TRx is set and either GATE=0 or INTx =1. When C/ T is set to 0, then it will count
clock cycles, and if C/ T is set to 1, then it will count 1 to 0 transitions on T0 (P3.4) for timer 0 and
T1 (P3.5) for timer 1. When the 13-bit count reaches 1FFFh, the next count will cause it to rollover
to 0000h. The timer overflow flag TFx of the relevant timer is set and if enabled an interrupts will
occur. Note that when they are used as a timer, the bits of the CKCON1 select the time-base.
MODE1
Mode 1 is similar to Mode 0 except that the counting register forms a 16-bit counter, rather than a
13 bit counter.
TM0=CKCON1.2, CKCON1.3
(TM1=CKCON1.4, CKCON1.5)
Fosc/4
Fosc/64
Fosc/1024
Fs
T0 = P3.4
(T1 = P3.5)
00
01
10
11
mux
M1,M0 = TMOD.1,TMOD.0
(M1,M0 = TMOD.5,TMOD.4)
C/T = TMOD.2
(C/T = TMOD.6)
0
00
0
1
4
7
0
01
TL0
(TL1)
TR0 = TCON.4
(TR1 = TCON.6)
GATE = TMOD.3
(GATE = TMOD.7)
INT0 = P3.2
(INT1 = P3.3)
TFx
7
TH0
(TH1)
Interrupt
TF0
(TF1)
PS: Functions of timer1 are shown in brackets
Figure 6-5 Mode 0 & Mode 1 of Timer/Counter 0 & 1
MODE 2
Mode 2 is the Auto Reload Mode. In mode 2, TLx acts as an 8-bit count register, while THx holds
the reload value. When the TLx register overflows from FFh to 00h, the TFx bit is set and TLx is
reloaded with the content of THx, and the counting process continues from the reloaded TLx. The
reload operation leaves the content of the THx register unchanged. Counting is controlled by the
TRx bit and the proper setting of GATE and INTx pins.
BUZZER
In mode 2, timer 0 can be use to output an arbitrary frequency to the BUZ pin by programming
bit6 and bit7 of CKCON2. BUZ pin can be configured as key tone (KT) output by setting BUZSL
to high. When disable buzzer output by clearing ENBUZ to low, the BUZ output is in floating
status.
-40-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
In the case where timer 0 clock input is FT, the desired frequency for BUZ output = FT / (255 –
preset value + 1) / 2 (HZ).
CKCON2.5, CKCON2.4
Low
512Hz
TM0=CKCON1.2, CKCON1.3
(TM1=CKCON1.4, CKCON1.5)
Fosc/4
Fosc/64
Fosc/1024
Fs
T0 = P3.4
(T1 = P3.5)
1024Hz
2048Hz
00
CKCON2.6 CKCON2.7
=BUZSL
=ENBUZ
01
10
mux
11
KT
00
01
10
11
mux
C/T = TMOD.2
(C/T = TMOD.6)
0
FT
TL0
(TL1)
0
1
Pin BUZ
1/2
From
TM0
7
floating
TFx
Interrupt
TF0
(TF1)
TR0 = TCON.4
(TR1 = TCON.6)
GATE = TMOD.3
(GATE = TMOD.7)
INT0 = P3.2
(INT1 = P3.3)
0
7
TH0
(TH1)
PS: Functions of timer1 are shown in brackets
Figure 6-6 Mode 2 of Timer/Counter 0 & 1
When FT equals 32768 Hz, depending on the preset value of TM0, the BUZ pin will output a
single tone signal in the tone frequency range from 64 Hz to 16384 Hz. The relation between the
tone frequency and the preset value of TM0 is shown in the table below.
-41-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
Table 5 The relation between the tone frequency and the preset value of TM0
3rd octave
Tone
frequency
T
O
N
E
TM0 preset value
& BUZ frequency
4th octave
Tone
frequency
5th octave
TM0 preset value
& BUZ frequency
Tone
frequency
TM0 preset value
& BUZ frequency
C
130.81
83H
131.07
261.63
C1H
260.06
523.25
E1H
528.51
C#
138.59
8AH
138.84
277.18
C5H
277.69
554.37
E3H
564.96
D
146.83
90H
146.28
293.66
C8H
292.57
587.33
E4H
585.14
D#
155.56
97H
156.03
311.13
CBH
309.13
622.25
E6H
630.15
E
164.81
9DH
165.49
329.63
CEH
327.68
659.26
E7H
655.36
F
174.61
A2H
174.30
349.23
D1H
348.58
698.46
E9H
712.34
F#
185.00
A7H
184.09
369.99
D4H
372.35
739.99
EAH
744.72
G
196.00
ACH
195.04
392.00
D6H
390.08
783.99
EBH
780.19
G#
207.65
B1H
207.39
415.30
D9H
420.10
830.61
ECH
819.20
A
220.00
B6H
221.40
440.00
DBH
442.81
880.00
EDH
862.84
A#
233.08
BAH
234.05
466.16
DDH
468.11
932.23
EEH
910.22
246.94
BEH
248.24
Note: Central tone is DB (440 Hz).
493.88
DF
H
496.48
987.77
EFH
963.76
B
WATCHDOG TIMER
The Watchdog timer is a free-running timer that can be programmed by the user to serve as a
system monitor, a time-base generator or an event timer. It is basically a set of dividers that
divides the system clock. The divider output is selectable and determines the time-out interval. In
the condition of the timer-out expiring, the WDT interrupt and WDT reset may be executed if the
corresponding enable control bits are set. The interrupt will occur if the individual interrupt enable
and the global enable are set. The interrupt and reset functions are independent of each other
and may be used separately or together depending on the users software.
Fsub
Fosc
12
1
WD1,WD0
WDIF
WFS(WDCON.4)
EWDI(EIE.5)
13
16
15
18
00
01
10
11
RWT (WDCON.0)
19
21
WTRF
Time-out
selector
Reset Watchdog
Interrupt
512 clock
delay
Reset
Enable Watchdog timer reset
EWT(WDCON.1)
Figure 6-7 Watchdog Timer
The Watchdog timer should first be restarted by using RWT. This ensures that the timer starts
from a known state. The RWT bit is used to restart the watchdog timer. This bit is self clearing,
-42-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
i.e. after writing a 1 to this bit the software will automatically clear it. The watchdog timer will now
count clock cycles. The time-out interval is selected by the two bits WD1 and WD0 (CKCON.7
and CKCON.6). When the selected time-out occurs, the Watchdog interrupt flag WDIF
(WDCON.3) is set. After the time-out has occurred, the watchdog timer waits for an additional 512
clock cycles. The software must issue a RWT to reset the watchdog before the 512 clocks have
elapsed. If the Watchdog Reset EWT (WDCON.1) is enabled, then 512 clocks after the time-out,
if there is no RWT, a system reset due to Watchdog timer will occur. This will last for two machine
cycles, and the Watchdog timer reset flag WTRF (WDCON.2) will be set. This indicates to the
software that the watchdog was the cause of the reset.
When used as a simple timer, the reset and interrupt functions are disabled. The timer will set the
WDIF flag each time the timer completes the selected time interval. The WDIF flag is polled to
detect a time-out and the RWT allows software to restart the timer. The Watchdog timer can also
be used as a very long timer. The interrupt feature is enabled in this case. Every time the time-out
occurs an interrupt will occur if the global interrupt enable EA is set.
Table 6 Time-out values for the Watchdog timer
WD1
WD0
Watchdog
Fosc=
Reset of
Number of
Fosc=
32768 Hz
Clocks
Interval
Clocks
3.579545 MHz
12
0
0
4096
1.14
mS
0.125
S
4608
2
0
1
1
0
2
2
15
32786
9.15 mS
1S
33280
18
262144
73.23 mS
8S
262656
21
2097152
585.87 mS
64 S
2097664
2
The Watchdog timer will de disabled by a power-on/fail reset. The Watchdog timer reset does not
disable the watchdog timer, but will restart it. In general, software should restart the timer to put it
into a known state.
The control bits that support the Watchdog timer are discussed below.
WATCHDOG CONTROL
WDIF: WDCON.3 - Watchdog Timer Interrupt flag. This bit is set whenever the time-out occurs in
the watchdog timer. If the Watchdog interrupt is enabled (EIE.5), then an interrupt will
occur (if the global interrupt enable is set and other interrupt requirements are met).
Software or any reset can clear this bit.
WTRF: WDCON.2 - Watchdog Timer Reset flag. This bit is set whenever a watchdog reset
occurs. This bit is useful for determined the cause of a reset. Software must read it, and
clear it manually. A Power-fail reset will clear this bit. If EWT = 0, then this bit will not be
affected by the watchdog timer.
EWT: WDCON.1 - Enable Watchdog timer Reset. This bit when set to 1 will enable the
Watchdog timer reset function. Setting this bit to 0 will disable the Watchdog timer reset
function, but will leave the timer running
RWT: WDCON.0 - Reset Watchdog Timer. This bit is used to clear the Watchdog timer and to
restart it. This bit is self-clearing, so after the software writes 1 to it the hardware will
automatically clear it. If the Watchdog timer reset is enabled, then the RWT has to be set
by the user within 512 clocks of the time-out. If this is not done then a Watchdog timer
reset will occur.
1
1
CLOCK CONTROL
-43-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
WD1,WD0:
CKCON.7, CKCON.6 - Watchdog Timer Mode select bits. These two bits select the
time-out interval for the watchdog timer. The reset time is longer 512 clocks time
than the interrupt time-out value.
12
The default Watchdog time-out is 2 clocks, which is the shortest time-out period. The EWT,
WDIF and RWT bits are protected by the Timed Access procedure. This prevents software from
accidentally enabling or disabling the watchdog timer. More importantly, it makes it highly
improbable that errant code can enable or disable the watchdog timer.
6.9
Serial Port 1
The P4.0 and P4.1 can be used as a 8-bit serial input/output port1. P4.0 is the serial port 1 clock
I/O pin and P4.1 is the serial port 1 data I/O pin. The serial port 1 is controlled by SCON1 register
which is described as below.
SF1: Serial port 1 interrupt flag. When 8-bits data is transceived completely, SF1 is set by
hardware. SF1 is cleared when serial interrupt1 routine is executed or cleared by software.
REN1: Set REN1 from 0 to 1 to start the serial port1 to receive 8-bit serial data.
SFQ:
SFQ=0 Serial clock output frequency is equal to fOSC /2
SFQ=1 Serial clock output frequency is equal to fOSC / 256
SEDG:
SEDG=0 Serial data latched at falling edge of clock, SCLK=Low initially.
SEDG=1 Serial data latched at rising edge of clock, SCLK=High initially.
CLKIO:
CLKIO=0 P4.0(SCLK) work as output mode
CLKIO=1 P4.0(SCLK) work as input mode
SIO:
SIO=0 P4.0 & P4.1 work as normal I/O pin
SIO=1 P4.0 & P4.1 work as Serial port1 function
Any instruction causes a write to SBUF1 will start the transmission of serial port 1. As the REN1 is
from 0 to 1, the serial port 1 begins to receive a byte into SBUF1 in the frequency of the serial
clock. REN1 could be cleared by software after receive function begins. The LSB is transmitted/
received first. The I/O mode of serial clock pin is controlled by CLKIO. User has to take care the
initial state of the serial port pins.
C1
C2
C3
C4
REN1
P4.0
SEDG=1, rising latch
P4.0
SEDG=0, falling latch
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
SF1
P4.1
Data Input
NOTE: The serial clock frequency is fosc/2
Figure 6-8 Timing of the Serial Port 1 Input Function
-44-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
C1
C2
C3
C4
serial out
instruction
Ins.
P4.0
SEDG=1, falling changed
P4.0
SEDG=0, rising changed
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
SF1
P4.1
Data output
NOTE: The serial clock frequency is fosc/2
Figure 6-9 Timing of the Serial Port 1 Output Function
6.10 Comparator
A built-in comparator to compare the analog signal. There is a analog input paths from pin VNEG.
Two reference inputs, one is from pin VPOS and other is from regulator output. When the voltage
of positive input is higher than the negative input, the comparator output will be high. The
RESEC(COMPR.3) is the result of the comparison. An internal rising signal on RESC produces
interrupt flag of COMPF (EXIF.4). The flag COMPF is cleared when comparator interrupt routine
is executed or cleared by software. Set COMPEN to enable the comparator function.
VNEG(P4.2)
D
C3
VPOS(P4.4)
D
CK
EXIF.4
(COMPF)
Clr
Clr
RESET
REF1
REF
X.XV
REGULATOR
EN
RESC
CK
COMPF=0
COMPEN
SCON1.5(REGON)
Figure 6-10 The Configuration of Comparator
6.11 DTMF Generator
W925E/C625 provides a DTMF generator which outputs the dual tone multi-frequency signal to
the DTMF pin. The DTMF generator can work well at the operating frequency of 3.58MHz. A
DTMF generator register DTMFG controls the DTMF output and specifies the desired low/high
frequency. The tones are divided into two groups (low group and high group). When the
-45-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
generator is disable, the DTMF pin is in tri-state. The relation between the DTMF signal and the
corresponding touch tone keypad is shown in Figure 6-11.
C1
C2
C3
C4
R1
1
2
3
A
R2
4
5
6
B
R3
7
8
9
C
R4
*
0
#
D
Row/Col
R1
R2
R3
R4
C1
C2
C3
C4
Frequency
697 Hz
770 Hz
852 Hz
941 Hz
1209 Hz
1336 Hz
1477 Hz
1633 Hz
Figure 6-11 The Relation Between DTMF and Keypad
Bit:
7
6
DTGE
Mnemonic: DTMFGR
5
HE
4
LE
3
L1
2
1
L0
H1
Address: BAh
0
H0
L1
L0
H1
H0
Selected tone
x
x
0
0
1209Hz
x
x
0
1
1336Hz
x
x
1
0
1477Hz
x
x
1
1
1633Hz
0
0
x
x
697Hz
0
1
x
x
770Hz
1
0
x
x
852Hz
1
1
x
x
941Hz
LE: Enable low group frequency output.
HE: Enable high group frequency output.
DTGE: Enable dual tone output to DTMF pin.
6.12 FSK Generator
W925E/C625 provides a FSK generator which outputs the FSK signal to the DTMF pin. The FSK
output share with DTMF output pin. It can out FSK signal with 1200Hz baud rate of ITU-T V.23 or
Bellcore 202 signal. A FSK transmit data register (FSKTB) specifies the desired output data. The
FSK Transmit Control Register (FSKTC) can control whether the FSK signal will be output or not.
The relation timing is shown in Figure 6-12.
-46-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
Auto clear
Enable signal
(FTE)
Latch clock
[FSF]
Interrupt occur when rising edge
Data latch Flag
(FDS)
Data
(FSKTB) bit0
FSK Signal
(DTMF pin)
1
0
1
1
0
0
Hi-Z
Hi-Z
1
0
1
1
0
833us
Figure 6-12 FSK Modulator
FSK TRANSIMT CONTROL REGISTER
Bit:
7
6
5
4
3
FTE
FTM
FDS
Mnemonic: FSKTC
FTE: FSK transmit Enable. Enable=1, Disable=0
FTM: FSK signal Standard. Bellcore 202=1, V.23=0
FDS: FSK data sending status
LO0, LO1: FSK transmit level option
FSK output level
150mV
120mV
95mV
75mV
LO1
0
0
1
1
(initial=00H)
2
1
LO1
Address: C6h
0
LO0
LO0
0
1
0
1
FSK TRANSMIT DATA BUFFER
(initial=00H)
Bit:
7
6
5
4
3
2
1
0
FSKTB.7 FSKTB.6 FSKTB.5 FSKTB.4 FSKTB.3 FSKTB.2 FSKTB.1 FSKTB.0
Mnemonic: FSKTB
Address: C7h
FSKTB.0: Only This bit will be latched and send out as FSK signal
When FTE enable will set the FDS to high to enable the internal latch clock in 1200Hz. When
FDS is in high state, FSKTB bit0 will be sent out by FSK modulator at the rising edge of latch
clock. FDS could be cleared by software to inform no more data will be sent out after the last bit is
sent completely. If the FDS is cleared then FTE will become low at next rising latch clock to
disable FSK modulator and clear FDS by hardware automatically.
When FTE is set, FSK modulation flag (FSF) will be set at every rising edge of latch clock to
produce an interrupt shared with CID interrupt routine. If a CID interrupt occurs, user can check
FSF to know if this interrupt is caused by FSK modulator. The only way to stop FSK signal
immediately is to disable FTE by software.
-47-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
6.13 I/O Ports
There are six 8-bit ports named from P0 to P4 in W925E/C625. All ports can be configured as
input or output mode. Except P0, every port has pull high resistor enable/disable by PxH register.
After reset the initial state of each port is in input mode and the value of the registers from P0 to
P3 are FFh. The I/O port is described as below:
P0: I/O mode is controlled by P0IO. Only P0 output as open drain mode and without pull high
resistor.
P1: I/O mode is controlled by P1IO. Pull high is controlled by P1H. P1.0~P1.3 work as INT2,
P1.4~P1.7 work as INT3. Falling edge on P1 pins to produce INT2 and INT3 flag. P1 is
configured as INT2/INT3 by P1EF register.
P2: I/O mode is controlled by P2IO. Pull high is controlled by P2H.
P3: I/O mode is controlled by P3IO. Pull high is controlled by P3H.
P3.5
T1
Timer/counter 1 external count input
P3.4
T0
Timer/counter 0 external count input
P3.3
External interrupt 1
INT1
P3.2
External interrupt 0
INT0
P4: I/O mode is controlled by P4IO. Pull high is controlled by P4H.
Special function of P4 is described below.
P4.4
Vpos
Positive input of the comparator
P4.2
Vneg
Negative input of the comparator
P4.1
SDATA
Serial port output
P4.0
SCLK
Serial port input
6.14 Divider
A built-in 13/14-bit binary up-counter designed to generate periodic interrupt. The clock source is
from sub-oscillator. When the frequency of sub-crystal is 32768Hz, it provides the divider interrupt
in the period of 0.25/0.5 second. Bit DIVS controls the degree of divider. When DIVA is high to
enable the divided counter, when DIVA is low to reset divider and stop counting. As the divider
overflows, the divider interrupt flag DIVF is set. DIVF is clear by software or serving divider
interrupt routine.
DIVS
(CKCON1.1)
overflow
D
ck
CR
Fs
DIVA
(DIVC.0)
1
Q
DIVF
(EXIF.3)
13 14
Executing DIV Int
Clear by software
Figure 6-13 13/14-bit Divider
6.15 LCD
1792 dots: 56 Segments x 32 Common, 1/5 bias
-48-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
An internal voltage pump is enable/disable by option code. The LCD on/off is controlled by bit
LCDON (SCON1.6). If the voltage pump is enable, when LCDON is high to pump voltage and the
LCD waveform is output to LCD pins according the LCD memory, when LCDON is low to turn off
the voltage pump. The voltage of internal regulator is the base voltage of the voltage pump which
5 times of the base voltage. The output voltage of the regulator is tunable by 4 bits in regulator
voltage control register (REGVC). When REGVC is equal to 0AH, the output voltage is 1.0V. The
higher value of REGVC the lower voltage output of regulator. The adjustable voltage range is
about from 0.72V to 1.48V . Accordingly, the LCD contrast is controlled by the value of REGVC.
The variation of the voltage depends on the VDD. Following is the table of REGVC vs regulator
voltage.
Regvc
No
Loading(3V)
No
Loading(5V)
With LCD
Loading(3v)
With LCD
Loading(5v)
00
01
02
03
04
05
06
07
08
09
0ah
0bh
0ch
0dh
0eh
0fh
1.497 1.4464 1.3941 1.3426 1.2899 1.238 1.186 1.1352 1.081 1.029 0.976 0.924 0.869 0.815 0.762 0.7112
1.500 1.449 1.397 1.345 1.292 1.241 1.188 1.137 1.083 1.031 0.978 0.925 0.87 0.816 0.763 0.712
1.46 1.41
1.36
1.31
1.26
1.21 1.16 1.11
1.05 1
0.95 0.9
0.85 0.80 0.75 0.71
1.484 1.433 1.381 1.330 1.278 1.227 1.176 1.125 1.072 1.024 0.975 0.926 0.874 0.825 0.773 0.723
LCD Frequency
The alternating frequency of the LCD can be set as 16Hz, 32Hz, 64Hz and 128Hz that are
determined by 2 bits of option code. structure of the LCD alternating frequency (FLCD) is shown in
Figure 6-14.
Sub-oscillator clock
32K
Q1
Q2
16K
Q3
8K
4K
Q4
2K
00
01 M
10 u
11 x
2 bits of
option code
F
LCD
1/4
optoin code
LCDT1
Figure 6-14 LCD alternating frequency (FLCD) circuit diagram
Fw = 32.768 KHz, the LCD frequency is shown in the table below.
Table7 The relationship between the FLCD and the 2 bits option code
Option Code 00
01
10
11
FLCD
16Hz 32Hz 64Hz 128Hz
LCD RAM MAP
The LCD memory address is list as below. Each dot is controlled by the corresponding bit and the
content high to light the LCD dot and low to off the LCD dot.
OUTPUT
COM0
COM1
COM2
COM3
S55-S48
BIT7-0
2006H
200EH
2016H
201EH
S47-S40
BIT7-0
2005H
200DH
2015H
201DH
S39-S32
BIT7-0
2004H
200CH
2014H
201CH
-49-
S31-S24
BIT7-0
2003H
200BH
2013H
201BH
S23-S16
BIT7-0
2002H
200AH
2012H
201AH
S15-S08
BIT7-0
2001H
2009H
2011H
2019H
Release Date : 2002/7/2
Revision : A6
S07-S00
BIT7-0
2000H
2008H
2010H
2018H
W925E/C625
8-bit CID Microcontroller
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
2026H
202EH
2036H
203EH
2046H
204EH
2056H
205EH
2066H
206EH
2076H
207EH
2086H
208EH
2096H
209EH
20A6H
20AEH
20B6H
20BEH
20C6H
20CEH
20D6H
20DEH
20E6H
20EEH
20F6H
20FEH
2025H
202DH
2035H
203DH
2045H
204DH
2055H
205DH
2065H
206DH
2075H
207DH
2085H
208DH
2095H
209DH
20A5H
20ADH
20B5H
20BDH
20C5H
20CDH
20D5H
20DDH
20E5H
20EDH
20F5H
20FDH
2024H
202CH
2034H
203CH
2044H
204CH
2054H
205CH
2064H
206CH
2074H
207CH
2084H
208CH
2094H
209CH
20A4H
20ACH
20B4H
20BCH
20C4H
20CCH
20D4H
20DCH
20E4H
20ECH
20F4H
20FCH
2023H
202BH
2033H
203BH
2043H
204BH
2053H
205BH
2063H
206BH
2073H
207BH
2083H
208BH
2093H
209BH
20A3H
20ABH
20B3H
20BBH
20C3H
20CBH
20D3H
20DBH
20E3H
20EBH
20F3H
20FBH
2022H
202AH
2032H
203AH
2042H
204AH
2052H
205AH
2062H
206AH
2072H
207AH
2082H
208AH
2092H
209AH
20A2H
20AAH
20B2H
20BAH
20C2H
20CAH
20D2H
20DAH
20E2H
20EAH
20F2H
20FAH
2021H
2029H
2031H
2039H
2041H
2049H
2051H
2059H
2061H
2069H
2071H
2079H
2081H
2089H
2091H
2099H
20A1H
20A9H
20B1H
20B9H
20C1H
20C9H
20D1H
20D9H
20E1H
20E9H
20F1H
20F9H
LCD Power Connection
The LCD power connection of bias is shown in Figure 6-15
1/5 Bias
DH1
0.1uF
C
H
I
P
C6
DH2
VSS
C5
VLCD5
C4
C3
C2
C1
0.1uF
VLCD4
VLCD3
VLCD2
Regulator
VLCD1
C1=C2=C3=C4=C5=C6=0.1uF
-50-
Release Date : 2002/7/2
Revision : A6
2020H
2028H
2030H
2038H
2040H
2048H
2050H
2058H
2060H
2068H
2070H
2078H
2080H
2088H
2090H
2098H
20A0H
20A8H
20B0H
20B8H
20C0H
20C8H
20D0H
20D8H
20E0H
20E8H
20F0H
20F8H
W925E/C625
8-bit CID Microcontroller
Figure 6-15 1/5 Bias LCD Power Connection
LCD Waveform
The LCD waveform is B type. Figure 6-16 is an example for 1/5 bias LCD waveform.
COM0
COM1
COM2
COM3
LCD outputs
for only seg. on
COM0 & COM2
side being lit
Figure 6-16 LCD waveform for 1/5 bias
-51-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
6.16 Calling Identity Delivery (CID)
W925E/C625 provides type I and type II of CID system. Type I is on-hook calling with CID
message and type II is off-hook call on waiting. The CID function includes FSK decoder, dual
tone alert signal detector, ring detector and DTMF receiver. The FSK demodulation function can
demodulate Bell 202 and ITU-T V.23 Frequency Shift keying (FSK) with 1200 baud rate. The
Tone Alert Signal detect function can detect dual tones of Bellcore Customer Premises
Equipment(CPE) Tone Alerting Signal(CAS) and BT Idle State and Loop State Tone Alert Signal.
The line reversal for BT, ring burst for CCA or ring signal for Bellcore can be detected by ring
detector. It is compatible with Bellcore TR-NWT-000030 & ST-TSV-002476, British Telecom(BT)
SIN227, U.K. Cable Communications Association(CCA) specification. The DTMF receiver can be
programmed as DTMF decoder to decode 16 DTMF signals or tone detector to detect the signal
which frequency is in DTMF band. The tone detector can be an auxiliary detector to improve the
performance of detecting tone alerting signal(CAS), said as talk down-off, in type II system.
The FSK decoder, alert tone detector and DTMF receiver can be enable/disable individually by
the bits of FSKE, CASE and DTMFE in FSK DATA REGISTER(FSKDR). CIDE is the global
control bit to enable/disable FSK decoder, alert tone detector and DTMF receiver. However, the
ring detector is always active.
DTMFE
CIDGA
CIDGD
High Tone
PGD
<7:4>
Bandpass
INP2
INN2
+
-
PGAF
<3:0>
Anti-alias
Filter
High Tone
Detector
Filter
Input Pre-processor
Guard
Time
Timer
PHAD<3:0>
Low Tone
PGD
<3:0>
ESt
Decode
data
and Latch
Low Tone
Detector
Bandpass
Filter
GCFB2
DTMFD
DD3-DD0
DTMFPT/DTMFAT
FSKE
FDATA
FSK Demodulation Circuit
FSK Bandpass
Filter
FSK
Data Output
Interface
FSK
Demodulator
Input Pre-processor
INP1
+
INN1
-
PGAF
<7:4>
PHFL<7:4>
Anti-alias
Filter
FSK Carrier
Detector
DATE
FD7-FD0
FDR
FCD
PHFL<3:0>
GCFB1
To internal
circuit
VREF
CAP
High Tone
Bias Voltage
Generator
Dual Tone Alert Signal Detection Circuit
Bandpass
High Tone
Detector
Filter
PHAD<7:4>
CIDE,RST
Low Tone
Bandpass
Filter
Guard
Time
Circuit
Interrupt
Generator
ALGO
CASPT/CASAT
Low Tone
Detector
VADD
Clock Driver
VASS
Ring Detector
RNG
To internal
circuit
Fm
RNGDI
RNGRC
PS: The signals noted in italic and underline type are CID pins on the chip.
Figure 6-17 The CID Block Diagram
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Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
Ring Detector
The application circuit in Figure 6-18 illustrates the relationship between the RNGDI, RNGRC and
RNG signals. The combination of RNGDI and RNGRC is used to detect an increase of the
RNGDI voltage from ground to a level above the Schmitt trigger high going threshold voltage VT+.
C1=0.1uF
R1=470K
Tip/A
R3=200K
C1=0.1uF
RNGDI
R4=300K
Ring/B
R2=470K
R5=150K
RNGRC
RNG
C3=0.22uF
Allowance minimal ring voltage (peak to peak) is:
Vpp (max ring) = 2 (VT+(max) (R1 + R3 + R4) / R4 + 0.7)
Tolerance to noise between Tip and Ring and VSS is:
Vpeak (max noise) = V T+(min) (R1 + R3 + R4) / R4 + 0.7
R5 from 10K ohm to 500K ohm.
C3 from 47 nF to 0.68 uF.
Time constant is:
T = R5 C3 ln [VDD / (VDD - VT+)]
VT+(min) <= VT+ <= VT+(max)
Figure 6-18 Application Circuit of the Ring Detector
The RC time constant of the RNGRC pin is used to delayed the output pulse of the RNG flag for a
low going edge on RNGDI. This edge goes from above the VT+ voltage to the Schmitt trigger low
going threshold voltage VT-. The RC time constant must be greater than the maximum period of
the ring signal, to ensures a minimum RNG high interval and to filter the ring signal to get an
envelope output. The rising signal of RNG will set the bit RNGF(CIDFG.0) high to cause the CID
flag(CIDF) high.
The diode bridge shown in Figure 6-18 works for both single ended ring signal and balanced
ringing. The R1 and R2 are used to set the maximum loading and must be of equal value to
achieve balanced loading at both the tip and ring line. R1, R3 and R4 form a resistor divider to
supply a reduced voltage to the RNGDI input. The attenuation value is determined by the
detection of minimal ring voltage and maximum noise tolerance between tip/ring and ground.
Input Pre-Processor
The input signal is processed by Input Pre-Processor, which is comprised of two OP amps and a
bias source(VREF). The gain OP-amps are used to bias the input voltage with the VREF signal
voltage. VREF is VAD/2 typically, this pin is recommended to connect a 0.1 uF capacitor to VAS.
The gain adjustable OP amps are sued to select the input gain by connecting a feedback resistor
between GCFB and INN pins. Figure 6-19 shows the differential input configuration and Figure
6-20 shows the single-ended configuration.
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Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
VREF
0.1uF
R3
R4
C1
R1
C2
R2
+
INN
-
GCFB
R5
Differential Input Amplifier
C1 = C2
R1 = R2
R3 = (R4 R5) / (R4 + R5)
INP
Voltage Gain
Av = R5 / R1
Input Impedance
2
2
Zin = 2 R1 + (1 / wC)
Figure 6-19 Differential Input Gain Control Circuit
VREF
0.1uF
C
R1
22n
R2
INP
+
INN
-
GCFB
Voltage Gain
Av = R2 / R1
Figure 6-20 Single-Ended Input Gain Control Circuit
CAS/DTAS Detection
In off-hook services (type II), the detection of CAS/DTAS will affect the quality of the call waiting
service. When the CAS/DTAS is sent from far end, sometimes the near end user maybe still
talking. The CPE must be able to detect the CAS/DTAS successfully in the presence of near end
speech. To detect CAS/DTAS from telephone hybrid receiver pair improves the detection.
However in BT’ s on-hook CID system the CAS/DTAS detection is from Tip/Ring pair.
The dual tone alert signal is separated into high and low tones and detected by a high/low tone
detector. When the alert tone is recognized by the detector, the bit ALGO will go high and the
rising signal will set the bit ALGOF in CIDFG to produce the CID flag(CIDF). Figure 6-21 shows
the guard time waveform of detecting alert tone. The total recognition time is tREC =tDP+tGP, where
tDP is the tone present detect time and tGP is the tone present guard time. The total absent guard
time is tABS=tDA+tGA where tDA is the tone absent detect time and tGA is the tone absent guard time.
The tone present/absent guard time is determined by guard-time timer which the input clock
period is 0.858mS. When the alert tone is detected the internal signal ALGR will be set and the
rising edge of ALGR resets the guard-time timer and the timer starts up counting from 00H. As
the content of the timer is the same as the register CASPT, the timer stops counting and the bit
ALGO will be set and the rising edge of ALGO triggers the flag ALGOF to become high. The
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Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
counting of tone absent time is similar to the counting of tone present time but the falling edge of
ALGR/ ALGO replaces the rising edge and the CASAT replaces the CASPT. The bit ALGO is
controlled by hardware only. The flag ALGOF is set by rising edge of ALGO and cleared by
software.
Vin
Dual Alert Tone Signal
t DA
t DP
t DA
t DP
ALGR*
t GA
t GP
ALGO
+
ALGOF
t REC
1
t ABS
3
2
3
1
1: Guard time timer is reset and starts to up count from 00H.
2: Guard time timer is reset and starts to up count from 00H.
3: The content of the guard-time timer reaches the content of ASPT/ASAT.
*ALGR is an internal signal in the uC.
+ Clear by software.
Figure 6-21 Guard Time Waveform of Alert Tone Signal Detection
DTMF Decoder
The DTMF decoder shares the same input pre-processor with FSK decoder. The dual tone is
separated into low group and high group by two SCFs (switched capacitor filter. The method of
DTMF detection is the same as alert tone detection. The present/absent guard time is adjusted by
registers DTMFPT/DTMFAT. As the DTMF signal is recognized and decoded, the bit DTMFD will
be set and the decoded DTMF data is stored in bit0 to bit3 of register DTMFDR. The rising edge
of DTMFD produces the flag DTMFDF. The bit DTMFD is controlled by hardware only. The flag
DTMFDF is set by rising edge of DTMFD and cleared by software.
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Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
Vin (Tip/ring)
TONE #n
t DA
t DP
ESt *
t GP
t GA
t REC
t ABS
DTMFD
+
DTMFDF
DTMFDR
Tone #n-1
Tone #n
1
3
2
3
1: Guard time timer is reset and starts to up count from 00H.
2: Guard time timer is reset and starts to up count from 00H.
3: The content of the up counting timer reaches the register DTMFPT/DTMFAT.
* ESt is an internal signal in the circuit.
+ Clear by software.
Figure 6-22 The Waveform of DTMF Detection
Tone Detector
In off-hook state, said type II system, detecting tone alert signal(CAS) is easily interfered by
human’ s voice or other noise in voice band. Sometimes the interference makes falsely
recognizing a noise as a CAS(talk-off), or lost detecting a real CAS(talk-down). The DTMF can be
programmed as a tone detector by setting bit 4 of DTMFR2. The frequency band of the tone
detector is DTMF frequency from 697Hz to 1633Hz. Once the tone detector gets signals in the
band, the bit of DTMFH or DTMFL in register DTMFDR will become high immediately. User can
poll these 2 bits to check if the tone exists on the tip/ring. The input gain of tone detector is the
same as DTMF receiver.
FSK Decoder
The FSK carrier detector provides an indication of the present of a signal within the FSK
frequency band. If the output amplitude of the FSK band-pass filter is sufficient to be detected
continuously for 8 mS, the FSK carrier detected bit FCD will go high and it will be released if the
FSK band-pass filter output amplitude is not able to be detected for greater than 8 mS. The 8 mS
is the hysteresis of the FSK carrier detector. Figure 6-23 shows the timing of FSK carrier
detection.
Tip/Ring
t FSKE
FSKE
Analog FSK Signal
Analog FSK Signal
Note
t CA
FCD
t CP
t CP
t CA
Figure 6-23 FSK Detection Enable and FSK Carrier Present and Absent Timing
The FSK demodulation function can demodulate Bell 202 and ITU-T V.23 Frequency Shift keying
(FSK) with 1200 baud rate. When the decoder receives the FSK serial data, the serial data will be
demodulated into bit FDATA with 1200 baud rate in the mean time the synchronous clock signal
is output to the bit FCLK. As the decoder receives one byte, the internal serial-to-parallel circuit
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Revision : A6
W925E/C625
8-bit CID Microcontroller
sets the bit FDR and converts the 8-bit serial data into the byte register FSKDR. The rising edge
of bit FDR will set the flag FDRF to produce CID interrupt but FDRF is cleared by software. User
can get the FSK data by reading register FSKDR or sampling the bit FDATA. The timing of FSK
demodulation is shown in Figure 6-24.
stop
1st byte data
Tip/Ring
1*
1
0
2nd byte data
start
start
b0 b1 b2 b3 b4 b5 b6 b7 1*
1
0
stop
start
b0 b1 b2 b3 b4 b5 b6 b7 1
0
b0
t IDD
1st byte data
stop
start
FDATA
2nd byte data
start
b0 b1 b2 b3 b4 b5 b6 b7
stop
start
b0 b1 b2 b3 b4 b5 b6 b7
1/fDCLK0
FCLK
t CRD
t RH
FDR
+
FDRF
FSKDR
1st byte data
2nd byte data
* Mark bit or redundant stop bit(s), will be omitted.
+ Clear by software.
Figure 6-24 Serial Data Interface Timing of FSK Demodulation
CID Input Gain Control
The CID input gain and input hysteresis are controllable by internal CID gain control registers.
CIDGD and CIDGA registers determine the 6 internal CID gain control registers. CID gain control
data register (CIDGD) presents the data bus. The lower 3 bits of CID gain control address register
(CIDGA) presents the address. The rising edge of CIDGA.4 will latch the CIDGD in the
corresponding internal CID gain control register. The 6 internal CID gain control registers are
addressed as following table. Setting the 6 registers as the suggestion value guarantees the CID
spec.
Address
Internal CID Gain Control Register
Suggestion
(CIDGA.2-0)
Value
000
DTMFR1: DTMF register1
0000 0001B
001
DTMFR2: DTMF register2
011X 0001Bè
002
PGAF: Programmable gain control alert tone and FSK
99H
003
PGAD: Programmable gain control DTMF
A7H
004
PHAD: Programmable hysteresis alert tone and DTMF
35H
005
PHFL: Programmable hysteresis FSK and low pass filter
33H
è
X=0 DTMF receiver works a DTMF decoder, X=1 DTMF receiver works as a tone detector.
The signals to set internal CID gain control registers is shown in Figure 6-25
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Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
CIDGA
CIDGA<2:0>
CIDGD
CIDGD
CIDGA.3
Rising latch
Figure 6-25 Internal CID Gain Control Register Setting Waveform
DTMFR1
DTMFR1[7:4] are reserved bits and must be 0000b.
Bit3~Bit0
Acceptable error percentage to sample 4 period of Row freq.
0000
0.6% (default)
0001
2.5%
001X
3.5%
01XX
Reserved
1XXX
Reserved
DTMFR2
Bit3~Bit0
Acceptable error percentage to sample 4 period of Col freq.
0000
0.5% (default)
0001
1.5%
001X
2.5%
01XX
Reserved
1XXX
Reserved
The acceptable error percentage may have small variation by different test environments.
DTMFR2.4=0
DTMFR2.4=1
DTMFR2.5=0
DTMF receiver works as a DTMF receiver
DTMF receiver works as a tone detector
DTMF PT counter is up counter type, change of detected frequency
does not effect counter
DTMFR2.5=1 DTMF PT counter is up counter type, change of detected frequency
resets DTMF PT counter
DTMFR2.6=0 DTMF AT counter is up-down counter type, up counting when no
DTMF detected, down counting if DTMF detected again.
DTMFR2.6=1 DTMF AT counter is up counter type, up counting when no DTMF
detected, pause counting if DTMF detected again.
DTMFR2.7: reserved
There are 4 programmable gain arrays, shown in Figure 6-17, are determined by Low/High
nibbles of PGxx. The following table lists the input gain corresponding to the value of L/H nibble
of PGxx.
X
20 log((40+15*X)/(230-(40+15*X))) dB
X
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20 log((40+15*X)/(230-(40+15*X))) dB
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
0
1
2
3
4
5
-13.53
-10.05
-7.18
-4.64
-2.28
0.00
6
2.28
7
4.64
8
7.18
9
10.05
10
13.53
X is the value of L/H nibble of PGxx
There are 4 programmable hysteresis input buffer, shown in Figure 6-17, are determined by Low/
High nibbles of PHxx. The hysteresis control formulas are list below.
Alert tone hysteresis
HAT=13mv + 3mv*X
X=PHAD<7:4>
DTMF hysteresis
HDTMF=6mv + 3mv*X
X=PHAD<3:0>
FSK hysteresis
HFSK=13mv + 3mv*X
X=PHFL<7:4>
FSK detector hysteresis
HFSKD=13mv + 3mv*X
X=PHFL<3:0>
Application Circuit
The analog interface circuit of W925E/C625 shown in Figure 6-26 is a typical CPE system. The
gain control op-amp is set to unit gain to allow the electrical characteristics to be met in this
application circuit.
22nF
430K
34K
Tip/A
INP2
INN2
22nF
430K
34K
464K
Ring/B
VREF
0.1uF
0.1uF
CAP
470K
RNGDI
150K
200K
0.1uF
470K
100K
464K
464K
Microphone
Tip
Ring
Tx+
Tx-
GCFB2
60K4
53K6
60K4
RNGRC
0.47u
60K4
INP1
22nF
Speech
Network
INN1
Rx+
Rx-
464K
Speaker
464K
22nF
GCFB1
Resistor must have 1% tolerance
Resistor must have 5% tolerance
Figure 6-26 Application Circuit of CID
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Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
Application Environment
There are three major timing differences for CID sequences, Bellcore, BT and CCA. Figure 6-27
is the timing diagram for Bellcore on-hook data transmission and Figure 6-28 is the timing
diagram for the Bellcore off-hook data transmission. Figure 6-29 is the timing diagram for the BT
caller display service on-hook data transmission and Figure 6-30 is the timing diagram for the BT
caller display service off-hook data transmission. Figure 6-31 is the timing diagram for the CCA
caller display service for on-hook data transmission. The CID flag (CIDF) must be cleared by
software when each time the CID interrupt routine is serviced. The CID global enable signal
(CIDE) must be set high.
Tip/Ring
1st Ring
A
CIDF
B
Ch. seizure
C
Mark
D
Message
E
...
...
...
...
2nd Ring
F
RNG
FSKE
FCD
FDR
FCLK
FDATA
...101010...
Data
A = 2 sec typical
B = 250-500mS
C = 250mS
D = 150mS
E = depend on data length
MAX C+D+E = 2.9 TO 3.7 sec
F >= 200mS
Figure 6-27 Input and Output Timing of Bellcore On-hook Data Transmission
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Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
CPE goes off-hook
CPE unmutes handset and
enable keypad
CPE mutes handset & disables keypad
CPE sends
Tip/Ring
CAS
A
ACK
B
C
Mark
D
E
Message
F
G
ASE
...
CIDF
t REC
t ABS
ALGO
FSKE
FCD
FDR
...
FCLK
FDATA
Data
A = 75 - 85mS
B = 0 - 100mS
C = 55 - 65mS
D = 0 - 500mS
E = 58 - 75mS
F = depends on data length
G <= 50mS
Figure 6-28 Input and Output Timing of Bellcore Off-hook Data Transmission
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Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
Line Reversal
Alert Signal
A/B Wires
A
B
Ch. Seizure
Mark
Message
D
E
F
C
Ring
G
RNGON
ASE
...
CIDF
ALGO
...
t ABS
t REC
50 - 150 ms
TE DC load
TE AC load
15
< 120uA
1 ms
< 0.5 mA (optiona)
Current wetting pulse (Refer to SIN227)
20
5 ms
Note 1
Zss (Refer to SIN227)
Note 2
FSKE
Note 3
FCDN
FDRN
...
...
DCLK
DATA
...101010...
Data
A >= 100mS
B = 88 - 100mS
C >= 45mS (up to 5Sec)
D = 80 - 262mS
E = 45 - 75mS
F <= 2.5S (500mS typical)
G >= 200mS
Figure 6-29 Input and Output Timing of BT Idle State (On-hook) Data Transmission
Note:
1. SIN227 specifies that the AC and DC loads should be applied at 20 ± 5mS after the end of the dual tone alert
signal.
2. SIN227 specifies that the AC and DC loads should be removed between 50 – 150mS after the end of the FSK
signal.
3. The FSKE bit should be set low to disable the FSK decoder when FSK is not expected. The tone alerting signal
speech and the DTMF tones are in the same frequency band as the FSK signal.
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Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
CPE goes off-hook
Start Point
CPE sends
CAS
Tip/Ring
A
Note 1
CPE unmutes handset and
enable keypad
CPE mutes handset & disables keypad
B
ACK
C
D
Mark
E
F
Message
G
H
Note 3
ASE
...
CIDF
t REC
t ABS
ALGO
FSKE
Note 2
Note 5
Note 4
FCD
FDR
...
FCLK
FDATA
Data
A = 40 - 50mS
B = 80 - 85mS
C <= 100mS
D = 65 - 75mS
E = 5 - 100mS
F = 40 - 75mS
G = depends on data length
H <= 100mS
Figure 6-30 Input and Output Timing of BT Loop State (Off-hook) Data Transmission
Note:
1. In a CPE where AC power is not available, the designer may choose to switch over to line power when the CPE
goes off-hook and use battery power while on-hook.
2. The FSKE bit may be set low to prevent the alert tone, speech or other FSK in-band noise decoded by FSK
demodulator and give false data when the dual tone alert signal is expected. If the FSKE pin can not controlled by
micro-controller, the FSKE bit must always placed in high state and the micro controller must give up the FSK
decoded data when the FSK signal is not expected.
3. The exchange will have already disabled the speech path to the distant customer in both transmission directions.
4. The FSKE should be set high as soon as the CPE has finished sending the acknowledge signal ACK.
5. The FSKE may be set low after the last byte (check sum) has been decoded or FCD has become inactive.
6. In an unsuccessful attempts where the exchange does not send the FSK signal, the CPE should disable FSKE,
un-mute the handset and enable the keypad after this interval.
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Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
Line Reversal
A/B Wires
First Ring Cycle
Ring Burst
A
Ch. Seizure
B
C
Mark
D
Message
E
F
RNG
CIDE
Note 4
...
CIDF
...
50 - 150 ms
TE DC load
250 - 400 ms
TE AC load
FSKE
Note 2
Note 3
Note 1
FCD
FDR
...
...
FCLK
FDATA
...101010...
Data
A = 200 - 450mS
B >= 500mS
C = 80 - 262mS
D = 45 - 262mS
E <= 2.5sec (500ms typical)
F >= 200mS
Figure 6-31 Input and Output Timing of CCA Caller Display Service Data Transmission
Notes:
1. The CPE designer may choose to set FSKE always high while the CPE is on-hook and the FSK signal is
expected.
2. TW/P & E/312 specifies that the AC and DC loads should be applied between 250 - 400 mS after the end of the
ring burst.
3. TW/P & E/312 specifies that the AC and DC loads should be removed between 50 - 150 ms after the end of the
FSK signal.
4. The CID may not be enable up at the first ring cycle after the FSK data had been processed.
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Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
7
7.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
(Voltage referenced to VSS pin)
1
2
3
4
Parameter
Supply Voltage with respect to VSS
Voltage on any pin other than supplies (note 1)
Current at any pin other than supplies
Storage Temperature
Symbol
VDD
Tst
Rating
-0.3 to 6
-0.7 to VDD + 0.7
0 to 10
-65 to 150
Units
V
V
MA
¢J
Note:
*. Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the lift and reliability
of the device.
1. VDD + 0.7 should not excess maximum rating of supply voltage.
7.2
Recommended Operating Conditions
Characteristics
Power Supplies (Analog)
Power Supplies (Digital)
Main Clock Frequency
Sub Clock Frequency
Tolerance on Clock Frequency
Symbol
VAD
VDD
fOSC
fSUB
Rating
3.0 to 6.0
2.2 to 6.0
3.579545
32768
-0.1 to +0.1
Unit
V
V
MHz
Hz
%
Operation Temperature
Top
0 to 75
¢J
7.3
∆fC
DC Electrical Characteristics
Parameter
Symbol
Operating Current
IOP1
IOP2
IOP3
IOP4
IOP5
IOP6
I/O Ports Input High
Voltage
I/O Ports Input Low
Voltage
I/O Ports Output High
Voltage
Condition
FSK On, dual
clock, normal
run
FSK Off, dual
clock, normal
run
FSK off, slow
run, main osc
stopped
Idle mode,
dual clock
Idle mode,
main osc
stopped
Power down
mode
Min
Typ*
Max
Unit Note
2.8
mA
1.3
mA
50
uA
500
uA
50
uA
1
uA
VIH
0.7VDD
VDD
V
VIL
VSS
0.3VDD
V
-
V
VOH
IOH = 2.0mA
-65-
2.4
-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
I/O Ports Output Low
Voltage
BUZ Pin Output High
Voltage
BUZ Pin Output High
Voltage
LCD ON Current
DTMF Output DC
Level
VOL
IOL = 2.0mA
-
-
0.4
V
VBOH
IOH = 3.5mA
2.4
-
-
V
VBOL
IOL = 3.5mA
0.4
-
-
V
ILCD
All Seg. On
RL = 5KΩ,
VDD = 2.5-3.8
RL = 5KΩ,
VDD = 2.5-3.8
Low group,
RL = 5KΩ
Col/Row
RL = 5KΩ,
VDD = 2.5-3.8
RL = 5KΩ,
VDD = 2.5-3.8
20
35
uA
1.1
-
2.8
V
-
-30
-23
dB
130
150
170
1
2
3
mV
rms
dB
1.1
-
2.8
V
-
-
-30
dB
RL = 5KΩ
75
150
170
100
360
1000
mV
rms
KΩ
0.48VAD
-
0.68VAD
V
0.28VAD
-
0.48VAD
V
VTDC
DTMF Distortion
DTHD
DTMF Output Voltage
VTO
Pre-emphasis
FSK Output DC
Level
VFDC
FSK Distortion
FTHD
FSK Output Voltage
VFD
Port Pull High Resistor
Schmitt Input High
Threshold
Schmitt Input High
Threshold
RPH
Schmitt Hysteresis
VHYS
RNGRC Low Sink
Current
IRNGL
RNGRC
Input Current
IIN
INPx, INNx,
RNGDI
VT+
VT-
RNGDI,
RNGRC
RNGDI,
RNGRC
RNGDI,
RNGRC
0.2
V
2.5
Reference Output
VREF
VREF
voltage
Reference Output
RREF
VREF
Resistance
*. Typical figure are at VDD = 3V and temperature = 25 ¢ J.
-66-
mA
-
-
1
µA
0.5VAD –
4%
-
0.5VAD +
4%
V
-
-
2
KΩ
No load
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
Electrical Characteristics - Gain Control OP-Amplifier
(Electrical characteristics supersede the recommended operating conditions unless otherwise stated.)
Parameter
Input Leakage Current
Typ‡ Max Units
1
µA
Symbol Min
IIN
Input Resistance
RIN
10
Input Offset Voltage
VOS
Power Supply Rejection Ratio
PSRR 40
Maximum Capacitive Load (GCFBx) CL
Maximum Resistive Load (GCFBx) RL
50
Note: "‡" Typical figure are at VDD = 5V and temperature = 25
25
100
MΩ
mV
dB
pF
kΩ
Test Conditions
VSS ≤ VIN ≤ VDD
1 kHz 0.1 Vpp ripple on VDD
¢ J are design aids only, not guaranteed and not subject to
production testing.
7.4
AC Electrical Characteristics
(AC timing characteristics supersede the recommended operating conditions unless otherwise stated.)
Dual Tone Alert Signal Detection Interface
Parameter
Symbol Min
Low Tone Frequency
fL
High Tone Frequency
fH
Frequency Deviation accept
1.1
Frequency Deviation reject
3.5
Maximum Input Signal Level
Input Sensitivity per tone
Reject Signal Level per tone
b
Positive and negative twist accept
Noise Tolerance
-40
Typ
2130
2750
Max
0.22
-38
-48
7
SNRTONE 20
Units
Hz
Hz
%
%
a
dBm
dBm
dBm
dB
dB
Notes
3
4
5
5
1, 2
Notes:
a. dBm = decibels with a reference power of 1 mW into 600 ohms, 0 dBm = 0.7746 Vrms.
b. Twist = 20 log (fH amplitude / fL amplitude).
1. Both tones have the same amplitude. Both tones are at the nominal frequencies.
2. Band limited random noise 300 - 3400 Hz. Present only when tone is present.
3. Range within which tones are accepted.
4. Ranges outside of which tones are rejected.
5. These characteristics are at VDD = 5V and temperature = 25 ¢ J.
Dual Tone Alert Signal Detection
Parameter
Condition Symbol
Min
Alert Signal present detect time
0.5
tDP
ALGR
Alert Signal absent detect time
0.1
tDA
"‡" Typical figure are at VDD = 5V and temperature = 25 ¢ J are design aids
Typ‡
Max
10
8
Units Notes
MS
MS
only, not guaranteed and not subject to
production testing.
-67-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
FSK Detection Interface
Parameter
Input Frequency Detection
Bell 202 Mark (logic 1)
Bell 202 Space (logic 0)
ITU-T V.23 Mark (logic 1)
ITU-T V.23 Space (logic 0)
Maximum Input Signal Level
Input Sensitivity
Transmission Rate
Input Noise Tolerance
Units Notes
Symbol
Min
Typ
Max
fMark
fSpace
fMark
fSpace
1188
2178
1280.5
2068.5
1200
2200
1300
2100
1212
2222
1319.5
2131.5
-5.78
SNRTONE
-43
1188
20
1200
+/- 1 %
+/- 1 %
+/- 1.5 %
+/- 1.5 %
Hz
dBm
dBm 1, 3
baud
dB
1, 2
1212
Notes:
1. Both mark and space have the same amplitude. Both mark and space are at the nominal frequencies.
2. Band limited random noise 300 - 3400 Hz. Present only when FSK signal is present.
3. These characteristics are at VDD = 5V and temperature = 25 ¢ J.
FSK Detection
Parameter
FSK detection enable time
Input FSK to FCD high delay
Input FSK to FCD low delay
Data Ready ACK Time
Rate
Input FSK to DATA delay
Frequency
High Time
Low Time
DCLK to FDR delay
Condition
FSKE
FCD
FDR
DATA
DCLK
DCLK, FDR
Symbol
tFSK
tCP
tCA
tDR
tIDD
fDCLK
tCH
tCL
tCRD
Min
8
415
1188
1201.6
415
415
415
Typ‡
Max
25
25
416
1200
1
1202.8
416
416
416
417
1212
5
1204
417
417
417
Units
MS
MS
MS
US
BpS
MS
Hz
US
US
US
Notes
2
1
2
2
2
2
Note :
1. FSK input data rate at 1200 +/- 12 baud.
2. OSCI frequency at 3.579545 MHz +/- 0.1%.
"‡" Typical figure are at VDD = 5V and temperature = 25 ¢ J are design aids only, not guaranteed and not subject to
production testing.
DTMF Decoder
Parameter
Input Sensitivity per tone
Positive and negative twist accept
Frequency Deviation accept
Frequency Deviation reject
3rd Tone Tolerance
Noise Tolerance
Dial tone Tolerance
Symbol Min
-29
7
1.5
3.5
Typ
Max
1
-16
-12
22
Units
dBm
dB
%
%
dB
dB
dB
Notes
1,2
1,2
1,2
1,2
1,2,3
1,2,3
1,2,4
Note :
1. signal consists of all DTMF tones.
2. Tone duration is 40mS at least, tone pause duration is 40mS at least.
3. Referenced to the lowest level frequency component in DTMF signal.
4. Referenced to the minimum valid accept level.
-68-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
DTMF Detection Interface
Parameter
DTMF present detect time
DTMF absent detect time
DTMF Detected Duration
DTMF Signal Ignore Time
DTMF Pause Accept Time
"‡" Typical figure are at VDD = 5V
Condition
Est
DTMFD=1
DTMFD=0
DTMFD=1
Symbol
tFP
tFA
tDD
tDI
tDPA
Min
0.5
0.1
Typ‡
Max
8
8
40
20
20
Units Notes
MS
MS
MS
MS
MS
and temperature = 25 ¢ J are design aids only, not guaranteed and not subject to
production testing.
-69-
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
8
PACKAGE
160L QFP (28X28 mm footprint 3.2mm)
H
D
D
160
121
1
120
E
H
E
81
40
41
80
b
e
c
A
2
A
See Detail F
A
L
control dimensions are in mm
Symbol
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
y
θ
Dimension in inch
Min
Nom
Min
Nom
Max
3.68
0.145
0.004
0.10
0.122
0.127
0.132
3.10
3.23
3.35
0.008
0.012
0.016
0.20
0.30
0.40
0.004
0.006
0.010
0.10
0.15
0.25
1.097
1.102
1.107
27.87
28.00
28.13
28.13
1.097
1.102
1.107
27.87
28.00
0.022
0.026
0.030
0.55
0.65
0.75
1.217
1.228
1.240
30.90
31.20
31.50
1.217
1.228
1.240
30.90
31.20
31.50
0.025
0.031
0.037
0.65
0.80
0.95
0.055
0.063
0.071
1.40
1.60
1.80
0.004
0
10
-70-
0.10
0
1
Detail F
Dimension in mm
Max
θ
L
1
y
Seating Plane
10
Release Date : 2002/7/2
Revision : A6
W925E/C625
8-bit CID Microcontroller
9
VERSION STATEMENT
Version
A6
Modification
1. Add initial state of registers
2. Modify description of WDCON.0
3. Modify Fig6-22
-71-
Release Date : 2002/7/2
Revision : A6