WB1330
Dual Serial Input PLL with 2.5-GHz and 600-MHz Prescalers
Features
Applications
• Operating voltage 2.7V to 5.5V
• PLL1 operating frequency:
— 2.5 GHz with prescaler ratios of 32/33 and 64/65
• PLL2 operating frequency:
— 600 MHz with prescaler ratios of 8/9 and 16/17
• Lock detect feature
• Power-down mode ICC < 1 µA typical at 3.0V
• 20-pin TSSOP (Thin Shrink Small Outline Package)
The Cypress WB1330 is a dual serial input PLL frequency
synthesizer designed to combine the RF and IF mixer frequency sections of wireless communications systems. One 2.5GHz and one 600-MHz prescaler, each with pulse swallow capability are included. The device operates from 2.7V and dissipates only 30 mW. (See Figure 1 for an example application
diagram of the WB1330.)
WB1330 Dual Hi-Lo PLL Block Diagram
GND (4)
FIN1 (5)
Prescaler
32/33 or
64/65
FIN1# (6)
GND (7)
Binary 7-Bit
Swallow Counter
Binary 11-Bit
Programmable Counter
19-Bit
Latch
VCC1 (1)
VCC2 (20)
VP1 (2)
fp1
Phase
Detector
Charge
Pump
DOPLL1 (3)
Pwr-dwn
PLL1
OSC_IN (8)
15-Bit
Reference Counter
fr fp
Monitor
Output
Selector
fr1
20-Bit Latch
Latch
Selector
FO /LD (10)
20-Bit Latch
LE (13)
DATA (12)
15-Bit
Reference Counter
Cntrl 22-Bit
Shift
Reg.
CLOCK (11)
FIN2 (16)
Prescaler
8/9 or
16/17
FIN2# (15)
19-Bit
Latch
Binary 4-Bit
Swallow Counter
GND (14)
fr2
Power
Control
Pwr-dwn
PLL2
Binary 11-Bit
Programmable Counter
Phase
Detector
Charge
Pump
GND (17)
VP2 (19)
fp2
GND (9)
DOPLL2 (18)
Pin Configuration
VCC 1
1
20
VCC2
VP1
2
19
VP2
DOPLL1
3
18
DOPLL2
GND
4
17
GND
FIN 1
5
16
FIN 2
FIN1#
6
15
FIN 2#
GND
7
14
GND
OSC_IN
8
13
LE
GND
9
12
DATA
FO/LD
10
11
CLOCK
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134 •
408-943-2600
August 11, 2000, rev. *B
WB1330
VP RF
VCC 2.7–5.5V
VP IF
10 µF
10 µF
10 µF
0.1 µF
(1)
(20)
VCC1
0.1 µF
100 pF
100 pF
(2)
100 pF
2400
MHz
VCO
(3)
33pF
0.1 µF
(18)
0.1 µF
10 kΩ
47 nH
DOPLL2
8.8 kΩ
0.01 µF
10 kΩ
0.001 µF (4)
(17) 0.01 µF
GND
0.15 µF
GND
FMMV2105CT-ND
18Ω
18Ω
18Ω
(16) 1000 pF
1000 pF (5)
FIN1
51Ω
(6)
RF LO
18Ω
(15)
FIN1#
IF LO
FIN2#
100 pF
100 pF
(7)
(14)
GND
1000 pF
18Ω
FIN 2
51Ω
18Ω
GND
(8)
(13)
OSC_IN
2 kΩ
LE
3 kΩ
51Ω
(9)
(12)
GND
2 kΩ
DATA
3 kΩ
(10)
(11)
FO/LD
2 kΩ
CLOCK
3 kΩ
Figure 1. Application Diagram Example - WB1330 2.5-GHz/600-MHz Hi/Lo Dual PLL
2
33 pF
150Ω
10 kΩ
12.5 kΩ
100 pF
DOPLL1
68 pF
100 pF
Vp2
100 pF
22 kΩ
0.1 µF
75Ω
(19)
VP1
0.1 µF
100 pF
VCC 2
BFS17CT
0.1 µF
WB1330
Pin Definitions
Pin
No.
Pin
Type
VCC1
1
P
Power Supply Connection for PLL1 and PLL2: When power is removed from both
the VCC1 and VCC2 pins, all latched data is lost.
VP1
2
P
PLL1 Charge Pump Rail Voltage: This voltage accommodates VCO circuits with
tuning voltages higher than the V CC of PLL1.
DOPLL1
3
O
PLL1 Charge Pump Output: The phase detector gain is IP/2π. Sense polarity can be
reversed by setting the FC bit in software (via the Shift Register).
GND
4
G
Analog and Digital Ground Connection: This pin must be grounded.
FIN1
5
I
Input to PLL1 Prescaler: Maximum frequency 2.5 GHz.
FIN1#
6
I
Complementary Input to PLL1 Prescaler: A bypass capacitor should be placed as
close as possible to this pin and must be connected directly to the ground plane.
GND
7
G
Analog and Digital Ground Connection: This pin must be grounded.
Pin Name
Pin Description
OSC_IN
8
I
Oscillator Input: This input has a VCC/2 threshold and CMOS logic level sensitivity.
GND
9
G
Reference Ground Connection: This pin must be grounded.
FO/LD
10
O
Lock Detect Pin of PLL1 Section: This output is HIGH when the loop is locked. It is
multiplexed to the output of the programmable counters or reference dividers in the
test program mode. (Refer to Table 3 for configuration.)
CLOCK
11
I
Data Clock Input: One bit of data is loaded into the Shift Register on the rising edge
of this signal.
DATA
12
I
Serial Data Input
LE
13
I
Load Enable: On the rising edge of this signal, the data stored in the Shift Register
is latched into the reference counter and configuration controls, PLL1 or PLL2 depending on the state of the control bits.
GND
14
G
Analog and Digital Ground Connection: This pin must be grounded.
FIN2#
15
I
Complementary Input to PLL2 Prescaler: A bypass capacitor should be placed as
close as possible to this pin and must be connected directly to the ground plane.
FIN2
16
I
Input to PLL2 Prescaler: Maximum frequency 600 MHz.
GND
17
G
Analog and Digital Ground Connections: This pin must be grounded.
DOPLL2
18
O
PLL2 Charge Pump Output: The phase detector gain is IP/2π. Sense polarity can be
reversed by setting the FC bit in software (via the Shift Register).
VP2
19
P
PLL2 Charge Pump Rail Voltage: This voltage accommodates VCO circuits with
tuning voltages higher than the V CC of PLL2.
VCC2
20
P
Power Supply Connections for PLL1 and PLL2: When power is removed from both
the VCC1 and VCC2 pins, all latched data is lost.
3
WB1330
only. Operation of the device at these or any other conditions
above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability.
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating
Parameter
Description
VCC or VP
Power Supply Voltage
VOUT
Output Voltage
Rating
Unit
–0.5 to +6.5
V
–0.5 to V CC+0.5
V
IOUT
Output Current
±15
mA
TL
Lead Temperature
+260
°C
TSTG
Storage Temperature
–55 to +150
°C
Handling Precautions
Always turn off power before adding or removing devices from
system.
Devices should be transported and stored in antistatic containers.
Protect leads with a conductive sheet when handling or transporting PC boards with devices.
These devices are static sensitive. Ensure that equipment and
personnel contacting the devices are properly grounded.
If devices are removed from the moisture protective bags for
more than 36 hours, they should be baked at 85°C in a moisture free environment for 24 hours prior to assembly in less
than 24 hours.
Cover workbenches with grounded conductive mats.
Recommended Operating Conditions
Parameter
Description
VCC1,
VCC2
Power Supply Voltage
VP
Charge Pump Voltage
TA
Operating Temperature
Test Condition
Ambient air at 0 CFM flow
4
Rating
Unit
2.7 to 5.5
V
VCC to +5.5
V
–40 to +85
°C
WB1330
Electrical Characteristics: VCC = VP = 2.7V to 5.5V, TA = –40°C to +85°C, Unless otherwise specified
Parameter
Description
Test Condition
Pin
Min.
Typ.
Max.
Unit
ICC
Power Supply Current
PLL1 + PLL2
VCC1 = VCC2 = 3.0V
VCC1,
VCC2
11
IPD
Power-down Current
Power-down, VCC = 3.0V
VCC1,
VCC2
1
FIN1
Operating Frequency
PLL1
FIN1
100
2500
MHz
PLL2
FIN2
45
600
MHz
2
45
MHz
FIN2
FOSC
Oscillator Input Frequency
Fφ
Maximum Phase Detector
Frequency
PFIN1,
PFIN2
Input Sensitivity
OSC_IN
25
10
FIN1[1]
VCC = 2.7V
VCC = 2.7V to 5.5V
MHz
4
dBm
–10
4
dBm
FIN1,
FIN2[2]
–15
4
dBm
OSC_IN
0.5
DATA,
CLOCK,
LE
VCC * 0.8
VOSC
Oscillator Input Sensitivity VCC = 3.0V
IIH, IIL
Oscillator Input Current
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IIH
High Level Input Current
–10
IIL
Low Level Input Current
–10
VOH
High level Output Voltage
VOL
Low Level Output Voltage
IDOH(SO)
IDO High, Source Current
VP–P
-100
VCC = 3.0V
VCC = 3.0V, VI = 1 mA
FO/LD
100
DOPLL1
DOPLL2
µA
V
VCC * 0.3
V
0.5
10
µA
0.5
10
µA
2.2
V
0.4
VCC = VP = 3.0V,
DO = VP/2
µA
–15
VCC = 5.5V
PFIN1,
PFIN2
mA
V
–3.8
mA
IDOL(SO)
IDO Low, Source Current
–1
mA
IDOH(SI)
IDO High, Sink Current
3.8
mA
IDOL(SI)
IDO Low, Sink Current
1
mA
∆IDO
IDO Charge Pump Sink
and Source Mismatch
VCC = VP = 3.0V,
[IIDO(SI)I – IIDO(SO)I]/
[1/2*{IID O(SI)]I+IID O(SO)I}]*100%
3
IDO vs T
Charge Pump Current
Variation vs Temperature
–40°C<T<85°C VDO = VP/2[3]
5
%
IOFF
Charge Pump High-ImVCC = VP = 3.0V,
pedance Leakage Current
±2.5
nA
Notes:
1. 2.0 GHz < FIN < 2.5 GHz.
2. FIN < 2.0 GHz.
3. IDOvs T; Charge pump current variation vs. temperature.
[IIDO(SI)@T I - IIDO(SI)@25° CI]/IID O(SI)@25°CI * 100% and
[IIDO(SO)@TI - IIDO(SO)@25°CI]/IID O(SO)@25°CI *100%.
5
15
%
WB1330
Timing Waveforms
Key:
FC Bit HIGH
FC Bit LOW
Increasing
Voltage
(Refer to Table 2 for meaning of FC bit.)
Increasing Frequency
VCO Characteristics
Phase Comparator Sense
Phase Detector Output Waveform
FR
FP
tw
tw
LD
DO Charge Pump Output Current Waveform
FR
FP
tw
tw
Do
IDO
High Impedance State
6
WB1330
Timing Waveforms (continued)
Serial Data Input Timing Waveform[4, 5, 6, 7]
//
DATA
PD = MSB
PRE
//
B1
A7
CNT2
//
//
//
//
CNT1 = LSB
CLOCK
t3
t2
t1
LE
t4
t5
//
//
Serial Data Input
Data is input serially using the DATA, CLOCK, and LE pins. Two control bits direct data into the locations given in Table 1.
Table 1. Control Configuration
CNT1
CNT2
Function
0
0
Program Reference 2: R = 3 to 32767, set PLL2 (low frequency) phase detector
polarity, set current in PLL2, set PLL2 High Impedance State, set monitor selector to PLL2.
0
1
Program Reference 1: R = 3 to 32767, set PLL1 (high frequency) phase detector
polarity, set current in PLL1, set PLL1 High Impedance State, set monitor selector to PLL1
1
0
Program Counter for PLL2: A = 0 to 15, B = 3 to 2047, set PLL2 prescaler ratio, set powerdown to PLL2.
1
1
Program Counter for PLL1: A = 0 to 63, B = 3 to 2047, set PLL1 prescaler ratio, set powerdown to PLL1.
Notes:
4. t1–t5 = 50 µs > t > 0.5 µs.
5. CLOCK may remain HIGH after latching in data.
6. DATA is shifted in with the MSB first.
7. For DATA definitions, refer to Table 2.
7
WB1330
Table 2. Shift Register Configuration[8]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
FC
IDO
TS
LD
FO
B9
B10 B11 PRE PD
Reference Counter and Configuration Bits
CNT1 CNT2 R1
R2
R3
R4
R5
R6
R7
R8
R9
A4
A5
A6
A7
B1
B2
R10 R11 R12 R13 R14 R15
Programmable Counter bits
CNT1 CNT2 A1
A2
A3
B3
B4
B5
B6
B7
B8
Bit(s) Name
Function
CNT1, CNT2
Control Bits: Directs programming data to PLL1 (high frequency) or PLL2 (low frequency).
R1–R15
Reference Counter Setting Bits: 15 bits, R = 3 to 32767.[9]
FC
Phase Sense of the Phase Detector: Set to match the VCO polarity, H = + (Positive VCO transfer function).
IDO
Charge Pump Setting Bit: IDO HIGH = 3.8 mA, ID O LOW = 1 mA.
TS
High Impedance State Bit: Makes DO High Impedance State for PLL1 and PLL2 when HIGH.
LD
Lock Detect: Directs the lock detect signal source pin 10. Pin 10 is HIGH with narrow low excursions when
locked. When not locked, this pin is LOW.
FO
Frequency Out: This bit can be set to read out reference or programmable divider at the LD pin for test
purposes.
PRE
Prescaler Divide Bit: For PLL1: LOW = 32/33 and HIGH = 64/65. For PLL2: LOW = 8/9 and HIGH = 16/17.
PD
Power-down: LOW = power-up and HIGH = power-down. FIN is at a high-impedance state, respective B
counter is disabled, forces three-state at DO outputs and phase comparators are disabled. The reference
counter is disabled and the OSC input is high-impedance after both PLLs are powered down. Data can be input
and latched in the power-down state.
A1–A7
Swallow Counter Divide Ratio: A = 0 to 63 for PLL1 and 0 to 15 for PLL2.
B1–B11
Programmable Counter Divide Ratio: B = 3 to 2047.[9]
Table 3. FO/LD Pin Truth Table
FO (Bit 22)
LD (Bit 21)
PLL1
PLL2
PLL1
PLL2
0
0
0
0
Disable
0
0
0
1
PLL2 Lock Detect
0
0
1
0
PLL1 Lock Detect
0
0
1
1
PLL1/PLL2 Lock Detect
0
1
X
0
PLL2 Reference Divider Output
1
0
X
0
PLL1 Reference Divider Output
0
1
X
1
PLL2 Programmable Divider Output
1
0
X
1
PLL1 Programmable Divider Output
1
1
0
1
PLL2 Counter Reset
1
1
1
0
PLL1 Counter Reset
1
1
1
1
PLL1/PLL2 Counter Reset
Notes:
8. The MSB is loaded in first.
9. Low count ratios may violate frequency limits of the phase detector.
8
FO/LD Pin Output State
WB1330
Table 4. 7-Bit Swallow Counter (A) Truth Table[10]
Divide Ratio A
A7
A6
A5
A4
A3
A2
A1
0
X
0
0
0
0
0
0
1
X
0
0
0
0
0
1
:::
:::
:::
:::
:::
:::
:::
:::
62
X
1
1
1
1
1
0
63
X
1
1
1
1
1
1
X
X
X
0
0
0
0
PLL1 (High Frequency)
PLL2 (Low Frequency)
0
1
X
X
X
0
0
0
1
:::
:::
:::
:::
:::
:::
:::
:::
14
X
X
X
1
1
1
0
15
X
X
X
1
1
1
1
Table 5. 11-Bit Programmable Counter (B) Truth Table[11]
Divide Ratio B
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
3
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
1
0
0
:::
:::
:::
:::
:::
:::
:::
:::
:::
:::
:::
:::
2046
1
1
1
1
1
1
1
1
1
1
0
2047
1
1
1
1
1
1
1
1
1
1
1
Table 6. 15-Bit Programmable Reference Counter (for PLL1 and PLL2) Truth Table[11]
Divide Ratio R
R15
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
3
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
:::
:::
:::
:::
:::
:::
:::
:::
:::
:::
:::
:::
:::
:::
:::
:::
32766
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
32767
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Ordering Information[12]
Ordering Code
WB1330
Package
Name
Package Type
X
20-pin TSSOP (0.173” wide)
TR
Tape and Reel Option
Notes:
10. B is greater than or equal to A.
11. Divide ratio less than 3 is prohibited. The divide ratio can be calculated using the following equation:
fvco = {(P * B) + A} * fosc / R where (A < B)
fvco: Output frequency of the external VCO.
fosc: The crystal reference oscillator frequency.
A: Preset divide ratio of the 7-bit swallow counter (0 to 63) and the 4-bit swallow counter (0 to 15).
B: Preset ratio of the 11-bit programmable counter (3 to 2047).
P: Preset divide ratio of the dual modulus prescaler.
R: Preset ratio of the 15-bit programmable reference counter (3 to 32767).
The divide ratio N = (P * B) + A.
12. Operating temperature range: –40°C to +85°C.
Document #: 38-00826-B
9
WB1330
Package Diagram
20-Pin Thin Shrink Small Outline Package (TSSOP, 0.173” wide)
Physical Dimensions In Millimeters
20 Lead (0.173" Wide) TSSOP Package Order Number X
20" clear antistatic tubes, 76 units/tube
JEDEC Outline MO-153
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.