WC32P020-XXM 68020 FEATURES ■ Selection of Processor Speeds: 16.67, 20, 25 MHz ■ High-Performance Asynchronous Bus Is Nonmultiplexed and Full 32-Bits ■ Military Temperature Range: -55°C to +125°C ■ Dynamic Bus Sizing Efficiently Supports 8-/16-/32-Bit Memories and Peripherals ■ Packaging • 114 pin Ceramic PGA (P2) ■ Full Support of Virtual Memory and Virtual Machine • 132 lead Ceramic Quad Flatpack, CQFP (Q2) ■ 16 32-Bit General-Purpose Data and Address Registers ■ Object-code compatible with earlier 68000 Microprocessors ■ Two 32-Bit Supervisor Stack Pointers and Five SpecialPurpose Control Registers ■ Addressing mode extensions for enhanced support of highlevel languages ■ 18 Addressing Modes and 7 Data Types ■ Bit Field Data Type Accelerates Bit-Oriented Applications– i.e., Video Graphics ■ 4 GigaByte Direct Addressing Range ■ Fast On-Chip Instruction Cache Speeds Instructions and Improves Bus Bandwidth DESCRIPTION ■ Coprocessor Interface to Companion 32-Bit Peripherals–the 68881 and 68882 Floating-Point Coprocessors and the 68851 Paged Memory Management Unit The WC32P020 is a 32-bit implementation of the 68000 Family of microprocessors. Using HCMOS technology, the WC32P020 is implemented with 32-bit registers and data paths, 32-bit addresses, a powerful instruction set, and flexible addressing modes. ■ Pipelined Architecture with High Degree of Internal Parallelism allowing Multiple Instructions to be executed concurrently FIG. 1 BLOCK DIAGRAM December 1998 1 White Microelectronics • Phoenix, AZ • (602) 437-1520 WC32P020-XXM FIG. 2 PIN CONFIGURATION FOR WC32P020-XXM, CQFP (Q2) 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 NC NC GND BG VDD GND GND CLK RESET VDD VDD RMC FC0 FC1 FC2 SIZ0 SIZ1 DBEN ECS CDIS AVEC DSACK0 DSACK1 BERR GND GND HALT AS DS GND GND R/W NC TOP VIEW NC BGAC BR A0 A1 A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 VDD VDD GND GND A16 A15 A14 A13 A12 A11 A10 NC NC 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 NC NC NC A9 A8 A7 A6 A5 A4 A3 A2 GND OSC IPEND VDD VDD GND GND IPL2 IPL1 IPL0 D0 D1 D2 D3 D4 GND GND VDD VDD D5 NC NC 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 NC D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 GND GND VDD VDD D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 NC NC FIG. 3 PIN CONFIGURATION FOR WC32P020-XXM, PGA (P2) N D31 D28 D25 D22 D20 D17 GND VCC D14 D12 D9 D8 VCC DS D29 D26 D24 D21 D18 D16 VCC D13 D10 D6 D5 D4 AS R/W D30 D27 D23 D19 GND D15 D11 D7 GND D3 D2 D1 D0 IPL0 IPL1 M L K GND HALT GND J DSACK1 BERR GND H CDIS AVEC DSACK0 IPL2 GND G ECS SIZ1 DBEN VCC GND VCC F FC2 FC1 FC0 RMC VCC A2 OCS VCC VCC A4 A3 SIZ0 GND IPEND E D VCC C RESET CLK GND A0 A29 A25 A21 A17 A16 A12 A9 A7 A5 A6 B BG BR A30 A27 A24 A20 A18 GND D15 D13 A10 BGACK A1 A31 A28 A26 A23 A22 A19 VCC GND A14 A11 A8 3 4 5 6 7 8 9 10 11 12 13 GND A 1 White Microelectronics • Phoenix, AZ • (602) 437-1520 2 2 WC32P020-XXM ADDRESSING MODES Addressing Register Direct Data Register Direct Address Register Direct Register Indirect Address Register Indirect Address Register Indirect with Postincrement Address Register Indirect with Predecrement Address Register Indirect with Displacement Register Indirect with Index Address Register Indirect with Index (8-Bit Displacement) Address Register Indirect with Index (Base Displacement) Memory Indirect Memory Indirect Postindexed Memory Indirect Preindexed Program Counter Indirect with Displacement Program Counter Indirect with Index PC Indirect with Index (8-Bit Displacement) PC Indirect with Index (Base Displacement) Program Counter Memory Indirect PC Memory Indirect Postindexed PC Memory Indirect Preindexed Absolute Absolute Short Absolute Long Immediate Syntax Mnemonic Dn An (An) (An) + - (An) (d16,An) (d8,An,Xn) (bd,An,Xn) ([bd,An],Xn,od) ([bd,An,Xn],od) (d16,PC) (d8,PC,Xn) (bd,PC,Xn) ([bd,PC],Xn,od) ([bd,PC,Xn],od) (xxx).W (xxx).L #(data) NOTES: Dn = Data Register, DO-D7 An = Address Register, AO-A7 d8, d 16 = A twos-complement or sign-extended displacement; added as part of the effective address calculation; size is 8 (d8) or 16 (d16) bits; when omitted, assemblers use a value of zero. Xn = Address or data register used as an index register; form is Xn.SIZE*SCALE, where SIZE is.W or .L (indicates index register size) and SCALE is 1, 2, 4, or 8 (index register is multiplied by SCALE); use of SIZE and/or SCALE is optional. bd = A twos-complement base displacement; when present, size can be 16 or 32 bits. od = 0uter displacement, added as part of effective address calculation after any memory indirection, use is optional with a size of 16 or 32 bits. PC = Program Counter (data) = Immediate value of 8, 16, or 32 bits ( ) = Effective Address [ ] = Use as indirect access to long-word address. INSTRUCTION SET Mnemonic ABCD ADD ADDA ADDI ADDQ ADDX AND ANDI ASL, ASR Description Add Decimal with Extend Add Add Address Add Immediate Add Quick Add with Extend Logical AND Logical AND Immediate Arithmetic Shift Left and Right 3 Description Bcc BCHG BCLR BFCHG BFCLR BFEXTS BFEXTU BFFFO BFINS BFSET BFTST BKPT BRA BSET BSR BTST Branch Conditionally Test Bit and Change Test Bit and Clear Test Bit Field and Change Test Bit Field and Clear Signed Bit Field Extract Unsigned Bit Field Extract Bit Field Find First One Bit Field Insert Test Bit Field and Set Test Bit Field Breakpoint Branch Test Bit and Set Branch to Subroutine Test Bit CALLM CAS Call Module Compare and Swap Operands CAS2 CHK CHK2 CLR CMP CMPA CMPI CMPM CMP2 Compare and Swap Dual Operands Check Register Against Bound Check Register Against Upper and Lower Bounds Clear Compare Compare Address Compare Immediate Compare Memory to Memory Compare Register Against Upper and Lower Bounds DBcc DIVS, DIVSL DIVU, DIVUL Test Condition, Decrement and Branch Signed Divide Unsigned Divide EOR EORI EXG EXT, EXTB Logical Exclusive OR Logical Exclusive OR Immediate Exchange Registers Sign Extend ILLEGAL Take Illegal Instruction Trap JMP JSR Jump Jump to Subroutine LEA LINK LSL, LSR Load Effective Address Link and Allocate Logical Shift Left and Right MOVE MOVEA MOVE CCR MOVE SR MOVE USP MOVEC MOVEM MOVEP MOVEQ MOVES Move Move Address Move Condition Code Register Move Status Register Move User Stack Pointer Move Control Register Move Multiple Registers Move Peripheral Move Quick Move Alternate Address Space MULS MULU Signed Multiply Unsigned Multiple White Microelectronics • Phoenix, AZ • (602) 437-1520 WC32P020-XXM SIGNAL DESCRIPTION INSTRUCTION SET (cont.) Mnemonic The Vcc and GND pins are separated into four groups to provide individual power supply connections for the address bus buffers, data bus buffers, and all other buffers and internal logic. See Fig. 4. Description NBCD NEG NEGX NOP NOT Negate Decimal with Extend Negate Negate with Extend No Operation Logical Complement OR ORI ORI CCR ORI SR Logical Inclusive OR Logical Inclusive OR Immediate Logical Inclusive OR Immediate to Condition Codes Logical Inclusive OR Immediate to Status Register PACK PEA Pack BCD Push Effective Address RESET ROL, ROR ROXL, ROXR RTD RTE RTM RTR RTS Reset External Devices Rotate Left and Right Rotate with Extend Left and Right Return and Deallocate Return from Exception Return from Module Return and Restore Codes Return from Subroutine SBCD Scc STOP SUB SUBA SUBI SUBQ SUBX SWAP Subtract Decimal with Extend Set Conditionally Stop Subtract Subtract Address Subtract Immediate Subtract Quick Subtract with Extend Swap Register Words TAS TRAP TRAPcc TRAPV TST Test Operand and Set Trap Trap Conditionally Trap on Overflow Test Operand UNLK UNPK Unlink Unpack BCD Mnemonic Mnemonic cpRESTORE cpSAVE cpScc cpTRAPcc GND A10, B9, C3, F12 Data Bus M8, N8, N13 L7, L11, N7, K3 Logic D1, D2, E3, G11, G13 G12, H13, J3, K1 Clock — B1 FUNCTIONAL SIGNAL GROUPS FUNCTION CODES FC0-FC2 ADDRESS BUS A0-A31 DATA BUS D0-D31 CDIS TRANSFER SIZE ASYNCHRONOUS BUS CONTROL Description Description Restore Internal State of Coprocessor Save Internal State of Coprocessor Set Conditionally Trap Conditionally 4 CACHE CONTROL INTERRUPT PRIORITY IPL0-IPL2 IPEND AVEC Branch Conditionally Test Coprocessor Condition, Decrement and Branch Coprocessor General Instruction White Microelectronics • Phoenix, AZ • (602) 437-1520 Vcc A9, D3 FIG. 4 Coprocessor Instructions cpBcc cpDBcc cpGEN Group Address Bus SIZ0 SIZ1 ECS OCS RMC AS DS R/W DBEN DSACK0 DSACK1 INTERRUPT CONTROL BR BG BGACK BUS ARBITRATION CONTROL RESET HALT BERR BUS EXCEPTION CONTROL CLK Vcc (10) GND (13) WC32P020-XXM SIGNAL INDEX Signal Name Mnemonic Function Function Codes FC2-FC0 3-bit function code used to identify the address space of each bus cycle. Address Bus A0-A31 32-bit address bus. Data Bus D0-D31 32-bit data bus used to transfer 8, 16, 24, or 32 bits of data per bus cycle. Size SIZ0/SIZ1 Indicates the number of bytes remaining to be transferred for this cycle. These signals, together with A1 and A0, define the active sections of the data bus. External Cycle Start ECS Provides an indication that a bus cycle is beginning. Operand Cycle Start OCS Identical operation to that of ECS except that OCS is asserted only during the first bus cycle of an operand transfer. Read,Write R/W Defines the bus transfer as a processor read or write. Read-Modify-Write Cycle RMC Provides an indicator that the current bus cycle is part of an indivisible read-modify-write operation. Address Strobe AS Indicates that a valid address is on the bus. Data Strobe DS Indicates that valid data is to be placed on the data bus by an external device or has been placed on the data bus by the WC32P020-XXM. Data Buffer Enable DBEN Data Transfer and Size Acknowledge DSACK0/DSACK1 Interrupt Priority Level IPL0-IPL2 Provides an enable signal for external data buffers. Bus response signals that indicate the requested data transfer operation has completed. In addition, these two lines indicate the size of the external bus port on a cycle-by-cycle basis and are used for asynchronous transfers. Provides an encoded interrupt level to the processor. Interrupt Pending IPEND Indicates that an interrupt is pending. Autovector AVEC Requests an autovector during an interrupt acknowledge cycle. Bus Request BR Indicates that an external device requires bus mastership. Bus Grant BG Indicates that an external device may assume bus mastership. Bus Grant Acknowledge BGACK Indicates that an external device has assumed bus mastership. Reset RESET System reset. Halt HALT Indicates that the processor should suspend bus activity. Bus Error BERR Indicates that an erroneous bus operation is being attempted. Cache Disable CDIS Dynamically disables the on-chip cache to assist emulator support Clock CLK Clock input to the processor. Power Supply Vcc Power supply. Ground GND Ground connection. 5 White Microelectronics • Phoenix, AZ • (602) 437-1520 WC32P020-XXM MAXIMUM RATINGS Symbol Vcc VI Parameter THERMAL CHARACTERISTICS (with no heat sink or airflow) Min Max Unit Supply voltage -0.3 +7.0 V Input voltage -0.3 +7.0 V 2.0 W Pdmax Max Power dissipation Characteristic Tcase Operating temperature (Mil.) -55 +125 °C Tcase Operating temperature (Ind.) -40 +85 °C Tstg Storage temperature -55 +150 °C Tj Junction temperature +160 °C The average chip junction temperature, TJ, in °C can be obtained from: (1) where: TA = Ambient Temperature, °C θJA = Package Thermal Resistance, Junction-to-Ambient, °C/W PD = PINT+PI/O PINT = ICC x VCC, Watts-Chip Internal Power PI/O = Power Dissipation on Input and Output Pins-User Determined For most applications, PI/O<PlNT and can be neglected. The following is an approximate relationship between PD and TJ (if PI/O is neglected ): PD = K÷(T J + 273°C) (2) Solving equations (1) and (2) for K gives: K = PD • (TA + 273°C) + θJA • PD2 (3) where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA . Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA . The total thermal resistance of a package (θJA) can be separated into two components, θJC and θCA, representing the barrier to heat flow from the semiconductor junction to the package (case) surface (θJC) and from the case to the outside ambient (θCA). These terms are related by the equation: θJA = θJC + θCA White Microelectronics • Phoenix, AZ • (602) 437-1520 Thermal Resistance — Junction to Ambient PGA Package CQFP Package θJA Thermal Resistance — Junction to Case PGA Package CQFP Package θJC Value Rating °C/W 26 46 °C/W 3 15 θJC is device related and cannot be influenced by the user. However, θCA is user dependent and can be minimized by such thermal management techniques as heat sinks, ambient air cooling, and thermal convection. Thus, good thermal management on the part of the user can significantly reduce θCA so that θJA approximately equals θJC. Substitution of θJC for θJA in equation (1) will result in a lower semiconductor junction temperature. POWER CONSIDERATIONS TJ = TA + (PD • θJA) Symbol (4) 6 WC32P020-XXM DC ELECTRICAL CHARACTERISTICS (VCC = 5.0 VDC ± 5%, GND = 0 VDC, TA = -55°C to +125°C) Symbol Min Max Unit Input High Voltage Characteristics V IH 2.0 Vcc V Input Low Voltage V IL GND -0.5 0.8 V BERR, BR, BGACK, CLK, IPL0-2, AVEC, CDIS, DSACK0, DSACK1 HALT, RESET IIN -4 4.0 µA -20 20 A 31-0, AS, DBEN, DS, D 31-0 , FC 2-0 R/W, RMC, SIZ 1-0 I TSI -20 20 µA A 31-0 , AS, BG, D 31-0 , DBEN, DS, ECS, R/W, IPEND, OCS, RMC, SIZ 1-0 , FC 2-0 V OH 2.4 - V - 0.5 0.5 0.5 0.5 Input Leakage Current GND ≤ VIN ≤ Vcc High-Z (Off State) Leakage Current Output High Voltage Output Low Voltage I OL = 3.2 mA I OL = 5.3 mA I OL = 2.0 mA I OL = 10.7 mA V OL V A 31-0 , FC 2-0 , SIZ 1-0 , BG, D 31-0 AS, DS, R/W, RMC, DBEN, IPEND ECS, OCS HALT, RESET Maximum Supply Current I CC - 333 mA Capacitance (1) V IN = 0V, T A = 25°C, f = 1MHz C IN - 20 pF CL - 50 130 pF Load Capacitance ECS, OCS All Other NOTES: 1. Capacitance is guaranteed by design but not tested. AC ELECTRICAL SPECIFICATIONS – CLOCK INPUT (see Fig. 5) Characteristic Specification Frequency of Operation 16.67 MHz Min Max 20 MHz Min 25MHz Max Min Unit Max 8 16.67 12.5 20 12.5 25 MHz 1 60 125 50 80 40 80 ns Clock Pulse Width 2,3 24 95 20 54 19 61 ns Rise and Fall Times 4,5 – 5 – 5 – 4 ns Cycle Time FIG.5 CLOCK INPUT TIMING DIAGRAM 1 2 3 2.0 V 0.8 V 4 5 NOTE: Timing measurements are referenced to and from a low 0.8V and a high voltage of 2.0V, unless otherwise noted. The voltage swing through this range should start outside and pass through the range such that the rise or fall will be linear between 0.8V and 2.0V. 7 White Microelectronics • Phoenix, AZ • (602) 437-1520 WC32P020-XXM AC ELECTRICAL SPECIFICATIONS – READ AND WRITE CYCLES (VCC = 5.0 V DC ± 5%, GND = 0 VDC, TA = -55°C to +125°C) Characteristic Clock high to Address, FC, Size, RMC Valid Clock High to ECS, OCS Asserted Clock High to Address, Data, FC, Size, RMC, High Impedance Specification 16.67 MHz Min Max 20 MHz Min Max 25 MHz Min Max Unit 6 0 30 0 25 0 25 6A 0 20 0 15 0 12 ns ns 7 0 60 0 50 0 40 ns Clock high to Address, FC, Size, RMC Invalid 8 0 - 0 - 0 - ns Clock Low to AS, DS Asserted 9 1 30 1 25 1 18 ns AS to DS Assertion (Read) (Skew) 9A (1) -15 15 -10 10 -10 10 ns AS Asserted to DS Asserted (Write) 9B (11) 37 - 32 - 27 - ns ECS Width Asserted 10 20 - 15 - 15 - ns OCS Width Asserted 10 20 - 15 - 15 - ns 10B (7) 15 - 10 - 5 - ns Address, FC, Size, RMC, Valid to AS (and DS Asserted Read) 11 15 - 10 - 6 - ns Clock Low to AS, DS Negated 12 0 30 0 25 0 15 ns 12A 0 30 0 25 0 15 ns ECS, OCS width Negated Clock Low to ECS, OCS Negated AS, DS Negated to Address, FC, Size, RMC Invalid 13 15 - 10 - 10 - ns AS (and DS Read) Width Asserted 14 100 - 85 - 70 - ns DS Width Asserted Write AS, DS Width Negated DS Negated to AS Asserted 14A 40 - 38 - 30 - ns 15 40 - 38 - 30 - ns ns 15A (8) 35 - 30 - 25 - Clock High to AS, DS, R/W Invalid, High Impedance 16 - 60 - 50 - 40 ns AS, DS Negated to R/W Invalid 17 15 - 10 - 10 - ns Clock High to R/W High 18 0 30 0 25 0 20 ns Clock High to R/W Low 20 0 30 0 25 0 20 ns R/W High to AS Asserted 21 15 - 10 - 5 - ns R/W Low to DS Asserted (Write) 22 75 - 60 - 50 - ns Clock High to Data Out Valid 23 - 30 - 25 - 25 ns ns DS Negated to Data Out Invalid 25 15 - 10 - 5 - DS Negated to DBEN Negated (Write) 25A (9) 15 - 10 - 5 - ns Data Out Valid to DS Asserted (Write) 26 15 - 10 - 5 - ns Data-In Valid to Clock Low (Data Setup) Late BERR/HALT Asserted to Clock Low Setup Time 27 5 - 5 - 5 - ns 27A 20 - 15 - 10 - ns AS, DS Negated to DSACKx, BERR, HALT, AVEC Negated 28 0 80 0 65 0 50 ns DS Negated to Data-In Invalid (Data-In Hold Time) 29 0 - 0 - 0 - ns DS Negated to Data-In (High Impedance) DSACKx Asserted to Data-In Valid DSACKx Asserted to DSACKx Valid (DSACK Asserted Skew) 29A - 60 - 50 - 40 ns 31 (2) - 50 - 43 - 32 ns 31A (3) - 15 - 10 - 10 ns Clks RESET Input Transition Time 32 - 1.5 - 1.5 - 1.5 Clock Low to BG Asserted 33 0 30 0 25 0 20 ns Clock Low to BG Negated 34 0 30 0 25 0 20 ns BR Asserted to BG Asserted (RMC Not Asserted) 35 1.5 3.5 1.5 3.5 1.5 3.5 Clks BGACK Asserted to BG Negated 37 1.5 3.5 1.5 3.5 1.5 3.5 Clks White Microelectronics • Phoenix, AZ • (602) 437-1520 8 WC32P020-XXM AC ELECTRICAL SPECIFICATIONS – READ AND WRITE CYCLES (cont.) Characteristic Specification BGACK Asserted to BR Negated 16.67 MHz Min Max 20 MHz Min Max 25MHz Min Max Unit 37A (6) 0 1.5 0 1.5 0 1.5 BG Width Negated 39 90 - 75 - 60 - Clks ns BG Width Asserted 39A 90 - 75 - 60 - ns Clock High to DBEN Asserted (Read) 40 0 30 0 25 0 20 ns Clock High to DBEN Negated (Read) 41 0 30 0 25 0 20 ns Clock High to DBEN Asserted (Write) 42 0 30 0 25 0 20 ns Clock High to DBEN Negated (Write) 43 0 30 0 25 0 20 ns R/W Low to DBEN Asserted (Write) 44 15 - 10 - 10 - ns 45 (5) 60 120 - 50 100 - 40 80 - ns R/W Width Valid (Write or Read) 46 150 - 125 - 100 - ns Asynchronous Input Setup Time 47A 5 - 5 - 5 - ns Asynchronous Input Hold Time 47B 15 - 15 - 10 - ns DBEN Width Asserted DSACKx Asserted to BERR, HALT Asserted Read Write 48 (4) - 30 - 20 - 18 ns Data Out Hold from Clock High 53 0 - 0 - 0 - ns R/W Valid to Data Bus Impedance Change 55 30 - 25 - 20 - ns RESET Pulse Width (Reset Instruction) 56 512 - 512 - 512 - Clks BERR Negated to HALT Negated (Rerun) 57 0 - 0 - 0 - ns BGACK Negated to Bus Driven 58 (10) 1 - 1 - 1 - Clks BG Negated to Bus Driven 59 (10) 1 - 1 - 1 - Clks NOTES: 1. This number can be reduced to 5ns if strobes have equal loads. 2. If the asynchronous setup time (#47A) requirements are satisfied, the DSACKx low data setup time (#31) and DSACKx low to BERR low setup time (#48) can be ignored. The data must only satisfy the data-in to clock low setup time (#27) for the following clock cycle, and BERR must only satisfy the late BERR low to clock low setup time (#27A) for the following clock cycle. 3. This parameter specifies the maximum allowable skew between DSACK0 to DSACK1 asserted or DSACK1 to DSACK0 asserted; specification #47A must be met by DSACK0 or DSACK1. 4. This specification applies to the first (DSACK0 or DSACK1) DSACKx signal asserted. In the absence of DSACKx, BERR is an asynchronous input setup time (347A). 5. DBEN may stay asserted on consecutive write cycles. 6. The minimum values must be met to guarantee proper operation. If this maximum value is exceeded, BG may be reasserted. 7. This specification indicates the minimum high time for ECS and OCS in the event of an internal cache hit followed immediately by a cache miss or operand cycle. 8. This specification guarantees operation with the 68881/68882, which specifies a minimum time for DS negated to AS asserted. Without this specification, incorrect interpretation of specifications #9A and #15 would indicate that the WC32P020-XXM does not meet the 68881/68882 requirements. 9. This specification allows a system designer to guarantee data hold times on the output side of data buffers that have output enable signals generated with DBEN. 10. These specifications allow system designers to guarantee that an alternate bus master has stopped driving the bus when the 68020 regains control of the bus after an arbitration sequence. 11. This specification allows system designers to qualify the CS signal of an 68881/68882 with AS (allowing 7 ns for a gate delay) and still meet the CS to DS setup time requirement. 9 White Microelectronics • Phoenix, AZ • (602) 437-1520 WC32P020-XXM FIG. 6 READ CYCLE TIMING DIAGRAM NOTE: Timing measurements are referenced to and from a low 0.8V and a high voltage of 2.0V, unless otherwise noted. The voltage swing through this range should start outside and pass through the range such that the rise or fall will be linear between 0.8V and 2.0V. White Microelectronics • Phoenix, AZ • (602) 437-1520 10 WC32P020-XXM FIG. 7 WRITE CYCLE TIMING DIAGRAM NOTE: Timing measurements are referenced to and from a low 0.8V and a high voltage of 2.0V, unless otherwise noted. The voltage swing through this range should start outside and pass through the range such that the rise or fall will be linear between 0.8V and 2.0V. 11 White Microelectronics • Phoenix, AZ • (602) 437-1520 WC32P020-XXM FIG. 8 BUS ARBITRATION TIMING DIAGRAM NOTE: Timing measurements are referenced to and from a low 0.8V and a high voltage of 2.0V, unless otherwise noted. The voltage swing through this range should start outside and pass through the range such that the rise or fall will be linear between 0.8V and 2.0V. White Microelectronics • Phoenix, AZ • (602) 437-1520 12 WC32P020-XXM FIG. 9 114 PIN GRID ARRAY, PGA (P2) 34.55 (1.360) ± 0.50 (0.020) SQ. 4.64 (0.182) ± 0.32 (0.012) 2.54 (0.100) N M L 2.54 (0.100) K J H G F 0.49 (0.019) ± 0.06 (0.002) E D C B A 1 2 3 4 6 5 7 8 10 11 12 13 9 3.18 (0.125) ± 0.64 (0.025) ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES FIG. 10 132 LEAD, CERAMIC QUAD FLAT PACK, CQFP (Q2) 27.43 (1.080) SQ ± 0.12 (0.005) 4.13 (0.162) ± 0.19 (0.007) 22.36 (0.880) ± 0.50 (0.020) SQ Pin 1 4.13 (0.162) ± 0.19 (0.007) 27.43 (1.080) ± 0.12 (0.005) 20.32 (0.800) REF 0° - 8° 0.76 (0.030) ± 0.12 (0.005) 0.64 (0.025) ± 0.13 (0.005) 0.64 (0.025) MIN DETAIL A 0.64 (0.025) 0.25 (0.010) ± 0.04 (0.002) DETAIL A 0.17 (0.006) ± 0.04 (0.001) ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES 13 White Microelectronics • Phoenix, AZ • (602) 437-1520 WC32P020-XXM ORDERING INFORMATION W C 32 P020 - X X M DEVICE GRADE: M = Military Temperature -55°C to +125°C PACKAGE: Q2 = 132 Lead Ceramic Quad Flatpack, CQFP P2 = 114 Pin Ceramic PGA Operating Frequency in MHz 68020 32 bit Wide MICROCONTROLLER WHITE MICROELECTRONICS White Microelectronics • Phoenix, AZ • (602) 437-1520 14