WED2DG472512V-D2 16MB (4x512Kx72) SYNC BURSTPIPELINE, DUAL KEY DIMM ADVANCED* FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ FIG. 1 4x512Kx72 Synchronous, Synchronous Burst Pipeline Architecture; Single Cycle Deselect Linear and Sequential Burst Support via MODE pin Clock Controlled Registered Module Enable (EM) Clock Controlled Registered Bank Enables (E1, E2, E3, E4) Clock Controlled Byte Write Mode Enable (BWE) Clock Controlled Byte Write Enables (BW1 - BW8) Clock Controlled Registered Address Clock Controlled Registered Global Write (GW) Asynchronous Output Enable (G) Internally Self-Timed Write Individual Bank Sleep Mode Enables (ZZ1, ZZ2, ZZ3, ZZ4) Gold Lead Finish 3.3V ± 10% Operation Frequency(s): 200, 166, 150, and 133MHz Access Speed(s): tKHQV = 3.0, 3.5, 3.7, and 4.0ns Common Data I/O High Capacitance (30pF) Drive, at Rated Access Speed Single Total Array Clock Multiple Vcc and Gnd for Improved Noise Immunity PIN CONFIGURATION PIN IDENTIFIER VSS A0 A16 A2 A14 VCC A4 A12 A6 A10 VSS A8 RFU E4 E2 VSS MODE EM GW RFU VCC BW4 BW3 BW8 BW7 ADSC ADSP VSS NC VCC DQ0 DQ1 DQ2 DQ3 VSS ZZ1 VCC DQ8 DQ9 DQ10 DQ11 VSS DESCRIPTION The WED2DG472512V is a Synchronous/Synchronous Burst SRAM, 84 position Dual Key; Double High DIMM (168 contacts) Module, organized as 4x512Kx72. The Module contains sixteeen (16) Synchronous Burst RAM devices, packaged in the industry standard JEDEC 14mmx20mm TQFP placed on a Multilayer FR4 Substrate. The Module Architecture is defined as a Sync/SyncBurst, Pipeline, with support for either linear or sequential burst. This Module provides high performance, 3-1-1-1 accesses when used in Burst Mode, and when used in Synchronous Only Mode, provides a high performance, data access every second cycle. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 VSS A17 A1 A15 A3 VCC A13 A5 A11 A7 VSS A9 A18 E1 E3 VSS CLK VSS G BWE VCC BW2 BW1 BW6 BW5 VSS ADV VSS DQP0 VCC DQ7 DQ6 DQ5 DQ4 VSS DQP1 VCC DQ15 DQ14 DQ13 DQ12 VSS NC VCC DQ16 DQ17 DQ18 DQ19 VSS ZZ2 VCC DQ24 DQ25 DQ26 DQ27 VSS NC VCC DQ32 DQ33 DQ34 DQ35 VSS ZZ3 VCC DQ40 DQ41 DQ42 DQ43 VSS NC VCC DQ48 DQ49 DQ50 DQ51 VSS ZZ4 VCC DQ56 DQ57 DQ58 DQ59 VSS 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 DQP2 VCC DQ23 DQ22 DQ21 DQ20 VSS DQP3 VCC DQ31 DQ30 DQ29 DQ28 VSS DQP4 VCC DQ39 DQ38 DQ37 DQ36 VSS DQP5 VCC DQ47 DQ46 DQ45 DQ44 VSS DQP6 VCC DQ55 DQ54 DQ53 DQ52 VSS DQP7 VCC DQ63 DQ62 DQ61 DQ60 VSS PIN DESCRIPTION Synchronous Only operations are performed via strapping ADSC Low, and ADSP/ADV High, which provides for Ultra Fast Accesses in Read Mode while providing for internally self-timed Early Writes. Synchronous/Synchronous Burst operations are in relation to an externally supplied clock, Registered Address, Registered Global Write, Registered Enables as well as an Asynchronous Output Enable. This Module has been defined with full flexibility, which allows individual control of each of the eight bytes, as well as Quad Words in both Read and Write Operations. DQ0 - DQ63 Input/Output Bus DQP0 - DQP7 Parity Bits A0 - A18 Address Bus EM Module Enable E1, E2, E3, E4 Synchronous Bank Enables BWE Byte Write Mode Enable BW1 - BW8 Byte Write Enables CLK Array Clock GW Synchronous Global Write Enable G Asynchronous Output Enable ZZ1, ZZ2, ZZ3, ZZ4 Bank Sleep Mode Enables Vcc 3.3V Power Supply Vss Ground * This data sheet describes a product that may or may not be under development and is subject to change or cancellation without notice. January 2000 Rev 0 1 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com WED2DG472512V-D2 FIG. 2 FUNCTIONAL BLOCK DIAGRAM ADDR BW8 BW7 BW6 BW5 BW4 BW3 BW2 BW1 BWE E4 E3 E2 E1 BW8 BW7 BW6 BW5 BW4 BW3 BW2 BW1 BWE E4 E3 E2 E1 ADV ADV BW4 BW3 BW2 BW1 BWE BW4 BW3 BW2 BW1 BWE 512K x 18 SBPL SCD E1 ZZ1 ADV ADSP ADSC 512K x 18 SBPL SCD 512K x 18 SBPL SCD E4 ZZ4 GW GW G G 512K x 18 SBPL SCD BW4 BW3 BW2 BW1 BWE 512K x 18 SBPL SCD E3 ZZ3 GW G ADSP ADSC BW4 BW3 BW2 BW1 BWE 512K x 18 SBPL SCD E2 ZZ2 ADV ADSP ADSC GW G 512K x 18 SBPL SCD ADSP ADSC 512K x 18 SBPL SCD Data (DQ) GW G MODE ADSP ADSC ADV BW8 BW7 BW6 BW5 BWE E1 ZZ1 512K x 18 SBPL SCD GW G ZZ1 ZZ2 BW8 BW7 BW6 BW5 BWE E2 ZZ2 ZZ3 ADSP ADSC ZZ4 ADV 512K x 18 SBPL SCD 512K x 18 SBPL SCD BW8 BW7 BW6 BW5 BWE E3 ZZ3 GW G ADSP ADSC GW G 512K x 18 SBPL SCD ADV ADSP ADSC ADV CLK White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com 512K x 18 SBPL SCD BW8 BW7 BW6 BW5 BWE E4 ZZ4 512K x 18 SBPL SCD 512K x 18 SBPL SCD GW G ADSP ADSC 512K x 18 SBPL SCD ADV U1 -U8 EQUAL LENGTH NET ROUTES 2 WED2DG472512V-D2 SYNC BURST – TRUTH TABLE E1 H X L L H H L H L L H H X X H H H H H H X H H H X X H H H H H H X H H H E2 X H H H L L H L H H L L H H X X H H H H H H X H H H X X H H H H H H X H 1234567890123 1234567890123 1234567890123 1234567890123 E3 E4 ADSP 1234567890123 1234567890123 1234567890123 X 1234567890123 1234567890123 1234567890123 1234567890123 X 1234567890123 1234567890123 1234567890123 L 1234567890123 1234567890123 1234567890123 L 1234567890123 1234567890123 1234567890123 L 1234567890123 1234567890123 1234567890123 L 1234567890123 1234567890123 1234567890123 1234567890123 H 1234567890123 1234567890123 1234567890123 H 1234567890123 1234567890123 1234567890123 H 1234567890123 1234567890123 1234567890123 H 1234567890123 1234567890123 1234567890123 1234567890123 H 1234567890123 1234567890123 1234567890123 H 1234567890123 1234567890123 1234567890123 X 1234567890123 1234567890123 1234567890123 X 1234567890123 1234567890123 1234567890123 X 1234567890123 1234567890123 1234567890123 1234567890123 X 1234567890123 1234567890123 1234567890123 X 1234567890123 1234567890123 1234567890123 X 1234567890123 1234567890123 1234567890123 X 1234567890123 1234567890123 1234567890123 X 1234567890123 1234567890123 1234567890123 1234567890123 H 1234567890123 1234567890123 1234567890123 X 1234567890123 1234567890123 1234567890123 H 1234567890123 1234567890123 1234567890123 X 1234567890123 1234567890123 1234567890123 1234567890123 H 1234567890123 1234567890123 1234567890123 H 1234567890123 1234567890123 1234567890123 H 1234567890123 1234567890123 1234567890123 H 1234567890123 1234567890123 1234567890123 X 1234567890123 1234567890123 1234567890123 1234567890123 X 1234567890123 1234567890123 1234567890123 X 1234567890123 1234567890123 1234567890123 X 1234567890123 1234567890123 1234567890123 H 1234567890123 1234567890123 1234567890123 X 1234567890123 1234567890123 1234567890123 1234567890123 H 1234567890123 1234567890123 1234567890123 X 1234567890123 No te A Operation Deselected Cycle, Power Down; Bank 1 Deselected Cycle, Power Down; Bank 2 Read Cycle, Begin Burst; Bank 1 Read Cycle, Begin Burst; Bank 1 Read Cycle, Begin Burst, Bank 2 Read Cycle, Begin Burst; Bank 2 Write Cycle, Begin Burst; Bank 1 Write Cycle, Begin Burst; Bank 2 Read Cycle, Begin Burst; Bank 1 Read Cycle, Begin Burst; Bank 1 Read Cycle, Begin Burst; Bank 2 Read Cycle, Begin Burst; Bank 2 Read Cycle, Continue Burst; Bank 1 Read Cycle, Continue Burst; Bank 1 Read Cycle, Continue Burst; Bank 2 Read Cycle, Continue Burst; Bank 2 Read Cycle, Continue Burst; Bank 1 Read Cycle, Continue Burst; Bank 1 Read Cycle, Continue Burst; Bank 2 Read Cycle, Continue Burst; Bank 2 Write Cycle, Continue Burst; Bank 1 Write Cycle, Continue Burst; Bank 1 Write Cycle, Continue Burst; Bank 2 Write Cycle, Continue Burst; Bank 2 Read Cycle, Suspend Burst; Bank 1 Read Cycle, Suspend Burst; Bank 1 Read Cycle, Suspend Burst; Bank 2 Read Cycle, Suspend Burst; Bank 2 Read Cycle, Suspend Burst; Bank 1 Read Cycle, Suspend Burst; Bank 1 Read Cycle, Suspend Burst; Bank 2 Read Cycle, Suspend Burst; Bank 2 Write Cycle, Suspend Burst; Bank 1 Write Cycle, Suspend Burst; Bank 1 Write Cycle, Suspend Burst; Bank 2 Write Cycle, Suspend Burst; Bank 2 ADSC L L X X X X L L L L L L H H H H H H H H H H H H H H H H H H H H H H H H ADV X X X X X X X X X X X X L L L L L L L L L L L L H H H H H H H H H H H H GW X X X X X X L L H H H H H H H H H H H H L L L L H H H H H H H H L L L L G X X L H L H X X L H L H L H L H L H L H X X X X L H L H L H L H X X X X CLK L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H DQ High-Z High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z Q High-Z Q High-Z Q High-Z Q High-Z D D D D Q High-Z Q High-Z Q High-Z Q High-Z D D D D Addr. Used None None External External External External External External External External External External Next Next Next Next Next Next Next Next Next Next Next Next Current Current Current Current Current Current Current Current Current Current Current Current Note A: All truth Table Functions Repeat for Bank 3 (E3) and Bank 4 (E4). 3 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com WED2DG472512V-D2 ABSOLUTE MAXIMUM RATINGS* Voltage on Vcc Relative to Vss Vin Storage Temperature Operating Temperature (Commercial) Operating Temperature (Industrial) Short Circuit Output Current RECOMMENDED DC OPERATING CONDITIONS Parameter Supply Voltage Supply Voltage Input High Input Low Input Leakage Output Leakage -0.3V to +4.6V -0.3V to Vcc +0.5V -55°C to + 125°C 0°C to +70°C -40°C to +85°C 100mA *Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Sym Vcc Vss ViH ViL ILi ILo Min 3.3 0 2.0 -0.3 -2 -2 Typ 3.3 0 3.0 0 1 1 Max 3.6 0 Vcc+0.3 0.3 2 2 Units V V V V µA µA SYNCHRONOUS ONLY – TRUTH TABLE Operation Synchronous Write - Bank 1 Synchronous Read - Bank 1 Synchronous Write - Bank 2 Synchronous Read - Bank 2 Synchronous Write - Bank 3 Synchronous Read - Bank 3 Synchronous Write - Bank 4 Synchronous Read - Bank 4 Snooze Mode E1 L L H H H H H H X E2 H H L L H H H H X E3 H H H H L L H H X E4 H H H H H H L L X GW L H L H L H L H X G H L H L H L H L X ZZ L L L L L L L L H CLK DQ High-Z ↑ ↑ ↑ High-Z ↑ ↑ High-Z ↑ ↑ High-Z ↑ X High-Z DC ELECTRICAL CHARACTERISTICS READ CYCLE Max Description Sym Typ 5.0 6.0 6.5 7.0 Units Power Supply Current Icc1 1.9 2.7 2.5 2.4 2.3 A Power Supply Current Icc 875 1.8 1.8 1.3 1.3 A Snooze Mode IccZZ 270 350 350 350 350 mA CMOS Standby Icc3 500 700 700 700 700 mA Clock Running-Deselect IccK 900 1.1 1.1 1.0 1.0 A Device Selected, No Operation AC TEST CONDITIONS AC TEST LOAD DQ Output Input Pulse Levels Input and Output Timing Ref. Output Test Equivalencies Z0 Z0==50Ω 50Ω RL = 50Ω VL = 1.25V Output Test Equivalencies White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com 4 Vss to 3.0V 1.25V see figure at left WED2DG472512V-D2 SYNC-BURST READ CYCLE PARAMETERS 3.0ns Description Frequency Clock Cycle Time Clock High Time Clock Low Time Clock to Output Valid Clock to Output Invalid Clock to Output Low-Z Output Enable to Output Valid Output Enable to Output Low-Z Output Enable to Output High-Z Address Setup Bank Enable Setup Address Hold Bank Enable Hold Sym fMAX tKC tKH tKL tKQ tKQX tKQLZ tOEQ tOELZ tOEHZ tS tS tH tH 123456789012345678 Min Max 123456789012345678 123456789012345678 123456789012345678 200 123456789012345678 123456789012345678 123456789012345678 5.0 123456789012345678 123456789012345678 123456789012345678 123456789012345678 2 123456789012345678 123456789012345678 123456789012345678 2 123456789012345678 123456789012345678 123456789012345678 3 123456789012345678 123456789012345678 123456789012345678 123456789012345678 1.25 123456789012345678 123456789012345678 123456789012345678 0 123456789012345678 123456789012345678 123456789012345678 1.25 3 123456789012345678 123456789012345678 123456789012345678 0 123456789012345678 123456789012345678 123456789012345678 123456789012345678 2.5 123456789012345678 123456789012345678 123456789012345678 1.5 123456789012345678 123456789012345678 123456789012345678 1.5 123456789012345678 123456789012345678 123456789012345678 123456789012345678 0.5 123456789012345678 123456789012345678 123456789012345678 0.5 3.5ns Min Max 166 6.0 2.4 2.4 3.5 1.25 0 1.25 4 0 3.5 1.5 1.5 0.5 0.5 3.7ns Min Max 150 6.5 2.5 2.5 Min 4.0ns Max 133 7.0 3 3 3.7 1.25 0 1.25 0 4 4 1.25 0 1.25 0 3.5 1.8 1.8 0.5 0.5 5 4 2.0 2.0 0.5 0.5 Units MHz ns ns ns ns ns ns ns ns ns ns ns ns ns SYNC-BURST WRITE CYCLE PARAMETERS 3.0ns Description Frequency Clock Cycle Time Clock High Time Clock Low Time Address Setup Address Hold Bank Enable Setup Bank Enable Hold Global Write Enable Setup Global Write Enable Hold Data Setup Data Hold Sym fMAX tKC tKH tKL tS tH tS tH tS tH tS tH Min Max 1234567890123456789 1234567890123456789 1234567890123456789 1234567890123456789 200 1234567890123456789 1234567890123456789 1234567890123456789 5.0 1234567890123456789 1234567890123456789 1234567890123456789 2 1234567890123456789 1234567890123456789 1234567890123456789 2 1234567890123456789 1234567890123456789 1234567890123456789 1234567890123456789 1.5 1234567890123456789 1234567890123456789 1234567890123456789 0.5 1234567890123456789 1234567890123456789 1234567890123456789 1.5 1234567890123456789 1234567890123456789 1234567890123456789 1234567890123456789 0.5 1234567890123456789 1234567890123456789 1234567890123456789 1.5 1234567890123456789 1234567890123456789 1234567890123456789 0.5 1234567890123456789 1234567890123456789 1234567890123456789 1.5 1234567890123456789 1234567890123456789 1234567890123456789 1234567890123456789 0.5 5 3.5ns Min Max 166 6.0 2.4 2.4 1.5 0.5 1.5 0.5 1.5 0.5 1.5 0.5 3.7ns Min 6.5 2.7 2.7 1.8 0.5 1.8 0.5 1.8 0.5 1.8 0.5 Max 150 Min 7.0 3 3 2.0 0.5 1.8 0.5 2.0 0.5 2.0 0.5 4.0ns Max 133 Units MHz ns ns ns ns ns ns ns ns ns ns ns White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com WED2DG472512V-D2 FIG. 3 SYNC-BURST READ CYCLE tKC tKH tKL CLK tS ADSP tH ADSC tS Ax A1 A2 tH BWx, BWE, GW EM, E tS ADV tH G tOEQ tKQ tKQLZ DQx tKQ tOELZ Q(A1) Q(A2) Q(A2+2) Burst Read Single Read White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com Q(A2+1) 6 Q(A2+3) Q(A2) Q(A2+1) WED2DG472512V-D2 FIG. 4 SYNC-BURST WRITE CYCLE CLK tS ADSP tH ADSC tS A1 Ax A2 A3 tH BWx, BWE GW EM, E tS ADV tH G tOEHZ tKQX DQx Q D(A1) D(A2) D(A2+1) D(A2+1) Burst Write Single Write 7 D(A2+2) D(A2+3) D(A3) D(A3+1) D(A3+2) Burst Write White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com WED2DG472512V-D2 FIG. 5 SYNC-BURST READ/WRITE CYCLE CLK tS ADSP tH ADSC tS Ax A1 A2 A3 A4 A5 tH BWx, BWE, GW EM, E ADV G DQx Q(A1) Q(A2) Single Read White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com D(A3) Q(A4) Q(A4+1) Burst Read Single Write 8 Q(A4+2) D(A5) D(A5+1) Burst Write WED2DG472512V-D2 PACKAGE DIMENSIONS: 168 DUAL KEY DIMM 0.195 MAX. 5.255 MAX. 0.157 (2x) 195 1.500 MAX. 0.700 P1 0.078 (2X) 0.450 0.575 0.050 TYP. 0.250 1.450 0.350 0.925 0.225 MIN. 2.150 0.125 1.700 ALL DIMENSIONS ARE IN INCHES ORDERING INFORMATION Part Number WED2DG472512V5D2 Configuration Description Voltage (V) Frequency Package 16MB (4 x 512K x 72) Sync-Burst Pipeline 3.3 200MHz 168 Dual Key DIMM WED2DG472512V6D2 16MB (4 x 512K x 72) Sync-Burst Pipeline 3.3 166MHz 168 Dual Key DIMM WED2DG472512V65D2 16MB (4 x 512K x 72) Sync-Burst Pipeline 3.3 150MHz 168 Dual Key DIMM WED2DG472512V7D2 16MB (4 x 512K x 72) Sync-Burst Pipeline 3.3 133MHz 168 Dual Key DIMM 9 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com