NSC NM27P512V120

NM27P512
524,288-Bit (64K x 8) Processor Oriented
CMOS EPROM
General Description
Features
The NM27P512 is a 512K Processor Oriented EPROM configured as 64k x 8. It’s designed to simplify microprocessor
interfacing while remaining compatible with standard
EPROMs. It can reduce both wait states and glue logic
when the specification improvements are taken advantage
of in the system design. The NM27P512 is implemented in
National’s advanced CMOS EPROM process to provide excellent reliability and access times as fast as 120 ns.
The interface improvements address two areas to eliminate
the need for additional devices to adapt the EPROM to the
microprocessor and to eliminate wait states at the termination of the access cycle. Even with these improvements, the
NM27P512 remains compatible with industry standard
JEDEC pinout EPROMs. The maximum specification for output turn-off time has been reduced, eliminating the need for
wait states at the end of a read cycle. Also, the minimum
specification for output hold time has been increased, eliminating the need for external circuitry to hold the data.
Y
Y
Y
Y
Y
Fast output turn off to eliminate wait states
Extended data hold time for microprocessor
compatibility
High performance CMOS
Ð 120 ns access time
JEDEC standard pin configuration
Manufacturer’s identification code
Block Diagram
TL/D/11365 – 1
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
NSC800TM is a trademark of National Semiconductor Corporation.
C1995 National Semiconductor Corporation
TL/D/11365
RRD-B30M105/Printed in U. S. A.
NM27P512 524,288-Bit (64K x 8) Processor Oriented CMOS EPROM
December 1993
Connection Diagrams
27C080 27C040 27C020 27C010 27C256
DIP
NM27P512
A19 XX/VPP XX/VPP XX/VPP
A16
A16
A16
A16
A15
A15
A15
A15
VPP
A12
A12
A12
A12
A12
A7
A7
A7
A7
A7
A6
A6
A6
A6
A6
A5
A5
A5
A5
A5
A4
A4
A4
A4
A4
A3
A3
A3
A3
A3
A2
A2
A2
A2
A2
A1
A1
A1
A1
A1
A0
A0
A0
A0
A0
O0
O0
O0
O0
O0
O1
O1
O1
O1
O1
O2
O2
O2
O2
O2
GND
GND
GND
GND
GND
27C256
27C010
27C020
27C040
27C080
VCC
VCC
VCC
VCC
XX/PGM XX/PGM
A18
A18
VCC
XX
A17
A17
A17
A14
A14
A14
A14
A14
A13
A13
A13
A13
A13
A8
A8
A8
A8
A8
A9
A9
A9
A9
A9
A11
A11
A11
A11
A11
OE
OE
OE
OE
OE/VPP
A10
A10
A10
A10
A10
CE/PGM
CE
CE
CE/PGM CE/PGM
O7
O7
O7
O7
O7
O6
O6
O6
O6
O6
O5
O5
O5
O5
O5
O4
O4
O4
O4
O4
O3
O3
O3
O3
O3
TL/D/11365 – 2
Note: Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27P512 pins.
Commercial Temp Range (0§ C to a 70§ C)
Parameter/Order Number
Extended Temp Range (b40§ C to a 85§ C)
Access Time (ns)*
Parameter/Order Number
Access Time (ns)*
NM27P512 Q, N, V 120
120
NM27P512 QE, NE, VE 120
120
NM27P512 Q, N, V 150
150
NM27P512 QE, NE, VE 150
150
NM27P512 Q, N, V 200
200
NM27P512 QE, NE, VE 200
200
Note: Surface mount PLCC package available for commercial and extended
temperature ranges only.
Military Temp Range (b55§ C to a 125§ C)
Parameter/Order Number
Access Time (ns)*
NM27P512 QM 200
*All versions are guaranteed to function for slower speeds.
200
Package Types: NM27P512 Q, N, V XXX
Q e Quartz-Windowed Ceramic DIP Package
N e Plastic OTP DIP Package
V e PLCC Package
# All packages conform to the JEDEC standard.
PLCC
Pin Names
A0 – A15
Addresses
CE
Chip Enable
OE
Output Enable
O0 – O7
Outputs
PGM
Program
XX
Don’t Care (During Read)
TL/D/11365 – 3
2
Absolute Maximum Ratings (Note 1)
VCC Supply Voltage with
Respect to Ground
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature
b 65§ C to a 150§ C
All Input Voltages Except A9 with
Respect to Ground
VPP and A9 with Respect to Ground
b 0.6V to a 7V
ESD Protection
(MIL Std. 883, Method 3015.2)
All Output Voltages with
Respect to Ground
b 0.6V to a 7V
l 2000V
VCC a 1.0V to GND b0.6V
b 0.7V to a 14V
Operating Range
Range
Temperature
VCC
Tolerance
Comm’l
0§ C to a 70§ C
a 5V
g 10%
b 40§ C to a 85§ C
a 5V
g 10%
b 55§ C to a 125§ C
a 5V
g 10%
Industrial
Military
Read Operation
DC Electrical Characteristics
Symbol
Parameter
Test Conditions
Min
VIL
Input Low Level
b 0.5
VIH
Input High Level
2.0
VOL
Output Low Voltage
IOL e 2.1 mA
VOH
Output High Voltage
IOH e b2.5 mA
ISB1(10)
VCC Standby Current (CMOS)
CE e VCC g 0.3V
ISB2
VCC Standby Current
CE e VIH
ICC
VCC Active Current
CE e OE e VIL,
I/O e 0 mA
IPP
VPP Supply Current
VPP e VCC
VPP
VPP Read Voltage
ILI
Input Load Current
VIN e 5.5V or GND
ILO
Output Leakage Current
VOUT e 5.5V or GND
Max
Units
08
V
VCC a 1
V
0.4
3.5
V
V
f e 5 MHz
100
mA
1
mA
40
mA
10
mA
VCC b 0.7
VCC
V
b1
1
mA
b 10
10
mA
AC Electrical Characteristics
Symbol
120
Parameter
Min
150
Max
Min
200
Max
Min
Units
Max
tACC
Address to Output Delay
120
150
200
tCE
CE to Output Delay
120
150
200
tOE
OE to Output Delay
50
50
50
tDF(2)
Output Disable to Output Float
25
25
25
tCF(2)
Chip Disable to Output Float
30
30
30
tOH(2)
Output Hold from Addresses, CE
or OE, Whichever Occurred First
7
7
3
7
ns
Capacitance TA e a 25§ C, f e 1 MHz (Note 2)
Typ
Max
Units
CIN1
Symbol
Input Capacitance
except OE/VPP
VIN e 0V
6
12
pF
COUT
Output Capacitance
VOUT e 0V
9
12
pF
OE/VPP Input
Capacitance
VIN e 0V
20
25
pF
CIN2
Parameter
Conditions
AC Test Conditions
Output Load
Input Rise and Fall Times
Input Pulse Levels
1 TTL Gate and
CL e 100 pF (Note 8)
s 5 ns
0.45V to 2.4V
Timing Measurement Reference Level (Note 9)
Inputs
0.8V and 2V
Outputs
0.8V and 2V
AC Waveforms (Notes 6, 7)
TL/D/11365 – 4
Note 1: Stresses above those listed under ‘‘Absolute Maximum Ratings’’ may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: This parameter is only sampled and is not 100% tested.
Note 3: OE may be delayed up to tACC – tOE after the falling edge of CE without impacting tACC.
Note 4: The tDF and tCF compare level is determined as follows:
High to TRI-STATE, the measured VOH1 (DC) b 0.10V;
Low to TRI-STATE, the measured VOL1 (DC) a 0.10V.
Note 5: TRI-STATE may be attained using OE or CE.
Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 mF ceramic capacitor be used on
every device between VCC and GND.
Note 7: The outputs must be restricted to VCC a 1.0V to avoid latch-up and device damage.
Note 8: 1 TTL Gate: IOL e 1.6 mA, IOH e b 400 mA.
CL: 100 pF includes fixture capacitance.
Note 9: Inputs and outputs can undershoot to b 2.0V for 20 ns Max.
Note 10: CMOS inputs; VIL e GND g 0.3V, VIH e VCC g 0.3V.
4
Programming Characteristics (Notes 1 and 2)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tAS
Address Setup Time
1
tOES
OE Setup Time
1
ms
tDS
Data Setup Time
1
ms
tVCS
VCC Setup Time
1
ms
tAH
Address Hold Time
0
ms
tDH
Data Hold Time
tCF
Chip Enable to Output Float Delay
tPW
Program Pulse Width
tOEH
OE Hold Time
ms
1
OE e VIL
ms
0
95
100
60
ns
105
ms
1
ms
OE e VIL
tDV
Data Valid from CE
tPRT
OE Pulse Rise Time
during Programming
250
ns
tVR
VPP Recovery Time
IPP
VPP Supply Current during
Programming Pulse
ICC
VCC Supply Current
TR
Temperature Ambient
20
VCC
Power Supply Voltage
6
VPP
Programming Supply Voltage
12.5
12.75
13
tFR
Input Rise, Fall Time
VIL
Input Low Voltage
VIH
Input High Voltage
2.4
tIN
Input Timing Reference Voltage
0.8
2
V
tOUT
Output Timing Reference Voltage
0.8
2
V
50
ns
1
ms
CE e VIL
OE e VPP
30
mA
50
mA
25
30
§C
6.25
6.5
V
5
V
ns
0
0.45
4
V
V
Programming Waveforms
TL/D/11365 – 5
Note 1: National’s standard product warranty applies to devices programmed to specifications described herein.
Note 2: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The EPROM must not be inserted into or removed from a
board with voltage applied to VPP or VCC.
Note 3: The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V. Care must be taken when switching the VPP
supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 mF capacitor is required across VCC to GND to suppress spurious
voltage transients which may damage the device.
Note 4: Programming and program verify are tested with the fast Program Algorithm at typical power supply voltages and timings.
5
Fast Programming Algorithm Flow Chart
TL/D/11365 – 6
FIGURE 1
6
Functional Description
This assures that all deselected memory devices are in their
low power standby modes and that the output pins are active only when data is desired from a particular memory device.
DEVICE OPERATION
The six modes of operation of the EPROM are listed in Table I. It should be noted that all inputs for the six modes are
at TTL levels. The power supplies required are VCC and
OE/VPP. The OE/VPP power supply must be at 12.75V during the three programming modes, and must be at 5V in the
other three modes. The VCC power supply must be at 6.25V
during the three programming modes, and at 5V in the other
three modes.
Programming
CAUTION: Exceeding 14V on pin 22 (OE/VPP) will damage
the EPROM.
Initially, and after each erasure, all bits of the EPROM are in
the ‘‘1’s’’ state. Data is introduced by selectively programming ‘‘0’s’’ into the desired bit locations. Although only
‘‘0’s’’ will be programmed, both ‘‘1’s’’ and ‘‘0’s’’ can be presented in the data word. The only way to change a ‘‘0’’ to a
‘‘1’’ is by ultraviolet light erasure.
The EPROM is in the programming mode when the OE/VPP
is at 12.75V. It is required that at least a 0.1 mF capacitor be
placed across VCC to ground to suppress spurious voltage
transients which may damage the device. The data to be
programmed is applied 8 bits in parallel to the data output
pins. The levels required for the address and data inputs are
TTL.
Read Mode
The EPROM has two control functions, both of which must
be logically active in order to obtain data at the outputs.
Chip Enable (CE/PGM) is the power control and should be
used for device selection. Output Enable (OE/VPP) is the
output control and should be used to gate data to the output
pins, independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to
the delay from CE to output (tCE). Data is available at the
outputs tOE after the falling edge of OE, assuming that CE
has been low and addresses have been stable for at least
tACC – tOE.
When the address and data are stable, an active low, TTL
program pulse is applied to the CE/PGM input. A program
pulse must be applied at each address location to be programmed.
The EPROM is programmed with the Fast Programming Algorithm shown in Figure 1 . Each Address is programmed
with a series of 100 ms pulses until it verifies good, up to a
maximum of 25 pulses. Most memory cells will program with
a single 100 ms pulse.
The EPROM must not be programmed with a DC signal applied to the CE/PGM input.
Programming multiple EPROM in parallel with the same
data can be easily accomplished due to the simplicity of
the programming requirements. Like inputs of the parallel
EPROM may be connected together when they are programmed with the same data. A low level TTL pulse applied
to the CE/PGM input programs the paralleled EPROM.
Standby Mode
The EPROM has a standby mode which reduces the active
power dissipation by over 99%, from 385 mW to 0.55 mW.
The EPROM is placed in the standby mode by applying a
CMOS high signal to the CE/PGM input. When in standby
mode, the outputs are in a high impedance state, independent of the OE input.
Output Disable
The EPROM is placed in output disable by applying a TTL
high signal to the OE input. When in output disable all circuitry is enabled, except the outputs are in a high impedance state (TRI-STATE).
Output OR-Typing
Because the EPROM is usually used in larger memory arrays, National has provided a 2-line control function that
accommodates this use of multiple memory connections.
The 2-line control function allows for:
a) the lowest possible memory power dissipation, and
b) complete assurance that output bus contention will not
occur.
To most efficiently use these two control lines, it is recommended that CE/PGM be decoded and used as the primary
device selecting function, while OE/VPP be made a common connection to all devices in the array and connected to
the READ line from the system control bus.
Program Inhibit
Programming multiple EPROMs in parallel with different
data is also easily accomplished. Except for CE/PGM all
like inputs (including OE/VPP) of the parallel EPROMs may
be common. A TTL low level program pulse applied to an
EPROM’s CE/PGM input with OE/VPP at 12.75V will program that EPROM. A TTL high level CE/PGM input inhibits
the other EPROMs from being programmed.
7
Functional Description (Continued)
length of 2537Ð. The integrated dose (i.e., UV intensity c
exposure time) for erasure should be minimum of
15W-sec/cm2.
The EPROM should be placed within 1 inch of the lamp
tubes during erasure. Some lamps have a filter on their
tubes which should be removed before erasure. Table III
shows the minimum EPROM erasure time for various light
intensities.
An erasure system should be calibrated periodically. The
distance from lamp to device should be maintained at one
inch. The erasure time increase as the square of the distance from the lamp (if distance is doubled the erasure time
increases by factor of 4). Lamps lose intensity as they age.
When a lamp is changed, the distance has changed, or the
lamp has aged, the system should be checked to make certain full erasure is occurring. Incomplete erasure will cause
symptoms that can be misleading. Programmers, components, and even system designs have been erroneously
suspected when incomplete erasure was the problem.
Program Verify
A verify should be performed on the programmed bits to
determine whether they were correctly programmed. The
verify is accomplished with OE/VPP and CE at VIL. Data
should be verified TDV after the falling edge of CE.
AFTER PROGRAMMING
Opaque labels should be placed over the EPROM window
to prevent unintentional erasure. Covering the window will
also prevent temporary functional failure due to the generation of photo currents.
MANUFACTURER’S IDENTIFICATION CODE
The EPROM has a manufacturer’s identification code to aid
in programming. When the device is inserted in an EPROM
programmer socket, the programmer reads the code and
then automatically calls up the specific programming algorithm for the part. This automatic programming control is
only possible with programmers which have the capability of
reading the code.
The Manufacturer’s Identification code, shown in Table II,
specifically identifies the manufacturer and device type. The
code for NM27P512 is ‘‘8F85’’, where ‘‘8F’’ designates that
it is made by National Semiconductor, and ‘‘85’’ designates
a 512K part.
The code is accessed by applying 12V g 0.5V to address
pin A9. Addresses A1–A8, A10–A16, and all control pins
are held at VIL. Address pin A0 is held at VIL for the manufacturer’s code, and held at VIH for the device code. The
code is read on the eight data pins, O0 – O7. Proper code
access is only guaranteed at 25§ C g 5§ C.
SYSTEM CONSIDERATION
The power switching characteristics of EPROMs require
careful decoupling of the devices. The supply current, ICC,
has three segments that are of interest to the system designer: the standby current level, the active current level,
and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent of the output capacitance
loading of the device. The associated VCC transient voltage
peaks can be suppressed by properly selected decoupling
capacitors. It is recommended that at least a 0.1 mF ceramic
capacitor be used on every device between VCC and GND.
This should be a high frequency capacitor of low inherent
inductance. In addition, at least a 4.7 mF bulk electrolytic
capacitor should be used between VCC and GND for each
eight devices. The bulk capacitor should be located near
where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop
caused by the inductive effects of the PC board traces.
ERASURE CHARACTERISTICS
The erasure characteristics of the device are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms (Ð). It
should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000Ж4000Рrange.
The recommended erasure procedure for the EPROM is exposure to short wave ultraviolet light which has a wave-
8
Mode Selection
The modes of operation of the NM27P512 are listed in Table I. A single 5V power supply is required in the read mode. All inputs
are TTL levels excepts for VPP and A9 for device signature.
TABLE I. Mode Selection
Pins
Mode
CE/PGM
OE/VPP
VCC
Outputs
VIL
VIL
5.0V
DOUT
X
(Note 1)
VIH
5.0V
High Z
High Z
Read
Output Disable
Standby
VIH
X
5.0V
Programming
VIL
12.75V
6.25V
DIN
Program Verify
VIL
VIL
6.25V
DOUT
Program Inhibit
VIH
12.75V
6.25V
High Z
Note 1: X can be VIL or VIH.
TABLE II. Manufacturer’s Identification Code
A0
(10)
A9
(24)
07
(19)
06
(18)
05
(17)
04
(16)
03
(15)
02
(13)
01
(12)
00
(11)
Hex
Data
Manufacturer Code
VIL
12V
1
0
0
0
1
1
1
1
8F
Device Code
VIH
12V
1
0
0
0
0
1
0
1
85
Pins
9
10
Physical Dimensions inches (millimeters)
UV Window Cavity Dual-In-Line Cerdip Package (Q)
Order Number NM27P512Q
NS Package Number J28CQ
28-Lead Plastic One-Time-Programmable Dual-In-Line
Order Number NM27P512N
NS Package Number N28B
11
NM27P512 524,288-Bit (64K x 8) Processor Oriented CMOS EPROM
Physical Dimensions inches (millimeters) (Continued)
32-Lead Plastic Leaded Chip Carrier (PLCC)
Order Number NM27P512V
NS Package Number VA32A
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failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
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Corporation
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
Fax: 1(800) 737-7018
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
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effectiveness.
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