WED3DL324V 4Mx32 SDRAM FEATURES DESCRIPTION n 53% Space Savings vs. Monolithic Solution The WED3DL324V is a 4Mx32 Synchronous DRAM configured as 4x1Mx32. The SDRAM BGA is constructed with two 4Mx16 SDRAM die mounted on a multi-layer laminate substrate and packaged in a 119 lead, 14mm by 22mm, BGA. n Reduced System Inductance and Capacitance n Pinout and Footprint Compatible to SSRAM 119 BGA n 3.3V Operating Supply Voltage The WED3DL324V is available in clock speeds of 133MHz, 125MHz and 100MHz. The range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. n Fully Synchronous to Positive Clock Edge n Clock Frequencies of 133, 125 and 100MHz n Burst Operation Sequential or Interleave The package and design provides performance enhancements via a 50% reduction in capacitance vs. two monolithic devices. The design includes internal ground and power planes which reduces inductance on the ground and power pins allowing for improved decoupling and a reduction in system noise. Burst Length = Programmable 1, 2, 4, 8 or Full Page Burst Read and Write Multiple Burst Read and Single Write n Data Mask Control Per Byte n Auto and Self Refresh n Automatic and Controlled Precharge Commands n Suspend Mode and Power Down Mode n 119 Pin BGA, JEDEC MO-163 FIG. 1 PINOUT (TOP VIEW) PIN DESCRIPTION A0 A11 A 1 VDDQ 2 NC 3 BA0 4 NC 5 A10 6 A7 7 VDDQ A B C D E NC NC DQC DQC NC NC NC DQC NC/A12* BA1 VSS VSS CAS VDD NC CE A11 A9 VSS VSS NC A8 NC DQB NC NC DQB DQB B C D E F G H J VDDQ DQC DQC VDDQ DQC DQC DQC VDD VSS DQMC VSS NC RAS NC CKE VDD VSS DQMB VSS NC DQB DQB DQB VDD VDDQ DQB DQB VDDQ F G H J K L M N DQD DQD VDDQ DQD DQD DQD DQD DQD VSS DQMD VSS VSS CLK NC WE A1 VSS DQMA VSS VSS DQA DQA DQA DQA DQA DQA VDDQ DQA K L M N P R T U DQD NC NC VDDQ NC A6 NC NC VSS NC A5 NC A0 VDD A4 NC VSS NC A3 NC NC A2 NC NC DQA NC NC VDDQ P R T U 1 2 3 4 5 6 7 BA0-1 DQ Address Bus Bank Select Addresses Data Bus CLK Clock CKE Clock Enable DQM Data Input/Output Mask RAS Row Address Strobe CAS Column Address Strobe CE VDD VDDQ VSS Chip Enable Power Supply pins, 3.3V Data Bus Power Supply pins,3.3V Ground pins *NOTE: Pin B3 is designated as NC/A12. This pin is used for future density upgrades as address pin A12. Oct. 2001 Rev.0 ECO #14583 1 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com WED3DL324V FIG. 2 4MX32 SDRAM BLOCK DIAGRAM ADDR0-11 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 BA0 BA0 DQ0-7 BA1 BA1 DQ8-15 DQMA LDQM DQMB UDQM CE DQA DQB CS RAS RAS CAS CAS WE WE CLK CLK CKE CKE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 DQ0-31 DQ0-7 DQC DQ8-15 DQD BA0 BA1 DQMC LDQM DQMD UDQM CS RAS CAS WE CLK CKE White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com 2 Oct. 2001 Rev.0 ECO #14583 WED3DL324V INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol Type Signal Polarity CLK Input Pulse Positive Edge Function CKE Input Level Active High Activates the CLK signal when high and deactivates the CLK signal when low. By deactivating the clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode. The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. CE Input Pulse Active Low CE disable or enable device operation by masking or enabling all inputs except CLK, CKE and DQM. RAS, CAS WE Input Pulse Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the SDRAM. BA0,BA1 Input Level Selects which SDRAM bank is to be active. A0-11, A10/AP Input Level During a Bank Activate command cycle, A0-11 defines the row address (RA0-11) when sampled at the rising clock edge. During a Read or Write command cycle, A0-7 defines the column address (CA0-7) when sampled at the rising clock edge. In addition to the row address, A10/AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If A10/AP is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged . If A10/AP is low, autoprecharge is disabled. During a Precharge command cycle, A10/AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If A10/AP is high, all banks will be precharged regardless of the state of BA0, BA1. If A10/AP is low, then BA0, BA1 is used to define which bank to precharge. DQ Input/Output Level Data Input/Output are multiplexed on the same pins DQM Input Pulse Mask Active High VDD, VSS Supply Power and ground for the input buffers and the core logic. VDDQ Supply Isolated power and ground for the output buffers to improve noise immunity. The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the Write operation if DQM is high. ABSOLUTE MAXIMUM RATINGS Parameter Symbol Min Max Units Power Supply Voltage VDD/VDDQ -1.0 +4.6 V VIN -1.0 +4.6 V Output Voltage VOUT -1.0 +4.6 V Operating Temperature TOPR -0 +70 °C Storage Temperature TSTG -55 +125 °C Power Dissipation PD 1.5 W Short Circuit Output Current IOS 50 mA Input Voltage RECOMMENDED DC OPERATING CONDITIONS (Voltage Referenced to: VSS = 0V, T A = 0°C to +70°C) Parameter Supply Voltage Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Oct. 2001 Rev.0 ECO #14583 Symbol VDD/VDDQ Min 3.0 Typ 3.3 Max 3.6 Unit V Input High Voltage VIH 2.0 3.0 VDD +0.3 V Input Low Voltage VIL -0.3 0.8 V Output High Voltage (IOH = -2mA) VOH 2.4 V Output Low Voltage (IOL = 2mA) VOL 0.4 V Input Leakage Voltage IIL -5 5 µA Output Leakage Voltage IOL -5 5 µA CAPACITANCE (TA = 25°C, f = 1MHz, VDD = 3.3V) Parameter 3 Symbol Max Unit Input Capacitance C I1 4 pF Input/Output Capacitance (DQ) COut 5 pF White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com WED3DL324V OPERATING CURRENT CHARACTERISTICS (VCC = 3.3V, TA = 0°C to +70°C) Parameter Operating Current (One Bank Active) (1) Operating Current (Burst Mode) (1) Precharge Standby Current in Power Down Mode Symbol Conditions -7 -8 -10 Units ICC1 Burst Length = 1, tRC ³ tRC(min), IOL = 0mA 250 230 200 mA ICC4 Page Burst, 4 banks active, tCCD = 2 clocks 300 280 230 mA ICC2P CKE £ VIL(max), tCC = 15ns 2 2 2 mA ICC2PS CKE, CLK £ VIL(max), tCC = ¥, Inputs Stable 2 2 2 mA ICC1N CKE = VIH, tCC = 15ns Input Change one time every 30ns 160 160 160 mA ICC1NS CKE ³ VIH(min), tCC = ¥ No Input Change 120 120 120 mA ICC3P CKE £ VIL(max), tCC = 15ns 12 12 12 mA ICC3PS CKE £ VIL(max), tCC = ¥ 12 12 12 mA ICC3N CKE = VIH, tCC = 15ns Input Change one time every 30ns 120 120 120 mA Precharge Standby Current in Non-Power Down Mode Precharge Standby Current in Power Down Mode Active Standby Current in Non-Power Down Mode (One Bank Active) ICC3NS CKE ³ VIH(min), tCC = ¥, No Input Change 90 90 90 mA Refresh Current (2) ICC5 tRC ³ tRC(min) 460 420 400 mA Self Refresh Current ICC6 CKE £ 0.2V 6 6 6 mA NOTES: 1. Measured with outputs open. 2. Refresh period is 64ms. White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com 4 Oct. 2001 Rev.0 ECO #14583 WED3DL324V Mode RegisterDefinition A11 A10 11 10 A9 9 Reserved* WB A8 8 A6 A7 6 7 Op Mode A5 5 A4 A3 4 CAS Latency 1 2 BT A1 A2 3 Burst Definition 0 Mode Register(Mx) StartingColumn Address 2 Burst Length *Should program M11, M10 = “ 0, 0” to ensure compatibility with future devices. Burst Length M2 M1 M0 M3 = 0 M3 = 1 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Full Page Reserved 4 8 Burst Type M3 0 Sequential 1 Interleaved M6 M5 M4 Oct. 2001 Rev.0 ECO #14583 Burst Length AddressBus A0 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 3 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved M8 M7 M6-M0 OperatingMode 0 0 Defined StandardOperation - - - M9 Write Burst Mode 0 ProgrammedBurst Length 1 SingleLocationAccess Full Page (y) CAS Latency A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 A0 0 1 0 1 A0 0 1 0 1 0 1 0 1 n = A0-A9/8/7 (location0-y) Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1 1-0 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn + 1, Cn + 2 Cn + 3, Cn + 4... …Cn - 1, Cn… 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Not Supported All other states reserved 5 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com WED3DL324V SDRAM AC CHARACTERISTICS Symbol Parameter Clock Cycle Time (1) Clock to valid Output delay (1,2) Output Data Hold Time (2) Clock HIGH Pulse Width (3) Clock LOW Pulse Width (3) Input Setup Time (3) Input Hold Time (3) CLK to Output Low-Z (2) CLK to Output High-Z Row Active to Row Active Delay (4) RAS to CAS Delay (4) Row Precharge Time (4) Row Active Time (4) Row Cycle Time - Operation (4) Row Cycle Time - Auto Refresh (4,8) Last Data in to New Column Address Delay (5) Last Data in to Row Precharge (5) Last Data in to Burst Stop (5) Column Address to Column Address Delay (6) Data Out to High Impedance from Precharge CL = 3 CL = 2 tCC tCC t SAC t OH t CH tCL tSS tSH tSLZ t SHZ tRRD tRCD tRP t RAS tRC tRFC t CDL t RDL tBDL tCCD CL3 t ROH CL2 t ROH Min 7 7.5 133MHz Max 1000 1000 5.4 3 2.5 2.5 1.5 0.8 1.0 Min 8 10 125MHz Max 1000 1000 6 3 3 3 2 1 1 5.4 14 15 15 37 60 66 1 2 1 1.0 3 2 120,000 Min 10 12 Max 1000 1000 7 3 3 3 2 1 1.5 7 20 20 20 50 70 70 1 2 1 1.0 3 2 100MHz 120,000 7 20 20 20 50 80 80 1 2 1 1.5 3 2 120,000 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CLK CLK CLK CLK CLK NOTES: 1. Parameters depend on programmed CAS latency. 2. If clock rise time is longer than 1ns (t rise/2 -0.5)ns should be added to the parameter. 3. Assumed input rise and fall time = 1ns. If t rise of tfal l are longer than 1ns. [(t rise = t fall)/2] - 1ns should be added to the parameter. 4. The minimum number of clock cycles required is detemined by dividing the minimum time required by the clock cycle time and then rounding up to the next higher integer. 5. Minimum delay is required to complete write. 6. All devices allow every cycle column address changes. 7. In case of row precharge interrupt, auto precharge and read burst stop. 8. A new command may be given t RFC after self-refresh exit. White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com 6 Oct. 2001 Rev.0 ECO #14583 WED3DL324V COMMAND TRUTH TABLE CKE Previous Current Cycle Cycle Function Register Refresh Precharge CE RAS CAS WE DQM Mode Register Set H X L L L L X Auto Refresh (CBR) H H L L L H X Entry Self Refresh H L L L L H Single Bank Precharge H X L L H L Precharge all Banks H X L L H L BA A10/AP A9-0 A12, A11, Notes OP CODE X X X X X X X X BA L X X X H X 2 Bank Activate H X L L H H X BA Row Address 2 Write H X L H L L X BA L Column 2 Write with Auto Precharge H X L H L L X BA H Column 2 Read H X L H L L X BA L Column 2 Read with Auto Precharge H X L H L H X BA H Column 2 Burst Termination H X L H H L X X X X 3 No Operation H X L H H H X X X X Device Deselect H X H X X X X X X X Clock Suspend/Standby Mode L X X X X X X X X X 4 Data Write/Output Disable H X X X X X L X X X 5 Data Mask/Output Disable Power Down Mode H X X X X X H X X X 5 Entry X L H X X X X X X X 6 Exit X H H X X X X X X X 6 NOTES: 1. All of the SDRAM operations are defined by states of CE, WE, RAS, CAS, and DQM at the positive rising edge of the clock. 2. Bank Select (BA), if BA = 0 then bank A is selected, if BA = 1 then bank B is selected. 3. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency. 4. During normal access mode, CKE is held high and CLK is enabled. When it is low, it freezes the internal clock and extends data Read and Write operations. One clock delay is required for mode entry and exit. 5. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the data outputs are disabled and become high impedance after a two clock delay. DQM also provides a data mask function for Write cycles. When it activates, the Write operation at the clock is prohibited (zero clock latency). All banks must be precharged before entering the Power Down Mode. The Power Down Mode does not preform any Refresh operations, therefore the device cant remain in this mode longer than the Refresh period (tREF) of the device. One clock delay is required for mode entry and exit. Oct. 2001 Rev.0 ECO #14583 7 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com WED3DL324V CLOCK ENABLE (CKE0 ) TRUTH TABLE Current State Self Refresh Power Down All Banks Idle Any State other than listed above CKE Previous Current Cycle Cycle Command CE RAS CAS WE BA0-1 A10-11 Action Notes H X X X X X X X INVALID 1 L H H X X X X X Exit Self Refresh with Device Deselect 2 L H L H H H X X Exit Self Refresh with No Operation 2 L H L H H L X X ILLEGAL 2 L H L H L X X X ILLEGAL 2 L H L L X X X X ILLEGAL 2 Maintain Self Refresh L L X X X X X X H X X X X X X X INVALID 1 L H H X X X X X Power Down Mode exit, all banks idle 2 X L H L X X X X H X L H L L X H H H X X X H H L H X X H H L L H X H H L L L H H H L L L L H L H X X X H L L H X X H L L L H X H L L L L H H H L L L L L X X X X X X X Power Down H H X X X X X X Refer to the Operations in the Current State Truth Table X X OP Code X X OP Code ILLEGAL 2 Maintain Power Down Mode 2 Refer to the Idle State section of the Current State Truth Table 3 CBR Refresh Mode Register Set 4 Refer to the Idle State section of the Current State Truth Table 3 Entry Self Refresh 4 Mode Register Set H L X X X X X X Begin Clock Suspend next cycle L H X X X X X X Exit Clock Suspend next cycle L L X X X X X X Maintain Clock Suspend 4 5 NOTES: 1. For the given Current State CKE must be low in the previous cycle. 2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE ( tCKS) must be satisfied before any command other than Exit is issued. 3. The address inputs (A11-A 0) depend on the command that is issued. See the Idle State section of the Current State Truth Table for more information. 4. The Power Down Mode, Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle state. Must be a legal command as defined in the Current State Truth Table. White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com 8 Oct. 2001 Rev.0 ECO #14583 WED3DL324V CURRENT STATE TRUTH TABLE Current State Idle Row Active Read Write Read with Auto Precharge Oct. 2001 Rev.0 ECO #14583 Command WE BA0-1 A11, A10/AP-A0 OP Code Action CE RAS CAS L L L L L L L H L L H L X X Precharge No Operation L L H H BA Row Address Bank Activate Activate the specified bank and row X X Description Notes Mode Register Set Set the Mode Register 2 Auto orSelf Refresh Start Auto orSelf Refresh 2,3 L H L L BA Column Write w/o Precharge ILLEGAL 4 L H L H BA Column Read w/o Precharge ILLEGAL 2 L H H L X X Burst Termination No Operation 2 L H H H X X No Operation No Operation H X X X X X Device Deselect No Operation or Power Down L L L L Mode Register Set ILLEGAL L L L H X X Auto orSelf Refresh ILLEGAL L L H L X X Precharge Precharge L L H H BA Row Address Bank Activate ILLEGAL 2 L H L L BA Column Write Start Write; Determine if Auto Precharge 7,8 L H L H BA Column Read Start Read; Determine if Auto Precharge 7,8 L H H L X X Burst Termination No Operation OP Code 5 6 L H H H X X No Operation No Operation H X X X X X Device Deselect No Operation L L L L L L L H L L H L X L L H H BA L H L L BA Column L H L H BA L H H L X L H H H X H X X X X L L L L L L L H L L H L X L L H H BA L H L L BA Column L H L H BA L H H L X L H H H X H X X X X L L L L L L L H L L H L X X Precharge ILLEGAL 4 L L H H BA Row Address Bank Activate ILLEGAL 4 L H L L BA Column Write ILLEGAL L H L H BA Column Read ILLEGAL L H H L X X Burst Termination ILLEGAL L H H H X X No Operation Continue the Burst H X X X X X Device Deselect Continue the Burst OP Code Mode Register Set ILLEGAL Auto orSelf Refresh ILLEGAL X Precharge Terminate Burst; Start the Precharge Row Address Bank Activate ILLEGAL 4 Write Terminate Burst; Start the Write cycle 8,9 Column Read Terminate Burst; Start a new Read cycle 8,9 X Burst Termination Terminate the Burst X No Operation Continue the Burst Device Deselect Continue the Burst X X X OP Code Mode Register Set ILLEGAL Auto orSelf Refresh ILLEGAL X Precharge Terminate Burst; Start the Precharge Row Address Bank Activate ILLEGAL 4 Write Terminate Burst; Start a new Write cycle 8,9 Column Read Terminate Burst; Start the Read cycle 8,9 X Burst Termination Terminate the Burst X No Operation Continue the Burst Device Deselect Continue the Burst X X X OP Code X X 9 Mode Register Set ILLEGAL Auto orSelf Refresh ILLEGAL White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com WED3DL324V CURRENT STATE TRUTH TABLE (cont.) Current State Write with Auto Precharge Precharging Row Activating Write Recovering Write Recovering with Auto Precharge Command WE BA0-1 A11, A10/AP-A0 OP Code Description Action Notes CE RAS CAS L L L L L L L H L L H L X X Precharge ILLEGAL 4 L L H H BA Row Address Bank Activate ILLEGAL 4 L H L L BA Column Write ILLEGAL L H L H BA Column Read ILLEGAL L H H L X X Burst Termination ILLEGAL X X Mode Register Set ILLEGAL Auto orSelf Refresh ILLEGAL L H H H X X No Operation Continue the Burst H X X X X X Device Deselect Continue the Burst L L L L L L L H L L H L X L L H H BA L H L L BA L H L H L H H L OP Code Mode Register Set ILLEGAL Auto orSelf Refresh ILLEGAL X Precharge No Operation; Bank(s) idle after tRP Row Address Bank Activate ILLEGAL 4 Column Write w/o Precharge ILLEGAL 4 BA Column Read w/o Precharge ILLEGAL 4 X X Burst Termination No Operation; Bank(s) idle after tRP X X L H H H X X No Operation No Operation; Bank(s) idle after tRP H X X X X X Device Deselect No Operation; Bank(s) idle after tRP L L L L L L L H L L H L X X Precharge ILLEGAL 4 L L H H BA Row Address Bank Activate ILLEGAL 4,10 L H L L BA Column Write ILLEGAL 4 L H L H BA Column Read ILLEGAL 4 L H H L X X Burst Termination No Operation; Row active after tRCD L H H H X X No Operation No Operation; Row active after tRCD H X X X X Device Deselect No Operation; Row active after tRCD L L L L L L L H L L H L X X Precharge ILLEGAL 4 L L H H BA Row Address Bank Activate ILLEGAL 4 L H L L BA Column Write Start Write; Determine if Auto Precharge 9 L H L H BA Column Read Start Read; Determine if Auto Precharge 9 L H H L X X Burst Termination No Operation; Row active after tDPL L H H H X X No Operation No Operation; Row active after tDPL H X X X X Device Deselect No Operation; Row active after tDPL L L L L L L L H L L H L X X Precharge ILLEGAL L L H H BA Row Address Bank Activate ILLEGAL 4 L H L L BA Column Write ILLEGAL 4,9 4,9 OP Code X X X OP Code X X X OP Code X X Mode Register Set ILLEGAL Auto orSelf Refresh ILLEGAL Mode Register Set ILLEGAL Auto orSelf Refresh ILLEGAL Mode Register Set ILLEGAL Auto orSelf Refresh ILLEGAL L H L H BA Column Read ILLEGAL L H H L X X Burst Termination No Operation; Precharge after tDPL L H H H X X No Operation No Operation; Precharge after tDPL H X X X X X Device Deselect No Operation; Precharge after tDPL White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com 10 4 Oct. 2001 Rev.0 ECO #14583 WED3DL324V CURRENT STATE TRUTH TABLE (cont.) Current State Refreshing Mode Register Accessing Command CE RAS CAS WE BA0-1 A11, A10/AP-A0 OP Code Description Action L L L L L L L H L L H L X X Precharge ILLEGAL L L H H BA Row Address Bank Activate ILLEGAL L H L L BA Column Write ILLEGAL L H L H BA Column Read ILLEGAL L H H L X X Burst Termination No Operation; Idle after tRC L H H H X X No Operation No Operation; Idle after tRC H X X X X L L L L L L L H X L L H L L L H H X X X Mode Register Set ILLEGAL Auto orSelf Refresh ILLEGAL Device Deselect No Operation; Idle after tRC Mode Register Set Load mode register X Auto orSelf Refresh ILLEGAL X X Precharge ILLEGAL BA Row Address Bank Activate ILLEGAL ILLEGAL OP Code L H L L BA Column Write L H L H BA Column Read ILLEGAL L H H L X X Burst Termination ILLEGAL L H H H X X No Operation No Operation; Idle after two clock cycles H X X X X X Device Deselect No Operation; Idle after two clock cycles Notes NOTES: 1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the command is being applied to. 2. Both Banks must be idle otherwise it is an illegal action. 3. If CKE is active (high) the SDRAM starts the Auto (CBR) Refresh operation, if CKE is inactive (low) then the Self Refresh mode is entered. 4. The Current State refers only refers to one of the banks, if BA selects this bank then the action is illegal. If BA selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank. 5. If CKE is inactive (low) than the Power Down mode is entered, otherwise there is a No Operation. 6. The minimum and maximum Active time (tRAS) must be satisfied. 7. The RAS to CAS Delay (tRCD ) must occur before the command is given. 8. Address A10 is used to determine if the Auto Precharge function is activated. 9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. The command is illegal if the minimum bank to bank delay time (tRRD ) is not satisfied. Oct. 2001 Rev.0 ECO #14583 11 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com WED3DL324V FIG. 3 SINGLE BIT READ-WRITE CYCLE (SAME PAGE) @CAS LATENCY=3, BURST LENGTH=1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK t CH t CC t CL HIGH CKE t RCD t RAS CE t SS t RCD t SS t SH t RP t SH RAS t SS t CCD t SH CAS t SS ADDR t SS t SH t SH Ra Ca Cb Cc Rb Note 2 Note 2, 3 Note 2, 3 BA BS BS BS BS BS BS A10/AP Ra Note 3 Note 3 Note 3 Note 4 Rb t RAC t SS t SAC Qa DQ t SLZ t OH Note 2, 3 Note 4 Note 2 t SH Db Qc t SS t SH t SS t SH WE DQM Row Active Read Write Read Row Active Precharge NOTES: 1. All input except CKE & DQM can be don't care when CE is high at the CLK high going edge. 2. Bank active & read/write are controlled by BA0~BA1. BA0 BA1 Active & Read/Write 0 0 Bank A 0 1 Bank B 1 0 Bank C 1 1 Bank D 3. Enable and disable auto precharge function are controlled by A10/AP in read/write command. A10/AP BA0 0 0 0 1 1 0 0 1 1 1 4. A10/AP and BA0~BA1 control bank precharge when precharge command is asserted. A10/AP 0 0 0 0 1 BA0 0 0 1 1 x BA1 0 1 0 1 x Precharge Bank A Bank B Bank C Bank D All Banks White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com DON'T CARE 12 BA1 0 1 0 1 0 1 0 1 Operation Distribute auto precharge, leave bank A active at end of burst. Disable auto precharge, leave bank B active at end of burst. Disable auto precharge, leave bank C active at end of burst. Disable auto precharge, leave bank D active at end of burst. Enable auto precharge, precharge bank A at end of burst. Enable auto precharge, precharge bank B at end of burst. Enable auto precharge, precharge bank C at end of burst. Enable auto precharge, precharge bank D at end of burst. Oct. 2001 Rev.0 ECO #14583 WED3DL324V FIG. 4 POWER UP SEQUENCE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK CKE High level is necessary CE t RFC t RP t RFC RAS CAS Key ADDR RAa BA RAa A10/AP HIGH-Z DQ WE DQM High level is necessary Precharge (All Banks) Auto Refresh Auto Refresh Mode Register Set Row Active (A-Bank) DON'T CARE Oct. 2001 Rev.0 ECO #14583 13 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com WED3DL324V FIG. 5 READ & WRITE CYCLE AT SAME BANK @BURST LENGTH=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE Note 1 t RC CE t RCD RAS Note 2 CAS ADDR Ra Ca0 Rb Cb0 BA A10/AP Ra Rb t SHZ t RAC Note 3 Qa0 Qa1 t RAC DQ Note 3 Qa2 Qa3 Db0 t SHZ t OH t SAC Qa0 CL = 3 t RDL t OH t SAC CL = 2 Note 4 Qa1 Qa2 Db1 Db2 Note 4 Qa3 Db3 t RDL Db0 Db1 Db2 Db3 WE DQM Row Active (A-Bank) Read (A-Bank) Precharge (A-Bank) Row Active (A-Bank) Write (A-Bank) Precharge (A-Bank) DON'T CARE NOTES: 1. Minimum row cycle times are required to complete internal DRAM operation. 2. Row precharge can interrupt burst on any cycle. (CAS Latency - 1) number of valid output data is available after Row precharge. Last valid output will be Hi-Z(tSHZ) after the clock. 3. Access time from Row active command. tCC *(tRCD + CAS latency - 1) + tSAC. 4. Output will be Hi-Z after the end of burst (1, 2, 4, 8 & full page bit burst). White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com 14 Oct. 2001 Rev.0 ECO #14583 WED3DL324V FIG. 6 PAGE READ & WRITE CYCLE AT SAME BANK @BURST LENGTH=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE CE t RCD RAS Note 2 CAS ADDR Ra Ca0 Cb0 Cc0 Cd0 BA A10/AP Ra t RDL Qa0 CL = 2 Qa1 Qb0 Qb1 Qb2 Dc0 DQ Dc1 Dd0 Dd1 t CDL Qa0 CL = 3 Qa1 Qb0 Qb1 Dc0 Dc1 Dd0 Dd1 WE Note 1 Note 3 DQM Row Active (A-Bank) Read (A-Bank) Read (A-Bank) Write (A-Bank) Write (A-Bank) Precharge (A-Bank) DON'T CARE NOTES: 1. To write data before burst read ends, DQM should be asserted three cycles prior to write command to avoid bus contention. 2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written. 3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. Oct. 2001 Rev.0 ECO #14583 15 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com WED3DL324V FIG. 7 PAGE READ CYCLE AT DIFFERENT BANK @BURST LENGTH=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE Note 1 CE RAS Note 2 CAS ADDR RAa CAa RBb CBb CAc CBd CAe BA A10/AP RAa RBb QAa0 CL = 2 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 DQ CL = 3 QBb2 QAe1 WE DQM Row Active (A-Bank) Row Active (B-Bank) Read (B-Bank) Read (A-Bank) Read (A-Bank) Read (B-Bank) Read (A-Bank) Precharge (A-Bank) DON'T CARE NOTES: 1. CE can be don't care when RAS, CAS and WE are high at the clock high going edge. 2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same. White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com 16 Oct. 2001 Rev.0 ECO #14583 WED3DL324V FIG. 8 PAGE WRITE CYCLE AT DIFFERENT BANK @BURST LENGTH=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE CE RAS Note 2 CAS ADDR RAa CAa RBb CBb CAc CBd BA A10/AP RAa RBb t CDL DAa0 DQ DAa1 DAa2 DAa3 DBb0 t RDL DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 DBd1 WE Note 1 DQM Row Active (A-Bank) Row Active (B-Bank) Write (B-Bank) Write (A-Bank) Write (A-Bank) Write (B-Bank) Precharge (Both Banks) DON'T CARE NOTES: 1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data. 2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same. Oct. 2001 Rev.0 ECO #14583 17 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com WED3DL324V FIG. 9 READ & WRITE CYCLE AT DIFFERENT BANK @BURST LENGTH=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 QAc0 QAc1 QAc2 QAc0 QAc1 CLOCK HIGH CKE CE RAS CAS ADDR RAa RBb CAa CBb RAc CAc BA A10/AP RAa RBb RAc t CDL QAa0 CL = 2 QAa1 QAa2 QAa3 QAa0 QAa1 QAa2 DBb0 DBb1 DBb2 DBb3 DBb0 DBb1 DBb2 DBb3 Note 1 DQ CL = 3 QAa3 WE DQM Row Active (A-Bank) Read (A-Bank) Precharge (A-Bank) Write (B-Bank) Row Active (B-Bank) Row Active (A-Bank) Read (A-Bank) DON'T CARE NOTE: 1. tCDL should be met to complete write. White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com 18 Oct. 2001 Rev.0 ECO #14583 WED3DL324V FIG. 10 READ & WRITE CYCLE WITH AUTO PRECHARGE @BURST LENGTH=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE CE RAS CAS ADDR Ra Rb Ra Rb Ca Cb BA A10/AP Qa0 CL = 2 Qa1 Qa2 Qa3 Qa0 Qa1 Qa2 Db0 Db1 Db2 Db3 Db0 Db1 Db2 Db3 DQ CL = 3 Qa3 WE DQM Row Active (A-Bank) Read with Auto Precharge (A-Bank) Row Active (B-Bank) Auto Precharge Start Point (A-Bank) Write with Auto Precharge (B-Bank) Auto Precharge Start Point (B-Bank) DON'T CARE NOTE: 1. tCDL should be controlled to meet minimum tRAS before internal precharge start. (in the case of Burst Length=1 & 2 and BRSW mode) Oct. 2001 Rev.0 ECO #14583 19 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com WED3DL324V FIG. 11 CLOCK SUSPENSION & DQM OPERATION CYCLE @CAS LATENCY=2, BURST LENGTH=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK CKE CE RAS CAS ADDR Ra Ca Cb Cc BA A10/AP Ra t SHZ Qa0 DQ Qa1 Qa2 t SHZ Qa3 Qb1 Qb1 Dc0 Dc2 WE Note 1 DQM Row Active Read Clock Suspension Read Write DQM Read DQM Write Write DQM Clock Suspension DON'T CARE NOTE: 1. DQM is needed to prevent bus contention. White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com 20 Oct. 2001 Rev.0 ECO #14583 WED3DL324V FIG. 12 READ INTERRUPTED BY PRECHARGE COMMAND & READ BURST STOP @BURST LENGTH=FULL PAGE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 QAb0 QAb1 QAb2 QAb3 QAb4 QAb5 QAb0 QAb1 QAb2 QAb3 QAb4 19 CLOCK HIGH CKE CE RAS CAS ADDR RAa CAa CAb BA A10/AP RAa Note 2 QAa0 CL = 2 1 QAa1 QAa2 QAa3 QAa4 QAa0 QAa1 QAa2 QAa3 1 DQ 2 CL = 3 2 QAa4 QAb5 WE DQM Row Active (A-Bank) Read (A-Bank) Burst Stop Read (A-Bank) Precharge (A-Bank) DON'T CARE NOTES: 1. At full page mode, burst is end at the end of burst. So auto precharge is possible. 2. About the valid DQs after burst stop, it is same as the case of RAS interrupt. Both cases are illustrated in above timing diagram. See the label 1, 2. But at burst write, Burst stop and RAS interrupt should be compared carefully. Refer to the timing diagram of "Full page write burst stop cycle." 3. Burst stop is valid at every burst length. Oct. 2001 Rev.0 ECO #14583 21 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com WED3DL324V FIG. 13 WRITE INTERRUPTED BY PRECHARGE COMMAND & WRITE BURST STOP CYCLE @BURST LENGTH=FULL PAGE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE CE RAS CAS ADDR RAa CAa CAb BA A10/AP RAa t BDL t RDL Note 2 DAa0 DQ DAa1 DAa2 DAa3 DAa4 DAb0 DAb1 DAb2 DAb3 DAb4 DAb5 WE DQM Row Active (A-Bank) Write (A-Bank) Burst Stop Write (A-Bank) Precharge (A-Bank) DON'T CARE NOTES: 1. At full page mode, burst is end at the end of burst. So auto precharge is possible. 2. Data-in at the cycle of interrupted by precharge cannot be written into the corresponding memory cell. It is defined by AC parameter of tRDL. DQM at write interrupted by precharge command is needed to prevent invalid write. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 3. Burst stop is valid at every burst length. White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com 22 Oct. 2001 Rev.0 ECO #14583 WED3DL324V FIG. 14 BURST READ SINGLE BIT WRITE CYCLE @BURST LENGTH=2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 QAd0 QAd1 19 CLOCK Note 1 HIGH CKE CE RAS Note 2 CAS ADDR RAa CAa RBb CAb RAc CBc CAd BA A10/AP RAa RBb DAa0 CL = 2 RAc QAb0 QAb1 DBc0 DQ DAa0 CL = 3 QAb0 QAb1 DBc0 QAd0 QAd1 WE DQM Row Active (A-Bank) Row Active (B-Bank) Write (A-Bank) Row Active (A-Bank) Read with Auto Precharge (A-Bank) Read (A-Bank) Write with Auto Precharge (B-Bank) Precharge (Both Banks) DON'T CARE NOTES: 1. BRSW mode is enabled by setting A9 "High" at MRS (Mode Register Set). At the BRSW Mode, the burst length at write is fixed to "1" regardless of programmed burst length. 2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command, the next cycle starts the precharge. Oct. 2001 Rev.0 ECO #14583 23 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com WED3DL324V FIG. 15 ACTIVE/PRECHARGE POWER DOWN MODE @CAS LATENCY=2, BURST LENGTH=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK Note 2 t SS t SS CKE t SS Note 1 Note 3 CE RAS CAS Ra ADDR Ca BA Ra A10/AP t SHZ Qa0 DQ Qa1 Qa2 WE DQM Precharge Power-Down Entry Row Active Read Precharge Active Power-Down Power-Down Exit Entry Active Power-Down Exit Precharge DON'T CARE NOTES: 1. Both banks should be in idle state prior to entering precharge power down mode. 2. CKE should be set high at least 1 CLK + tSS prior to Row active command. 3. Cannot violate minimum refresh specification (64ms). White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com 24 Oct. 2001 Rev.0 ECO #14583 WED3DL324V FIG. 16 SELF REFRESH ENTRY & EXIT CYCLE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK t SS CKE Note 2 t RFC min Note 3 Note 1 Note 6 Note 4 Note 5 CE RAS Note 7 CAS ADDR BA A10/AP DQ HI-Z HI-Z WE DQM Self Refresh Entry Self Refresh Exit Auto Refresh DON'T CARE NOTES: TO ENTER SELF REFRESH MODE 1. CE, RAS & CAS with CKE should be low at the same clock cycle. 2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE. 3. The device remains in self refresh mode as long as CKE stays "Low." Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh. TO EXIT SELF REFRESH MODE 4. System clock restart and be stable before returning CKE high. 5. CE starts from high. 6. Minimum tRFC is required after CKE going high to complete self refresh exit. 7. 4K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh. Oct. 2001 Rev.0 ECO #14583 25 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com WED3DL324V FIG. 17 FIG. 18 MODE REGISTER SET CYCLE 0 1 2 3 4 5 6 7 8 0 1 AUTO REFRESH CYCLE 2 3 4 5 6 7 8 9 10 CLOCK HIGH HIGH CKE CE Note 2 t RFC RAS Note 1 CAS Note 3 Key ADDR DQ Ra HI-Z HI-Z WE DQM MRS New Command Auto Refresh New Command DON'T CARE NOTES: Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle. MODE REGISTER SET CYCLE 1. CE, RAS, CAS, & WE activation at the same clock cycle with address key will set internal mode register. 2. Minimum 2 clock cycles should be met before new RAS activation. 3. Please refer to Mode Register Set table. White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com 26 Oct. 2001 Rev.0 ECO #14583 WED3DL324V PACKAGE DESCRIPTION 2.79 (0.110) MAX 7.62 (0.300) TYP 14.00 (0.551) TYP R 1.52 (0.060) MAX (4x) A A1 CORNER B C D E F 1.27 (0.050) TYP G 20.32 (0.800) TYP H 22.00 (0.866) TYP J K L M N P R T U 0.711 (0.028) MAX 1.27 (0.050) TYP ORDERING INFORMATION PART NUMBER CLOCK FREQUENCY WED3DL324V7BC 133MHZ 119 BGA WED3DL324V8BC 125MHZ 119 BGA WED3DL324V10BC 100MHZ 119 BGA Oct. 2001 Rev.0 ECO #14583 27 PACKAGE White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com