WF2M16-XXX5 HI-RELIABILITY PRODUCT 2Mx16 FLASH MODULE, SMD 5962-97610 PRELIMINARY* FEATURES ■ Data Polling and Toggle Bit feature for detection of program or erase cycle completion. ■ Access Times of 90, 120, 150ns ■ Packaging: • 56 lead, Hermetic Ceramic, 0.520" CSOP (Package 207). Fits standard 56 SSOP footprint. ■ Supports reading or programming data to a sector not being erased. ■ Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation. • 44 pin Ceramic SOJ (Package 102)** • 44 lead Ceramic Flatpack (Package 208)** ■ Sector Architecture • 32 equal size sectors of 64KBytes each • Any combination of sectors can be erased. Also supports full chip erase. ■ Minimum 100,000 Write/Erase Cycles Minimum ■ Organized as 2Mx16; User Configurable as 2 x 2Mx8 ■ Commercial, Industrial, and Military Temperature Ranges ■ 5 Volt Read and Write. 5V ± 10% Supply. ■ Low Power CMOS FIG. 1 ■ RESET pin resets internal state machine to the read mode. ■ Ready/Busy (RY/BY) output for detection of program or erase cycle completion. ■ Multiple Ground Pins for Low Noise Operation * This data sheet describes a product under development, not fully characterized, and is subject to change without notice. * * Package to be developed. Note: For programming information refer to Flash Programming 16M5 Application Notes. PIN CONFIGURATIONS WF2M16-XDAX5 56 CSOP TOP VIEW CS1 A12 A13 A14 A15 NC CS2 NC A20 A19 A18 A17 A16 VCC GND I/O6 I/O14 I/O7 I/O15 RY/BY OE WE NC I/O13 I/O5 I/O12 I/O4 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 NC RESET A11 A10 A9 A1 A2 A3 A4 A5 A6 A7 GND A8 VCC I/O9 I/O1 I/O8 I/O0 A0 NC NC NC I/O2 I/O10 I/O3 I/O11 GND PIN DESCRIPTION WF2M16-XXX5 44 CSOJ (DL)** 44 FLATPACK (FL)** TOP VIEW A15 A14 A13 A12 A11 A10 A9 A8 RESET CS1 VCC VSS CS2 RY/BY A7 A6 A5 A4 A3 A2 A1 A0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A16 A17 A18 A19 A20 OE I/O7 I/O6 I/O5 I/O4 VSS VCC I/O3 I/O2 I/O1 I/O0 WE NC NC NC NC NC I/O0-15 Data Inputs/Outputs A0-20 Address Inputs WE Write Enable CS1-2 Chip Select OE Output Enable VCC Power Supply VSS Ground RY/BY Ready/Busy RESET Reset BLOCK DIAGRAM I/O0-7 I/O8-15 RESET WE OE A0-20 RY/BY 2M x 8 2M x 8 ** Package to be developed. CS1 CS2 NOTE: 1. RY/BY is an open drain output and should be pulled up to Vcc with an external resistor. 2. Address compatible with Intel 2M8 56 SSOP. August 2001 Rev. 4 1 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WF2M16-XXX5 CAPACITANCE (T A = +25°C) ABSOLUTE MAXIMUM RATINGS Parameter Voltage on Any Pin Relative to VSS Power Dissipation Storage Temperature Short Circuit Output Current Data Retention (Mil Temp) Endurance - write/erase cycles (Mil Temp) Symbol Ratings Unit VT PT Tstg IOS -2.0 to +7.0 8 -65 to +125 100 20 100,000 min. V W °C mA years cycles Parameter Max Unit OE capacitance Symbol COE VIN = 0 V, f = 1.0 MHz Conditions 25 pF WE capacitance CWE VIN = 0 V, f = 1.0 MHz 25 pF CS capacitance CCS VIN = 0 V, f = 1.0 MHz 15 pF Data I/O capacitance CI/O VI/O = 0 V, f = 1.0 MHz 15 pF Address input capacitance CAD VIN = 0 V, f = 1.0 MHz 25 pF This parameter is guaranteed by design but not tested. RECOMMENDED DC OPERATING CONDITIONS Parameter Symbol Min Typ Max Supply Voltage V CC 4.5 5.0 5.5 Unit V Ground V SS 0 0 0 V Input High Voltage V IH 2.0 - V CC + 0.5 V Input Low Voltage V IL -0.5 - +0.8 V Operating Temperature (Mil.) TA -55 - +125 °C Operating Temperature (Ind.) TA -40 - +85 °C DC CHARACTERISTICS - CMOS COMPATIBLE (VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C) Parameter Max Unit Input Leakage Current Symbol I LI V CC = 5.5, V IN = GND to VCC Conditions Min 10 µA Output Leakage Current I LO V CC = 5.5, V IN = GND to VCC 10 µA VCC Active Current for Read (1) ICC1 CS = VIL, OE = VIH, f = 5MHz 80 mA V CC Active Current for Program or Erase (2) I CC2 CS = VIL, OE = VIH 120 mA V CC Standby Current I CC3 V CC = 5.5, CS = V IH , f = 5MHz, RESET = Vcc ± 0.3V 4.0 mA Output Low Voltage V OL I OL = 12.0 mA, V CC = 4.5 Output High Voltage V OH I OH = -2.5 mA, V CC = 4.5 Low V CC Lock-Out Voltage V LKO 0.45 0.85xV cc 3.2 V V 4.2 V NOTES: 1. The Icc current listed includes both the DC operating current and the frequency dependent component (@ 5MHz). The frequency component typically is less than 2mA/MHz, with OE at VIH . 2. Icc active while Embedded Algorithm (program or erase) is in progress. 3. DC test conditions VIL = 0.3V, VIH = V CC - 0.3V White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 2 WF2M16-XXX5 AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS - WE CONTROLLED (VCC = 5.0V, T A = -55°C to +125°C) Parameter Symbol -90 Min Write Cycle Time tAVAV tWC -120 Max 90 Min -150 Max 120 Min Unit Max 150 ns Chip Select Setup Time tELWL tCS 0 0 0 ns Write Enable Pulse Width tWLWH tWP 45 50 50 ns Address Setup Time tAVWL tAS 0 0 0 ns Data Setup Time tDVWH tDS 45 50 50 ns Data Hold Time tWHDX tDH 0 0 0 ns ns Address Hold Time tWLAX tAH 45 50 50 Write Enable Pulse Width High tWHWL tWPH 20 20 20 Duration of Byte Programming Operation (1) tWHWH1 300 300 300 µs Sector Erase (2) tWHWH2 15 15 15 sec Read Recovery Time before Write tGHWL 0 V CC Setup Time t VCS 50 0 µs 50 44 Chip Erase Time (3) µs 0 50 Chip Programming Time ns 44 256 256 44 sec 256 sec Output Enable Hold Time (4) tOEH 10 10 10 ns RESET Pulse Width tRP 500 500 500 ns NOTES: 1. Typical value for t WHWH1 is 7µs. 2. Typical value for t WHWH2 is 1sec. 3. Typical value for Chip Erase Time is 32sec. 4. For Toggle and Data Polling. AC CHARACTERISTICS – READ-ONLY OPERATIONS (VCC = 5.0V, T A = -55°C to +125°C) Parameter Symbol -90 Min -120 Max 90 Min -150 Max 120 Min Unit Max Read Cycle Time t AVAV t RC Address Access Time t AVQV t ACC 90 120 150 150 ns Chip Select Access Time t ELQV t CE 90 120 150 ns Output Enable to Output Valid t GLQV t OE 40 50 55 ns ns Chip Select High to Output High Z (1) t EHQZ t DF 20 30 35 ns Output Enable High to Output High Z (1) t GHQZ t DF 20 30 35 ns Output Hold from Addresses, CS or OE Change, whichever is First t AXQX t OH RESET Low to Read Mode (1) 0 t Ready 0 20 0 20 ns 20 µs 1. Guaranteed by design, not tested. 3 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WF2M16-XXX5 AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS,CS CONTROLLED (VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C) Parameter Symbol -90 Min -120 Max Min -150 Max Min Unit Max Write Cycle Time t AVAV t WC 90 120 150 Write Enable Setup Time t WLEL t WS 0 0 0 ns Chip Select Pulse Width t ELEH t CP 45 50 50 ns Address Setup Time t AVEL t AS 0 0 0 ns Data Setup Time t DVEH t DS 45 50 50 ns Data Hold Time t EHDX t DH 0 0 0 ns Address Hold Time t ELAX t AH 45 50 50 ns t EHEL t CPH 20 Chip Select Pulse Width High 20 ns 20 ns Duration of Byte Programming Operation (1) t WHWH1 300 300 300 µs Sector Erase Time (2) t WHWH2 15 15 15 sec Read Recovery Time t GHEL 44 sec 256 sec 0 0 Chip Programming Time 44 Chip Erase Time (3) 256 Output Enable Hold Time (4) t OEH 10 µs 0 44 256 10 10 ns NOTES: 1. Typical value for t WHWH1 is 7µs. 2. Typical value for t WHWH2 is 1sec. 3. Typical value for Chip Erase Time is 32sec. 4. For Toggle and Data Polling. FIG. 2 AC TEST CONDITIONS AC TEST CIRCUIT Parameter I OL Current Source VZ D.U.T. ≈ 1.5V (Bipolar Supply) C eff = 50 pf CS I OH The Current Source Typ VIL = 0, VIH = 3.0 V Input Rise and Fall 5 ns Input and Output Reference Level 1.5 V Output Timing Reference Level 1.5 V NOTES: VZ is programmable from -2V to +7V. IOL & I OH programmable from 0 to 16mA. Tester Impedance Z0 = 75 Ω. VZ is typically the midpoint of V OH and V OL. IOL & edge I OH are of adjusted to simulate a typical resistive load circuit. rising the last WE signal ATE tester includes jig capacitance. WE Entire programming or erase operations FIG. 3 RY/BY RESET TIMING DIAGRAM tBUSY RESET tRP tReady White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 4 Unit Input Pulse Levels WF2M16-XXX5 FIG. 3 5 Outputs FWE FOE FCS1/FCS2 FDx High Z tACC tCE tOE Addresses Stable FDx Addresses tRC Output Valid tOH tDF High Z AC WAVEFORMS FOR READ OPERATIONS White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WF2M16-XXX5 NOTES: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. D7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 6 A0H tDH tWPH Data tDS tCS WE OE 5.0 V tWP tGHWL CS tWC Addresses 5555H tAS PA PD tAH tWHWH1 Data Polling D7 PA DOUT tOE tCE tRC tDF WRITE/ERASE/PROGRAM OPERATION, WE CONTROLLED tOH FIG. 4 WF2M16-XXX5 FIG. 5 AAH tDS tDH tVCS VCC Data WE OE CS Addresses tGHWL tCS tWP tAS tWPH 55H 2AAAH 5555H tAH 5555H 80H 5555H AAH 2AAAH 55H SA 10H/30H AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS NOTE: 1. SA is the sector address for Sector Erase. 7 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WF2M16-XXX5 FIG. 6 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 8 Data WE OE CS D0-D6 D7 t CH tOEH tCE t OE tWHWH 1 or 2 D7 D0-D6 = Invalid D7 = Valid Data D0-D7 Valid Data t OH t DF High Z AC WAVEFORMS FOR DATA POLLING DURING EMBEDDED ALGORITHM OPERATIONS WF2M16-XXX5 FIG. 7 A0H tDH tCPH 5.0 V tDS Data CS OE tWS tWC WE Addresses 5555H tGHEL tCP tAS PA PD tAH tWHWH1 Data Polling D7 PA DOUT ALTERNATE CS CONTROLLED PROGRAMMING OPERATION TIMINGS NOTES: 1. PA represents the address of the memory location to be programmed. 2. PD represents the data to be programmed at byte address. 3. D7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates the last two bus cycles of a four bus cycle sequence. 9 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WF2M16-XXX5 PACKAGE 102: 44 LEAD, CERAMIC SOJ** 28.70 (1.13) ± 0.25 (0.010) 3.96 (0.156) MAX 0.89 (0.035) Radius TYP 0.2 (0.008) ± 0.05 (0.002) 11.3 (0.446) ± 0.2 (0.009) 9.55 (0.376) ± 0.25 (0.010) 1.27 (0.050) ± 0.25 (0.010) PIN 1 IDENTIFIER 1.27 (0.050) TYP 26.7 (1.050) TYP ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES ** Package to be developed. PACKAGE 208: 44 LEAD, CERAMIC FLAT PACK** 28.45 (1.120) ± 0.26 (0.010) PIN 1 IDENTIFIER 3.18 (0.125) MAX 12.95 (0.510) ± 0.13 (0.005) 9.90 (0.390) ± 0.13 (0.005) 12.70 (0.500) ± 0.51 (0.020) 5.08 (0.200) ± 0.25 (0.010) 0.43 (0.017) ± 0.05 (0.002) 3.81 (0.150) TYP 0.13 (0.005) ± 0.05 (0.002) 32.64 (1.285) TYP 1.27 (0.050) TYP 26.67 (1.050) TYP 43.17 (1.699) ± 0.39 (0.015) ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES ** Package to be developed. White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 10 WF2M16-XXX5 PACKAGE 207: 56 LEAD, CERAMIC SOP* 23.63 (0.930) ± 0.25 (0.010) 0.18 (0.007) ± 0.05 (0.002) 21.59 (0.850) TYP 2.87 (0.113) MAX 1.02 (0.040) ± 0.18 (0.007) 12.96 (0.510) ± 0.15 (0.006) 16.13 (0.635) ± 0.13 (0.005) 1.60 (0.063) TYP + + PIN 1 IDENTIFIER 0.25 (0.010) ± 0.05 (0.002) 0.80 (0.031) TYP R = 0.18 (0.007) TYP 0° / -4° SEE DETAIL "A" * Package Dimensions subject to change 0.51 (0.020) TYP 4.06 (0.160) MAX DETAIL "A" ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES FIG. 8 ALTERNATE PIN CONFIGURATION FOR WF2M16W-XDAX5 PIN DESCRIPTION 56 CSOP TOP VIEW CS1 A12 A13 A14 A15 NC CS2 A21 A20 A19 A18 A17 A16 VCC GND I/O6 I/O14 I/O7 I/O15 RY/BY OE WE NC I/O13 I/O5 I/O12 I/O4 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 BLOCK DIAGRAM NC RESET A11 A10 A9 A1 A2 A3 A4 A5 A6 A7 GND A8 VCC I/O9 I/O1 I/O8 I/O0 NC NC NC NC I/O2 I/O10 I/O3 I/O11 GND I/O0-7 I/O8-15 RESET WE OE A1-21 RY/BY 2M x 8 2M x 8 CS1 CS2 I/O0-15 Data Inputs/Outputs A1-21 Address Inputs WE Write Enable CS1-2 Chip Select OE Output Enable VCC Power Supply VSS Ground RY/BY Ready/Busy RESET Reset NOTE: 1. RY/BY is an open drain output and should be pulled up to Vcc with an external resistor. 2. Address compatible with Intel 1M16 56 SSOP. 11 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WF2M16-XXX5 ORDERING INFORMATION W F 2M16 X - XXX X X 5 X LEAD FINISH: Blank = Gold plated leads A = Solder dip leads VPP PROGRAMMING VOLTAGE 5 = 5V DEVICE GRADE: M = Military, 883 Screened -55°C to +125°C I = Industrial -40°C to +85°C C = Commercial 0°C to +70°C PACKAGE TYPE: DA = 56 Lead CSOP (Package 207) fits standard 56 SSOP footprint DL = 44 Lead Ceramic SOJ (Package 102)* FL = 44 Lead Ceramic Flatpack (Package 208)* ACCESS TIME (ns) IMPROVEMENT MARK: • Address Pinout for 56 CSOP Package W = Word Wide Applications ORGANIZATION of 2M x 16 User configurable as 2 x 2M x 8 Flash WHITE ELECTRONIC DESIGNS CORP. * Package to be developed. DEVICE TYPE SECTOR SIZE SPEED 2M x 16 5V Flash Module 64KByte 2M x 16 5V Flash Module 64KByte 2M x 16 5V Flash Module 64KByte White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com PACKAGE SMD NO. 150ns 56 lead CSOP (DA) 5962-97610 01HXX 120ns 56 lead CSOP (DA) 5962-97610 02HXX 90ns 56 lead CSOP (DA) 5962-97610 03HXX 12