ETC WSF512K16

WSF512K16-XXX
HI-RELIABILITY PRODUCT
512KX16 SRAM/FLASH MODULE, SMD 5962-96901
FEATURES
FLASH MEMORY FEATURES
■ Access Times of 35ns (SRAM) and 90ns (FLASH)
■ 100,000 Erase/Program Cycles
■ Access Times of 70ns (SRAM) and 120ns (FLASH)
■ Sector Architecture
• 8 equal size sectors of 64K bytes each
• Any combination of sectors can be concurrently erased.
Also supports full chip erase
■ Packaging
• 66 pin, PGA Type, 1.385" square HIP, Hermetic Ceramic
HIP (Package 402)
• 68 lead, Hermetic CQFP (G2), 22mm (0.880") square
(Package 500). Designed to fit JEDEC 68 lead 0.990” CQFJ
footprint (Fig. 2)
■ 512Kx16 SRAM
■ 5 Volt Programming; 5V ± 10% Supply
■ Embedded Erase and Program Algorithms
■ Hardware Write Protection
■ Page Program Operation and Internal Program Control Time.
■ 512Kx16 5V FLASH
Note: Programming information available upon request.
■ Organized as 512Kx16 of SRAM and 512Kx16 of Flash
Memory with separate Data Busses
■ Both blocks of memory are User Configurable as 1Mx8
■ Low Power CMOS
■ Commercial, Industrial and Military Temperature Ranges
■ TTL Compatible Inputs and Outputs
■ Built-in Decoupling Caps and Multiple Ground Pins for
Low Noise Operation
■ Weight - 13 grams typical
FIG. 1
PIN CONFIGURATION FOR WSF512K16-XH2X
PIN DESCRIPTION
TOP VIEW
1
12
23
FD0-15
34
45
56
Flash Data Inputs/Outputs
SD0-15 SRAM Data Inputs/Outputs
SD8
SWE2
SD15
FD8
VCC
FD15
A0-18
Address Inputs
SD9
SCS2
SD14
FD9
FCS2
FD14
SWE1-2
SRAM Write Enable
SD10
GND
SD13
FD10
FWE2
FD13
SCS1-2
SRAM Chip Selects
OE
Output Enable
VCC
Power Supply
SD12
SD11
A13
FD11
A6
FD12
A14
A10
OE
A7
A3
A0
GND
Ground
A15
A11
A17
NC
A4
A1
NC
Not Connected
A16
A12
SWE1
A8
A5
A2
FWE1-2
Flash Write Enable
A18
VCC
SD7
A9
FWE1
FD7
FCS1-2
Flash Chip Select
SD0
SCS1
SD6
FD0
FCS1
FD6
SD1
NC
SD5
FD1
GND
FD5
SD2
SD3
SD4
FD2
FD3
FD4
11
22
33
44
55
BLOCK DIAGRAM
S W E1 S CS1
512K x 8
SRAM
F W E1 F CS1
F W E2 F CS2
512K x 8
SRAM
512K x 8
FLASH
512K x 8
FLASH
66
8
SD0-7
October 2000 Rev.
5
S W E2 S CS2
OE
A0-18
1
8
SD8-15
8
FD0-7
8
FD8-15
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WSF512K16-XXX
FIG. 2
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
GND
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
PIN CONFIGURATION FOR WSF512K16-XG2X
TOP VIEW
NC
A0
A1
A2
A3
A4
A5
FCS1
GND
FCS2
SWE1
A6
A7
A8
A9
A10
VCC
PIN DESCRIPTION
FD0-15
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
SD0-15 SRAM Data Inputs/Outputs
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
FD0
FD1
FD2
FD3
FD4
FD5
FD6
FD7
GND
FD8
FD9
FD10
FD11
FD12
FD13
FD14
FD15
NC
NC
A18
FWE2
FWE1
SWE2
OE
SCS2
A17
A16
SCS1
A15
A14
A13
A12
A11
VCC
Address Inputs
SRAM Write Enable
SCS1-2
SRAM Chip Selects
OE
Output Enable
VCC
Power Supply
GND
Ground
NC
Not Connected
FWE1-2
Flash Write Enable
FCS1-2
Flash Chip Select
BLOCK DIAGRAM
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
S W E1 S CS1
S W E2 S CS2
F W E1 F CS1
F W E2 F CS2
OE
A0-18
512K x 8
SRAM
8
SD0-7
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
A0-18
SWE1-2
0.940"
The WEDC 68 lead G2 CQFP fills
the same fit and function as the
JEDEC 68 lead CQFJ or 68 PLCC.
But the G2 has the TCE and lead
inspection advantage of the
CQFP form.
Flash Data Inputs/Outputs
2
512K x 8
SRAM
8
SD8-15
512K x 8
FLASH
8
FD0-7
512K x 8
FLASH
8
FD8-15
WSF512K16-XXX
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature
Storage Temperature
SRAM TRUTH TABLE
Symbol
Min
Max
Unit
TA
-55
+125
°C
°C
T STG
-65
+150
Signal Voltage Relative to GND
VG
-0.5
7.0
V
Junction Temperature
TJ
150
°C
Supply Voltage
V CC
7.0
V
-0.5
SCS
H
L
L
L
OE
X
L
H
X
SWE
X
H
H
L
20 years
Flash Endurance (write/erase cycles)
100,000
Data I/O
High Z
Data Out
High Z
Data In
Power
Standby
Active
Active
Active
CAPACITANCE
(T A = +25°C)
Parameter
Flash Data Retention
Mode
Standby
Read
Read
Write
Test
NOTES:
1. Stresses above the absolute maximum rating may cause permanent damage
to the device. Extended operation at the maximum levels may degrade
performance and affect reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol
Condition
Max
Unit
OE Capacitance
C OE
V IN = 0V, f = 1.0MHz
50
pF
F/S WE 1-2 Capacitance
C WE
V IN = 0V, f = 1.0MHz
20
pF
F/S CS 1-2 Capacitance
C CS
V IN = 0V, f = 1.0MHz
20
pF
Data I/O Capacitance
C I/O
V IN = 0V, f = 1.0MHz
20
pF
Address Input Capacitance
C AD
V IN = 0V, f = 1.0MHz
50
pF
This parameter is guaranteed by design but not tested.
Parameter
Symbol
Min
Max
Unit
Supply Voltage
V CC
4.5
5.5
V
Input High Voltage
V IH
2.2
V CC + 0.3
V
Input Low Voltage
V IL
-0.5
+0.8
V
DC CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
Parameter
Max
Unit
Input Leakage Current
I LI
V CC = 5.5, V IN = GND to VCC
10
µA
Output Leakage Current
I LO
FCS = SCS = VIH, OE = VIH, VOUT = GND to VCC
10
µA
SCS = VIL, OE = VIH, f = 5mHz, V CC = 5.5, FCS = VIH
330
mA
SRAM Operating Supply Current x 16 Mode
Symbol
ICCx16
Conditions
Min
Standby Current
I SB
FCS = SCS = VIH, OE = VIH, f = 5mHz, V CC = 5.5
45
mA
SRAM Output Low Voltage
V OL
I OL = 8mA, V CC = 4.5, FCS = VIH
0.4
V
SRAM Output High Voltage
V OH
I OL = -4.0mA, V CC = 4.5, FCS = VIH
Flash V CC Active Current for Read (1)
I CC1
FCS = VIL, OE = VIH, SCS = VIH
130
mA
Flash V CC Active Current for Program or
Erase (2)
I CC2
FCS = VIL, OE = VIH, SCS = VIH
150
mA
Flash Output Low Voltage
V OL
I OL = 8.0mA, V CC = 4.5, SCS = VIH
0.45
V
Flash Output High Voltage
V OH1
I OH = -2.5 mA, V CC = 4.5, SCS = VIH
Flash Low V CC Lock Out Voltage
V LKO
4.2
V
2.4
V
0.85 x V CC
3.2
V
NOTES:
1. The I CC current listed includes both the DC operating current and the frequency dependent component (@ 5 MHz).
The frequency component typically is less than 2 mA/MHz, with OE at VIH .
2. ICC active while Embedded Algorithm (program or erase) is in progress.
3. DC test conditions: VIL = 0.3V, VIH = V CC - 0.3V
3
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WSF512K16-XXX
SRAM AC CHARACTERISTICS
(VCC = 5.0V, T A = -55°C to +125°C)
Parameter
Read Cycle
Symbol
SRAM AC CHARACTERISTICS
(VCC = 5.0V, T A = -55°C to +125°C)
-35
Min Max
-70
Unit
Min Max
Parameter
Write Cycle
35
70
ns
Write Cycle Time
ns
Chip Select to End of Write
ns
Symbol
-35
Min Max
-70
Min Max
Unit
t WC
35
70
ns
tCW
25
60
ns
Address Valid to End of Write
t AW
25
60
ns
Read Cycle Time
t RC
Address Access Time
tAA
Output Hold from Address Change
t OH
Chip Select Access Time
t ACS
35
70
ns
Data Valid to End of Write
t DW
20
30
ns
Output Enable to Output Valid
t OE
25
35
ns
Write Pulse Width
t WP
25
50
ns
Chip Select to Output in Low Z
t CLZ 1
4
10
ns
Address Setup Time
t AS
0
0
ns
Output Enable to Output in Low Z
t OLZ 1
0
5
ns
Address Hold Time
t AH
0
5
ns
Chip Disable to Output in High Z
t CHZ 1
15
25
ns
Output Active from End of Write
t OW 1
0
5
Output Disable to Output in High Z
t OHZ 1
15
25
ns
Write Enable to Output in High Z
t WHZ 1
35
0
70
5
1. This parameter is guaranteed by design but not tested.
Data Hold from Write Time
t DH
15
0
ns
25
0
ns
1. This parameter is guaranteed by design but not tested.
FIG. 3
AC TEST CONDITIONS
AC TEST CIRCUIT
I OL
Parameter
Current Source
VZ
D.U.T.
≈ 1.5V
(Bipolar Supply)
C eff = 50 pf
I OH
Current Source
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
4
Typ
ns
Unit
Input Pulse Levels
VIL = 0, VIH = 3.0
V
Input Rise and Fall
5
ns
Input and Output Reference Level
1.5
V
Output Timing Reference Level
1.5
V
Notes:
V Z is programmable from -2V to +7V.
I OL & IOH programmable from 0 to 16mA.
Tester Impedance Z 0 = 75 Ω.
V Z is typically the midpoint of V OH and V OL.
I OL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
WSF512K16-XXX
FIG. 4 SRAM
tRC
TIMING WAVEFORM - READ CYCLE
ADDRESS
tAA
SCS
tRC
tCHZ
tACS
ADDRESS
tCLZ
tAA
SOE
tOE
tOLZ
tOH
DATA I/O
PREVIOUS DATA VALID
DATA I/O
DATA VALID
tOHZ
DATA VALID
HIGH IMPEDANCE
READ CYCLE 2, (SWE = VIH)
READ CYCLE 1, (SCS = OE = VIL, SWE = VIH)
FIG. 5 SRAM
WRITE CYCLE - SWE CONTROLLED
tWC
ADDRESS
tAW
tAH
tCW
SCS
tAS
tWP
SWE
tOW
tWHZ
tDW
DATA I/O
tDH
DATA VALID
WRITE CYCLE 1, SWE CONTROLLED
FIG. 6 SRAM
WRITE CYCLE - SCS CONTROLLED
tWC
WS32K32-XHX
ADDRESS
tAS
tAW
tAH
tCW
SCS
tWP
SWE
tDW
DATA I/O
tDH
DATA VALID
WRITE CYCLE 2, SCS CONTROLLED
5
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WSF512K16-XXX
FLASH AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS, FWE CONTROLLED
(VCC = 5.0V, TA = -55°C to +125°C)
Parameter
Symbol
-90
Min
-120
Max
Min
Unit
Max
Write Cycle Time
t AVAV
t WC
90
120
Chip Select Setup Time
t ELWL
t CS
0
0
ns
Write Enable Pulse Width
t WLWH
t WP
45
50
ns
Address Setup Time
t AVWL
t AS
0
0
ns
Data Setup Time
t DVWH
t DS
45
50
ns
Data Hold Time
t WHDX
t DH
0
0
ns
Address Hold Time
t WLAX
t AH
45
50
ns
Write Enable Pulse Width High
t WHWL
t WPH
20
Duration of Byte Programming Operation (1)
t WHWH1
300
300
µs
Sector Erase Time (2)
t WHWH2
15
15
sec
Read Recovery Time Before Write
20
ns
0
0
µs
t VCS
50
50
µs
t OEH
10
t GHWL
VCC Set-up Time
ns
Chip Programming Time
11
Chip Select Hold Time
11
sec
64
sec
10
Chip Erase Time (3)
ns
64
1. Typical value for tWHWH1 is 7ns.
2. Typical value for tWHWH2 is 1sec.
3. Typical value for Chip Erase Time is 8sec.
FLASH AC CHARACTERISTICS – READ ONLY OPERATIONS
(VCC = 5.0V, TA = -55°C to +125°C)
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
OE to Output Valid
Chip Select to Output High Z (1)
OE High to Output High Z (1)
Output Hold from Address, CS or OE Change, whichever is first
Symbol
t AVAV
t AVQV
t ELQV
t GLQV
t EHQZ
t GHQZ
t AXQX
t RC
t ACC
t CE
t OE
t DF
t DF
t OH
1. Guaranteed by design, not tested.
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
-90
6
Min
90
-120
120
90
90
35
20
20
0
Unit
Max
120
120
50
30
30
0
ns
ns
ns
ns
ns
ns
ns
WSF512K16-XXX
FLASH AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS, FCS CONTROLLED
(VCC = 5.0V, TA = -55°C to +125°C)
Parameter
Symbol
-90
-120
Unit
Write Cycle Time
t AVAV
t WC
Min
90
FWE Setup Time
t WLEL
t WS
0
0
ns
FCS Pulse Width
t ELEH
t CP
45
50
ns
Address Setup Time
t AVEL
t AS
0
0
ns
Data Setup Time
t DVEH
t DS
45
50
ns
Data Hold Time
t EHDX
t DH
0
0
ns
Address Hold Time
t ELAX
t AH
45
50
ns
tEHEL
tCPH
20
FCS Pulse Width High
Duration of Programming Operation (1)
t WHWH1
Sector Erase Time (2)
t WHWH2
Read Recovery Time
t GHEL
Max
120
ns
20
300
15
0
ns
300
µs
15
sec
0
ns
Chip Programming Time
11
11
sec
Chip Erase Time (3)
64
64
sec
1. Typical value for tWHWH1 is 7ns.
2. Typical value for tWHWH2 is 1sec.
3. Typical value for Chip Erase Time is 8sec.
7
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WSF512K16-XXX
FIG. 7
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
8
Outputs
FWE
OE
FCS
Addresses
High Z
tACC
tCE
tOE
Addresses Stable
tRC
Output Valid
tOH
tDF
High Z
AC WAVEFORMS FOR FLASH MEMORY READ OPERATIONS
WSF512K16-XXX
FIG. 8
A0H
tDH
tWPH
tWP
tDS
tCS
tGHWL
tWC
5555H
tAS
PA
PD
tAH
tWHWH1
Data Polling
D7
PA
DOUT
tOE
tCE
tRC
tDF
tOH
WRITE/ERASE/PROGRAM OPERATION, FLASH MEMORY FWE CONTROLLED
9
5.0 V
Data
FWE
OE
FCS
1. PA is the address of the memory location
to be programmed.
2. PD is the data to be programmed at byte address.
3. D7 is the output of the complement of the
data written to the device.
4. DOUT is the output of the data written to
the device.
5. Figure indicates last two bus cycles of four bus
cycle sequence.
Addresses
NOTES:
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WSF512K16-XXX
FIG. 9
1. SA is the sector address
for Sector Erase.
AAH
tDS
tDH
VCC
tVCS
10
Data
OE
FCS
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
FWE
NOTES:
Addresses
tGHWL
tCS
tWP
tWPH
55H
2AAAH
5555H
tAS
tAH
5555H
80H
5555H
AAH
2AAAH
55H
SA
10H/30H
AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS FOR FLASH MEMORY
WSF512K16-XXX
FIG. 10
D0-D7
Valid Data
D0-D6
FWE
OE
FCS
D7
t CH
tOEH
tCE
t OE
tWHWH 1 or 2
D7
D0-D6 = Invalid
t OE
D7 =
Valid Data
t OH
t DF
High Z
AC WAVEFORMS FOR DATA POLLING DURING
EMBEDDED ALGORITHM OPERATIONS FOR
FLASH MEMORY
11
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WSF512K16-XXX
FIG. 11
A0H
tDH
tCPH
NOTES:
1. PA represents the address of the memory location to be programmed.
2. PD represents the data to be programmed at byte address.
3. D7 is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates the last two bus cycles of a four bus cycle sequence.
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12
5.0 V
tDS
Data
FCS
OE
tWS
tWC
FWE
Addresses
5555H
tGHEL
tCP
tAS
PA
PD
tAH
tWHWH1
Data Polling
D7
PA
DOUT
WRITE/ERASE/PROGRAM OPERATION FOR FLASH MEMORY, CS CONTROLLED
WSF512K16-XXX
PACKAGE 402:
66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H2)
35.2 (1.385) ± 0.38 (0.015) SQ
PIN 1 IDENTIFIER
SQUARE PAD
ON BOTTOM
25.4 (1.0) TYP
5.7 (0.223)
MAX
3.81 (0.150)
± 0.1 (0.005)
1.27 (0.050) ± 0.1 (0.005)
0.76 (0.030) ± 0.1 (0.005)
2.54 (0.100)
TYP
1.27 (0.050) TYP DIA
15.24 (0.600) TYP
0.46 (0.018) ± 0.05 (0.002) DIA
25.4 (1.0) TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
13
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WSF512K16-XXX
PACKAGE 500:
68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2)
25.1 (0.990) ± 0.25 (0.010) SQ
5.1 (0.200) MAX
22.4 (0.880) ± 0.25 (0.010) SQ
0.25 (0.010) ± 0.1 (0.002)
0.25 (0.010) REF
Pin 1
R 0.25
(0.010)
24.0 (0.946)
± 0.25 (0.010)
0.25 (0.010)
± 0.127 (0.005)
1° / 7°
1.0 (0.040)
± 0.127 (0.005)
23.87
(0.940) REF
DETAIL A
1.27 (0.050) TYP
SEE DETAIL "A"
0.38 (0.015) ± 0.05 (0.002)
20.3 (0.800) REF
The WEDC 68 lead G2 CQFP fills
the same fit and function as the
JEDEC 68 lead CQFJ or 68 PLCC.
But the G2 has the TCE and lead
inspection advantage of the
CQFP form.
0.940"
TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
14
WSF512K16-XXX
ORDERING INFORMATION
W S F 512K16 - XXX X X X
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
DEVICE GRADE:
M = Military Screened
I = Industrial
C = Commercial
-55°C to +125°C
-40°C to +85°C
0°C to +70°C
PACKAGE TYPE:
H2 = Ceramic Hex In-line Package, HIP (Package 402)
G2 = 22 mm Ceramic Quad Flat Pack, CQFP (Package 500)
ACCESS TIME (ns)
39 = 35ns SRAM and 90ns FLASH
72 = 70ns SRAM and 120ns FLASH also available
ORGANIZATION, 512K x 16
Flash
SRAM
WHITE ELECTRONIC DESIGNS CORP.
DEVICE TYPE
SRAM SPEED
FLASH SPEED
PACKAGE
SMD NO.
512K x 16 Mixed Module
70ns
120ns
66 pin HIP (H2)
5962-96901 01HXX
512K x 16 Mixed Module
35ns
90ns
66 pin HIP (H2)
5962-96901 02HXX
512K x 16 Mixed Module
70ns
120ns
68 lead CQFP/J (G2)
5962-96901 01HMX
512K x 16 Mixed Module
35ns
90ns
68 lead CQFP/J (G2)
5962-96901 02HMX
15
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