a Quad, 12-Bit DAC Voltage Output with Readback DAC8412/DAC8413 FEATURES +5 to 615 Volt Operation Unipolar or Bipolar Operation True Voltage Output Double-Buffered Inputs Reset to Min or Center Scale Fast Bus Access Time Readback FUNCTIONAL BLOCK DIAGRAM VLOGIC DATA I/O A0 A1 APPLICATIONS Automatic Test Equipment Digitally Controlled Calibration Servo Controls Process Control Equipment I/O 12 PORT INPUT REG A OUTPUT REG A DAC A DGND INPUT REG B OUTPUT REG B DAC B INPUT REG C OUTPUT REG C DAC C INPUT REG D OUTPUT REG D DAC D CONTROL LOGIC R/W CS RESET LDAC GENERAL DESCRIPTION The DAC8412 and DAC8413 are quad, 12-bit voltage output DACs with readback capability. Built using a complementary BiCMOS process, these monolithic DACs offer the user very high package density. Output voltage swing is set by the two reference inputs VREFH and VREFL. By setting the VREFL input to 0 volts and VREFH to a positive voltage, the DAC will provide a unipolar positive output range. A similar configuration with VREFH at 0 volts and VREFL at a negative voltage will provide a unipolar negative output range. Bipolar outputs are configured by connecting both VREFH and VREFL to nonzero voltages. This method of setting output voltage range has advantages over other bipolar offsetting methods because it is not dependent on internal and external resistors with different temperature coefficients. VDD VREFH VOUTA VOUTB VOUTC VOUTD VREFL VSS Digital controls allow the user to load or read back data from any DAC, load any DAC and transfer data to all DACs at one time. An active low RESET loads all DAC output registers to midscale for the DAC8412 and zero scale for the DAC8413. The DAC8412/DAC8413 are available in 28-pin plastic DIP, cerdip, PLCC and LCC packages. They can be operated from a wide variety of supply and reference voltages with supplies ranging from single +5 volt to ± 15 volts, and references from +2.5 to ± 10 volts. Power dissipation is less than 330 mW with ± 15 volt supplies and only 60 mW with a +5 volt supply. For MIL-STD-883 applications, contact your local ADI sales office for the DAC8412/DAC8413/883 data sheet which specifies operation over the –55°C to +125°C temperature range. All 883 parts are also available on Standard Military Drawings 5962-91-76401MXA through -76404M3A. INL vs. Code Over Temperature REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 DAC8412/DAC8413–SPECIFICATIONS (@ V = +15.0 V, V = –15.0 V, V DD SS LOGIC = +5.0 V, VREFH = +10.0 V, VREFL = –10.0 V, ELECTRICAL CHARACTERISTICS –408C ≤ T ≤ +858C unless otherwise noted. See Note 1 for supply variations.) A Parameter Integral Linearity “E” Integral Linearity “F” Differential Linearity Min Scale Error Full-Scale Error Min Scale Tempco Full-Scale Tempco MATCHING PERFORMANCE Linearity Matching REFERENCE Positive Reference Input Range Negative Reference Input Range Reference High Input Current Reference Low Input Current AMPLIFIER CHARACTERISTICS Output Current Settling Time Slew Rate LOGIC CHARACTERISTICS Logic Input High Voltage Logic Input Low Voltage Logic Output High Voltage Logic Output Low Voltage Logic Input Current Input Capacitance Crosstalk Large Signal Bandwidth LOGIC TIMING CHARACTERISTICS WRITE Chip Select Write Pulse Width Write Setup Write Hold Address Setup Address Hold Load Setup Load Hold Write Data Setup Write Data Hold Load Pulse Width Reset Pulse Width READ Chip Select Read Pulse Width Read Data Hold Read Data Setup Data to Hi Z Chip Select to Data SUPPLY CHARACTERISTICS Power Supply Sensitivity Positive Supply Current Negative Supply Current Power Dissipation Symbol INL INL DNL VZSE VFSE TCVZSE TCVFSE Conditions Min Monotonic Over Temperature RL = 2 kΩ RL = 2 kΩ RL = 2 kΩ RL = 2 kΩ –1 Note 2 Note 2 IREFH IREFL IOUT tS SR VINH VINL VOH VOL IIN CIN tRCS tRDH tRDS tDZ tCSD PSS IDD ISS PDISS tWCS = 80 ns tWCS = 80 ns tWCS = 80 ns tWCS = 80 ns tRCS = 130 ns tRCS = 130 ns CL = 10 pF CL = 100 pF 15 20 Units LSB LSB LSB LSB LSB ppm/°C ppm/°C ±1 LSB ±2 ±2 VDD – 2 5 VREFH – 2.5 +2.75 +2.75 V V mA mA –5 +5 mA µs V/µs 6 2.2 2.4 0.8 2.4 0.4 1 8 >72 160 –3 dB, VREFH = 0 to +10 V p-p Note 3 tWCS tWS tWH tAS tAH tLS tLH tWDS tWDH tLWD tRESET Max ± 0.5 ±1 VREFL + 2.5 –10 –2.75 +1.5 0 +2 to 0.01% 10% to 90% TA = +25°C TA = +25°C IOH = +0.4 mA IOL = –1.6 mA Typ 0.25 80 0 0 0 0 70 30 20 0 170 140 40 130 0 0 100 14.25 V ≤ VDD ≤ 15.75 V VREFH = +2.5 V –10 ns ns ns ns ns ns ns ns ns ns ns 30 10 130 100 150 120 8.5 –6.5 V V V V µA pF dB kHz 160 150 12 330 ns ns ns ns ns ppm/V mA mA mW NOTES 1 All supplies can be varied ± 5%, and operation is guaranteed. Device is tested with nominal supplies. 2 Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed. 3 All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. Specifications subject to change without notice. –2– REV. C DAC8412/DAC8413 ELECTRICAL CHARACTERISTICS (@ VDD = VLOGIC = +5.0 V 6 5%, VSS = 0.0 V, VREFH = +2.5 V, VREFL = 0.0 V, and VSS = –5.0 V 6 5%, VREFL = –2.5 V, –408C ≤ TA ≤ +858C unless otherwise noted. See Note 1 for supply variations.) Parameter Symbol Integral Linearity “E” Integral Linearity “F” Integral Linearity “E” Integral Linearity “F” Differential Linearity Min Scale Error Full-Scale Error Min Scale Error Full-Scale Error Min Scale Tempco Full-Scale Tempco INL INL INL INL DNL VZSE VFSE VZSE VFSE TCVZSE TCVFSE MATCHING PERFORMANCE Linearity Matching REFERENCE Positive Reference Input Range Negative Reference Input Range Negative Reference Input Range Reference High Input Current AMPLIFIER CHARACTERISTICS Output Current Settling Time Slew Rate LOGIC CHARACTERISTICS Logic Input High Voltage Logic Input Low Voltage Logic Output High Voltage Logic Output Low Voltage Logic Input Current Input Capacitance LOGIC TIMING CHARACTERISTICS WRITE Chip Select Write Pulse Width Write Setup Write Hold Address Setup Address Hold Load Setup Load Hold Write Data Setup Write Data Hold Load Pulse Width Reset Pulse Width READ Chip Select Read Pulse Width Read Data Hold Read Data Setup Data to Hi Z Chip Select to Data SUPPLY CHARACTERISTICS Power Supply Sensitivity Positive Supply Current Negative Supply Current Conditions VSS = 0.0 V; Note 2 VSS = 0.0 V; Note 2 Monotonic Over Temperature VSS = –5.0 V VSS = –5.0 V VSS = 0.0 V VSS = 0.0 V IREFH Note 3 VSS = 0.0 V VSS = –5.0 V Code 000H IOUT tS SR to 0.01% 10% to 90% VINH VINL VOH VOL IIN CIN Min Typ Max Units 1/2 ±1 ±2 ±2 ±4 100 100 LSB LSB LSB LSB LSB LSB LSB LSB LSB ppm/°C ppm/°C ±1 LSB –1 ±4 ±4 ±8 ±8 VREFL + 2.5 0 –2.5 –1.0 –1.25 TA = +25°C TA = +25°C IOH = +0.4 mA IOL = –1.6 mA VDD – 2 5 VREFH – 2.5 VREFH – 2.5 +1.0 V V V mA +1.25 mA µs V/µs 6 2.2 2.4 0.8 2.4 0.45 1 8 Note 4 tWCS tWS tWH tAS tAH tLS tLH tWDS tWDH tLWD tRESET tRCS tRDH tRDS tDZ tCSD PSS IDD ISS tWCS = 150 ns tWCS = 150 ns tWCS = 150 ns tWCS = 150 ns tRCS = 170 ns tRCS = 170 ns CL = 10 pF CL = 100 pF VSS = –5.0 V 150 0 0 0 0 70 50 20 0 180 150 90 170 20 0 120 ns ns ns ns ns ns ns ns ns ns ns 30 20 130 110 200 220 320 100 7 12 –10 NOTES 1 All supplies can be varied ± 5%, and operation is guaranteed. Device is tested with V DD = +4.75 V. 2 For single supply operation only (V REFL = 0.0 V, VSS = 0.0 V): Due to internal offset errors, INL and DNL are measured beginning at code 2 (002 H). 3 Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed. 4 All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. Specifications subject to change without notice. REV. C V V V V µA pF –3– ns ns ns ns ns ppm/V mA mA DAC8412/DAC8413 (@ VDD = +15.0 V, VSS = –15.0 V, VLOGIC = +5.0 V, VREFH = +10.0 V, VREFL = –10.0 V, TA = +258C unless WAFER TEST LIMITS otherwise noted.) Parameter Symbol Integral Nonlinearity Differential Nonlinearity Min Scale Offset Full-Scale Offset Logic Input High Voltage Logic Input Low Voltage Logic Input Current Logic Output High Voltage Logic Output Low Voltage Positive Supply Current Negative Supply Current INL DNL VZSE VFSE VINH VINL IIN VOH VOL IDD ISS Conditions IOH = +0.4 mA IOL = –1.6 mA VREFH = +2.5 V DAC8412GBC DAC8413GBC Limit Units +1 +1 +1 +1 2.4 0.8 1 2.4 0.4 12 –10 LSB max LSB max LSB max LSB max V min V max µA max V min V max mA max mA min NOTE Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing. ABSOLUTE MAXIMUM RATINGS DICE CHARACTERISTICS (TA = +25°C unless otherwise noted) VSS to VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +33.0 V VSS to VLOGIC . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +33.0 V VLOGIC to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V, +18.0 V VSS to VREFL . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +VSS–2.0 V VREFH to VDD . . . . . . . . . . . . . . . . . . . . . . . . . +2.0 V, +33.0 V VREFH to VREFL . . . . . . . . . . . . . . . . . . . . . . . . +2.0 V, VSS–VDD Current into Any Pin 4 . . . . . . . . . . . . . . . . . . . . . . . ± 15 mA Digital Input Voltage to DGND . . . . . –0.3 V, VLOGIC +0.3 V Digital Output Voltage to DGND . . . . . . . . . . –0.3 V, +7.0 V Operating Temperature Range ET, FT, EP, FP, FPC . . . . . . . . . . . . . . . . –40°C to +85°C AT, BT, BTC . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C Dice Junction Temperature . . . . . . . . . . . . . . . . . . . . . +150°C Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Power Dissipation Package . . . . . . . . . . . . . . . . . . . 1000 mW Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . +300°C Thermal Resistance Package Type θJA* θJC Units 28-Pin Hermetic DIP (T) 28-Pin Plastic DIP (P) 28-Lead Hermetic Leadless Chip Carrier (TC) 28-Lead Plastic Leaded Chip Carrier (PC) 50 48 70 63 7 22 28 25 °C/W °C/W °C/W °C/W NOTE *θJA is specified for worst case mounting conditions, i. e., θJA is specified for device in socket. CAUTION 1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to the above maximum rating conditions for extended periods may affect device reliability. 2. Digital inputs and outputs are protected, however, permanent damage may occur on unprotected units from high-energy electrostatic fields. Keep units in conductive foam or packaging at all times until ready to use. Use proper antistatic handling procedures. 3. Remove power before inserting or removing units from their sockets. 4. Analog outputs are protected from short circuit to ground or either supply. –4– WARNING! ESD SENSITIVE DEVICE REV. C DAC8412/DAC8413 ORDERING INFORMATION1 Package Package Option P-28A E-28A Q-28 Q-28 Q-28 Q-28 N-28 N-28 VOUTC VOUTA 3 26 VOUTD VSS 4 25 VDD DGND 5 24 VLOGIC RESET 6 23 CS LDAC 7 DB0 (LSB) 8 TOP VIEW (Not to Scale) 22 A0 21 A1 DB1 9 20 R/W DB2 10 19 DB11 (MSB) DB3 11 18 DB10 DB4 12 17 DB9 DB5 13 16 DB8 DB6 14 15 DB7 VOUTD 1 VREFL VREFH 2 VOUTC VOUTB 3 28 27 26 DGND 5 25 VDD RESET 6 24 VLOGIC 23 CS 22 A0 LDAC 7 DB0 (LSB) 8 DB1 9 DAC8412PC DAC8413PC TOP VIEW (Not to Scale) 21 A1 DB2 10 20 R/W DB3 11 19 DB11 (MSB) t DZ 13 14 15 16 17 DB9 DB4 12 18 DB10 A0/A1 DB8 tAH 4 DB7 R/W DATA OUT DAC8412 DAC8413 DB6 t RDH tAS VREFL 27 PLCC t RCS t RDS 28 2 P-28A E-28A Q-28 Q-28 Q-28 Q-28 N-28 N-28 NOTES 1 Burn-in is available on extended industrial temperature range parts in cerdip. 2 A complete /883 data sheet is available. For availability and burn-in information, contact your local sales office. CS 1 VSS DAC8412FPC PLCC DAC8412BTC/883 LCC DAC8412ET Cerdip DAC8412AT/883 Cerdip DAC8412FT Cerdip DAC8412BT/883 Cerdip DAC8412EP Plastic DAC8412FP Plastic DAC8412GBC Dice DAC8413FPC PLCC DAC8413BTC/883 LCC DAC8413ET Cerdip DAC8413AT/883 Cerdip DAC8413FT Cerdip DAC8413BT/883 Cerdip DAC8413EP Plastic DAC8413FP Plastic DAC8413GBC Dice VREFH VOUTB VOUTA ±1 ± 1.5 ± 0.5 ± 0.75 ±1 ± 1.5 ± 0.5 ±1 ±1 ±1 ± 1.5 ± 0.5 ± 0.75 ±1 ± 1.5 ± 0.5 ±1 ±1 Cerdip DB5 Extended Industrial2 Temperature –408C to +858C Military2 INL Temperature (LSB) –558C to +1258C PIN CONFIGURATIONS DATA VALID t CSD R/W tAS tAH A0/A1 tLS tLWD tLH 5 RESET 6 LDAC 7 DB0 (LSB) 8 DB1 9 DB2 10 VOUTD 2 VOUTC 3 VREFL 4 28 27 26 25 1 DAC8412TC DAC8413TC TOP VIEW (Not to Scale) t RESET RESET Data WRITE (Input and Output Registers) Timing –5– CS 22 A0 20 R/W 13 14 15 16 17 18 DB6 DB7 DB8 DB9 DB10 19 DB11 (MSB) 12 DB5 t DH 23 21 A1 DB4 t DS DATA IN VDD 24 VLOGIC DB3 11 LDAC REV. C DGND VOUTB tWH VSS tWS VOUTA tWCS CS VREFH LCC Data Output (Read) Timing DAC8412/DAC8413 V DD V REFH dividing the system into three separate functional groups: the digital I/O and logic, the digital to analog converters and the output amplifiers. V REFL + C1 + D1 R2 R2 D1 C2 C2 R1 DACs D1 C1 C1 + V REFH V REFL N/C VOUTB V OUTC N/C N/C V OUTA V OUTD N/C C2 VSS GND R6 R1 R3 R3 Each DAC is a voltage switched, high impedance (R = 50 kΩ), R-2R ladder configuration. Each 2R resistor is driven by a pair of switches that connect the resistor to either VREFH or VREFL. R3 Reference Inputs V DD All four DACs share common reference high (VREFH) and reference low (VREFL) inputs. The voltages applied to these reference inputs set the output high and low voltage limits of all four of the DACs. Each reference input has voltage restrictions with respect to the other reference and to the power supplies. The VREFL can be set at any voltage between VSS and VREFH – 2.5 volts, and VREFH can be set to any value between +VDD – 2.5 volts and VREFL + 2.5 volts. Note that because of these restrictions the DAC8412 references cannot be inverted (i.e., VREFL cannot be greater than VREFH). VLOGIC RESET CS LDAC A0 DB0 A1 DB1 R/W DB2 DB11 DB3 DB10 DB4 DB9 DB5 DB8 DB6 DB7 C2 R5 R4 R4 * ONCE PER PORT GND + C1 D1 VSS VDD = +15V, VSS = –15V, VREFH = +10V, V REFL = –10V R1 = 10Ω, R2 = 100Ω, R3 = 5kΩ, R4 = 10kΩ, R5 = 100kΩ, R6 = 47Ω for LCC, R6 = 100Ω for DIP C1 = 4.7 µF (ONCE PER PORT), C2 = 0.01µF (EACH DEVICE) D1 = 1N4001 OR EQUIVALENT (ONCE PER PORT) DAC8412/DAC8413 Burn-In Diagram OPERATION Introduction The DAC8412 and DAC8413 are quad, voltage output, 12-bit DACs featuring a 12-bit data bus with readback capability. The only differences between the DAC8412 and DAC8413 are the reset functions. The DAC8412 resets to midscale (code 800H) and the DAC8413 resets to minimum scale (code 000H). It is important to note that the DAC8412’s VREFH input both sinks and sources current. Also the input current of both VREFH and VREFL are code dependent. Many references have limited current sinking capability and must be buffered with an amplifier to drive VREFH. The VREFL has no such special requirements. It is recommended that the reference inputs be bypassed with 0.2 µF capacitors when operating with ± 10 volt references. Digital I/O See Table I for digital control logic truth table. Digital I/O consists of a 12-bit wide bidirectional data bus, two register select inputs, A0 and A1, a R/W input, a RESET input, a Chip Select (CS), and a Load DAC (LDAC) input. Control of the DACs and bus direction is determined by these inputs as shown in Table I. Digital data bits are labeled with the MSB defined as data bit “11” and the LSB as data bit “0.” All digital pins are TTL/CMOS compatible. The ability to operate from a single +5 volt only supply is a unique feature of these DACs. Table I. DAC8412/DAC8413 Logic Table A1 A0 R/W CS RS LDAC INPUT REG OUTPUT REG MODE L L H H L L H H L L H H X X X X L H L H L H L H L H L H X X X X L L L L L L L L H H H H X X X X L L L L L L L L L L L L H H X H H H H H H H H H H H H H H H L g L L L L H H H H H H H H L H X X WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE HOLD WRITE INPUT WRITE HOLD WRITE INPUT WRITE HOLD WRITE INPUT WRITE HOLD WRITE INPUT READ HOLD READ INPUT READ HOLD READ INPUT READ HOLD READ INPUT READ HOLD READ INPUT HOLD Update all output registers HOLD HOLD HOLD *All registers reset to mid/zero-scale *All registers latched to mid/zero-scale DAC A B C D A B C D A B C D All All All All *DAC8412 resets to midscale, and DAC8413 resets to zero scale. L = Logic Low; H = Logic High; X - Don’t Care. –6– REV. C DAC8412/DAC8413 amplifiers in most applications. These amplifiers are short circuit protected. RESET ADDRESS DECODE A0 A1 *RDA *WRA R/W DECODE INPUT REG A 12 OUTPUT DAC A REG A 12 TO AMPLIFIER Careful attention to grounding is important to accurate operation of the DAC8412. This is not because the DAC8412 is more sensitive than other 12-bit DACs, but because with four outputs and two references there is greater potential for ground loops. Since the DAC8412 has no analog ground, the ground must be specified with respect to the reference. *RDD *WRD 12 CS R/W DATA LDAC Reference Configurations Output voltage ranges can be configured as either unipolar or bipolar, and within these choices a wide variety of options exists. The unipolar configuration can be either positive or negative voltage output, and the bipolar configuration can be either symmetrical or nonsymmetrical. *NOTE: THE SIGNALS RDA, WRA, ETC., ARE INTERNAL CONTROL SIGNALS. THEY ARE INCLUDED FOR CLARIFICATION ONLY. Figure 1. I/O Logic Diagram +15V See Figure 1 for a simplified I/O logic diagram. The register select inputs A0 and A1 select individual DAC registers “A” (binary code 00) through “D” (binary code 11). Decoding of the registers is enabled by the CS input. When CS is high no decoding takes place, and neither the writing nor the reading of the input registers is enabled. The loading of the second bank of registers is controlled by the LDAC input. By taking CS low while CS is high, all output registers can be updated simultaneously. Note that the tLWD required pulse width for updating all DACs is a minimum of 170 ns. + V REFH INPUT OP-400 OUTPUT 0.2µF DAC8412 REF10 TRIM OR 10kΩ V REFL DAC8413 +10V OPERATION The R/W input, when enabled by CS, controls the writing to and reading from the input register. Figure 2. Unipolar +10 V Operation Coding +15V Both the DAC-8412 and DAC8413 use binary coding. The output voltage can be calculated by: VOUT = VREFL + 39kΩ (VREFL _VREFL ) * N 6 BALANCE 100kΩ where N is the digital code in decimal. RESET GAIN 100kΩ The RESET function can be used either at power-up or at any time during the DAC’s operation. The RESET function is independent of CS. This pin is active LOW and sets the DAC output registers to either center code for the DAC8412, or zero code for the DAC8413. The reset to center code is most useful when the DAC is configured for bipolar references and an output of zero volts after reset is desired. 3 1 12 6.2Ω V REFH 0.2µF 5 DAC8412 AD688 For ± 10v AD588 For ± 5v OR 14 DAC8413 15 6.2Ω V REFL 0.2µF 8 13 7 1µF ±5 OR ±10V OPERATION Figure 3. Symmetrical Bipolar Operation Supplies Figure 3 (Symmetrical Bipolar Operation) shows the DAC8412 configured for ± 10 volt operation. Note: See the AD688 data sheet for a full explanation of reference operation. Adjustments may not be required for many applications since the AD688 is a very high accuracy reference. However if additional adjustments are required, adjust the DAC8412 full scale first. Begin by loading the digital full-scale code (FFFH), and then adjust the Gain Adjust potentiometer to attain a DAC output voltage of 9.9976 volts. Then, adjust the Balance Adjust to set the center scale output voltage to 0.000 volts. Supplies required are VSS, VDD and VLOGIC. The VSS supply can be set between –15 volts and 0 volts. VDD is the positive supply; its operating range is between +5 and +15 volts. VLOGIC is the digital output reference voltage for the readback function. It is normally connected to +5 volts. This pin is a logic reference input only. It does not supply current to the device. If you are not using the readback function, VLOGIC can be hardwired to VDD. While VLOGIC does not supply current to the DAC8412, it does supply currents to the digital outputs when readback is used. The 0.2 µF bypass capacitors shown at the reference inputs in Figure 3 should be used whenever ± 10 volt references are used. Applications with single references or references to ± 5 volts may not require the 0.2 µF bypassing. The 6.2 Ω resistor in series with the output of the reference amplifier is to keep the amplifier from oscillating with the capacitive load. We have Amplifiers Unlike many voltage output DACs, the DAC8412 features buffered voltage outputs. Each output is capable of both sourcing and sinking 5 mA at ± 10 volts, eliminating the need for external REV. C 4 4096 –7– DAC8412/DAC8413 found that this is large enough to stabilize this circuit. Larger resistor values are acceptable, provided that the drop across the resistor doesn’t exceed a VBE. Assuming a minimum VBE of 0.6 volts and a maximum current of 2.75 mA, then the resistor should be under 200 Ω for the loading of a single DAC8412. Figure 4 shows the DAC8412 configured for –10 volt to zero volt operation. A REF08 with a –10 volt output is connected directly to VREFL for the reference voltage. Single +5 Volt Supply Operation For operation with a +5 volt supply, the reference should be set between 1.0 and +2.5 volts for optimum linearity. Note that lower reference voltages will have greater effects due to noise. Figure 5 shows a REF43 used to supply a +2.5 volt reference voltage. The headroom of the reference and DAC are both sufficient to support a +5 volt supply with ± 5% tolerance. VDD and VLOGIC should be connected to the same supply and separate bypassing to each pin should be used. Using two separate references is not recommended. Having two references could cause different drifts with time and temperature; whereas with a single reference, most drifts will track. Unipolar positive full-scale operation can usually be set with a reference with the correct output voltage. This is preferable to using a reference and dividing down to the required value. For a 10 volt full-scale output, the circuit can be configured as shown in Figure 2. In this configuration the full-scale value is set first by adjusting the 10 kΩ resistor for a full-scale output of 9.9976 volts. +5V 10µF 0.01µF 10kΩ V REFH TRIM GND REF08 OUT INPUT OUTPUT DAC8412 REF43 OR 0.2µF V REFL .01µF V REFH 0.2µF TRIM 10kΩ DAC8413 DAC8412 OR GND V REFL DAC8413 10µF ZERO TO +2.5V OPERATION SINGLE +5V SUPPLY ZERO TO –10V OPERATION –15V Figure 4. Unipolar –10 V Operation Figure 5. +5 V Single Supply Operation +1 0 –1 VDD = +15V VSS = –15V V REFL = –10.0V TA = +25˚C 6 7 8 9 10 11 V REFH – Volts 12 Differential Linearity vs. VREFH VDD = +5V VSS = 0V VREFL = 0V TA = +25˚C +2 MAXIMUM LINEARITY ERROR – LSB MAXIMUM LINEARITY ERROR – LSB MAXIMUM LINEARITY ERROR – LSB Typical Performance Characteristics +1 0 –1 –2 1 2 V REFH – Volts 3 Differential Linearity vs. VREFH –8– 0.3 0.2 VDD = +15V VSS = –15V VREFL = 0V TA = +25˚C 0.1 6 8 10 V REFH – Volts 12 INL vs. VREFH REV. C DAC8412/DAC8413 0 VDD = +5V VSS = 0V VREFL = 0V TA = +25°C –1 1 2 0.3 V DD = +15V VSS = –15V V REFH = +10V V REFL = –10V 0.2 0 X+3σ –0.2 X –0.4 3 200 400 600 800 1000 X–3 σ –0.3 V DD = +15V VSS = –15V V REFH = +10V V REFL = –10V –0.5 0 T = HOURS OF OPERATION AT +125°C Full-Scale Error vs. Time Accelerated by Burn-In 200 400 600 800 1000 T = HOURS OF OPERATION AT +125°C Zero-Scale Error vs. Time Accelerated by Burn-In 0.2 0.3 V DD = +15V VSS = –15V V REFH = +10V V REFL = –10V 0 DAC A ZERO-SCALE ERROR – LSB FULL-SCALE ERROR – LSB X –0.1 –0.7 0 INL vs. VREFH DAC D DAC B –0.4 DAC C –0.6 –75 0 75 TEMPERATURE – °C V DD = +15V VSS = –15V V REFH = +10V V REFL = –10V 0.1 DAC A –0.1 DAC C DAC D –0.3 –0.5 –75 150 Full-Scale Error vs. Temperature DAC B 0 75 TEMPERATURE – °C 150 Zero-Scale Error vs. Temperature Channel-to-Channel Matching (VSUPPLY = ± 15 V) REV. C 0.1 X–3σ –0.6 V REFH – Volts –0.2 X+3 σ ZERO-SCALE ERROR – LSB +1 FULL-SCALE ERROR – LSB MAXIMUM LINEARITY ERROR – LSB 0.4 Channel-to-Channel Matching (VSUPPLY = +5 V) –9– DAC8412/DAC8413 13 V DD = +15V VSS = –15V V REFL = –10V I DD – mA 10 7 4 –7 –3 1 5 V REFH – Volts 9 13 IDD vs. VREFH All DACS High INL vs. Code IVREFH vs. Code Settling Time (Negative) Settling Time (Positive) Positive Slew Rate –10– Negative Slew Rate REV. C DAC8412/DAC8413 GAIN – dB 0 –10 V DD = +15V VSS = –15V V REFH = 0 ±100mV V REFL = –10V DATA BITS = +5V 200mV P–P –30 –50 0 10 100 1k 10k 100k 1M 100 I DD 6 VDD = +15V VSS = –15V 2 –2 I SS –6 –10 –75 10M POWER SUPPLY REJECTION – dB POWER SUPPLY CURRENT – mA 10 FREQUENCY – Hz +PSRR 80 –PSRR 60 +PSRR: VDD = +15V±1VP VSS = –15V –PSRR: VDD = +15V VSS = –15V±1VP VREFH = 10V ALL DATA 0 40 20 0 0 75 150 10 100 TEMPERATURE – °C Small Signal Response 1k 10k 100k FREQUENCY – Hz PSRR vs. Frequency Power Supply Current vs. Temperature 0 30 20 I OUT – mA 10 V DD = +15V VSS = –15V V REFH = +10V V REFL = –10V TA = +25˚C DATA = 000 H 0 –10 –20 –30 0 –25 –20 –15 –10 –5 0 5 10 15 20 25 VOUT – Volts IOUT vs. VOUT OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Position Leadless Chip Carrier (TC Suffix) 0.458 (11.63) 0.442 (11.23) PLANE 2 PLANE 1 0.150 (3.81) REF 0.015 (0.38) MIN 0.075 (1.91) REF 0.093 (2.36) 0.077 (1.96) 0.300 (7.62) REF 0.028 (0.71) 0.022 (0.56) BOTTOM VIEW TOP VIEW 0.050 (1.27) MIN 0.055 (1.40) 0.045 (1.14) 0.100 (2.54) 0.064 (1.63) 0.075 (1.91) REF 0.458 (11.63) MAX SIDE VIEW REV. C 0.088 (2.24) 0.054 (1.37) –11– 45° TYP 0.200 (5.08) BSC 1M DAC8412/DAC8413 28-Lead PLCC (PC Suffix) SEATING PLANE 4 26 PIN 1 IDENTIFIER 5 25 0.430 (10.920) 0.390 (9.910) C1544–24–5/91 0.048 (1.219) x 45° 0.042 (1.067) TOP VIEW 0.050 (1.270) BSC 0.021 (0.533) 0.013 (0.331) 11 0.032 (0.812) 0.026 (0.661) 19 12 18 0.456 (11.582) 0.450 (11.430) 0.020 (0.510) MIN 0.180 (4.51) 0.165 (4.20) 0.495 (12.570) 0.485 (12.320) 28-Lead Cerdip (T Suffix) 0.005 (0.13) MIN 0.098 (2.49) MAX 28 15 0.610 (15.49) 0.500 (12.70) PIN 1 1 14 0.075 (1.91) 1.490 (37.85) MAX 0.620 (15.75) 0.590 (14.99) 0.015 (0.38) 0.225 (5.72) MAX 0.150 (3.81) MIN 0.200 (5.08) 0.120 (3.05) 0.023 (0.58) 0.014 (0.36) 0.100 (2.54) BSC SEATING PLANE 0.070 (1.78) 0.030 (0.76) 0.015 (0.38) 0.008 (0.20) 15° 0° 28-Lead Epoxy DIP (P Suffix) 15 PRINTED IN U.S.A. 28 0.580 (14.73) 0.485 (12.32) PIN 1 1 14 1.565 (39.70) 1.380 (35.10) 0.015 (0.39) MIN 0.250 (6.35) MAX 0.200 (5.08) 0.115 (2.93) 0.022 (0.558) 0.014 (0.36) 0.130 (3.32) MIN 0.100 (2.54) BSC 0.070 (1.78) 0.030 (0.76) –12– 0.625 (15.87) 0.600 (15.24) 0.015 (0.381) 0.008 (0.203) 15° 0° SEATING PLANE REV. C