54191/DM54191/DM74191 Synchronous Up/Down 4-Bit Binary Counter with Mode Control General Description This circuit is a synchronous, reversible, up/down counter. The 191 is a 4-bit binary counter. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change simultaneously when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters. The outputs of the four master-slave flip-flops are triggered on a low-to-high level transition of the clock input, if the enable input is low. A high at the enable input inhibits counting. Level changes at either the enable input or the down/ up input should be made only when the clock input is high. The direction of the count is determined by the level of the down/up input. When low, the counter counts up and when high, it counts down. This counter is fully programmable; that is, the outputs may be preset to either level by placing a low on the load input and entering the desired data at the data inputs. The output will change independent of the level of the clock input. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. The clock, down/up, and load inputs are buffered to lower the drive requirement; which significantly reduces the number of clock drivers, etc., required for long parallel words. Two outputs have been made available to perform the cascading function: ripple clock and maximum/minimum count. The latter output produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock when the counter overflows or underflows. The ripple clock output produces a low-level output pulse equal in width to the low-level portion of the clock input when an overflow or underflow condition exists. The counters can be easily cascaded by feeding the ripple clock output to the enable input of the succeeding counter if parallel clocking is used, or to the clock input if parallel enabling is used. The maximum/minimum count output can be used to accomplish look-ahead for high-speed operation. Features Y Y Y Y Y Y Y Single down/up count control line Count enable control input Ripple clock output for cascading Asynchronously presettable with load control Parallel outputs Cascadable for n-bit applications Alternate Military/Aerospace device (54191) is available. Contact a National Semiconductor Sales Office/ Distributor for specifications. Connection Diagram Dual-In-Line Package TL/F/6562 – 1 Order Number 54191DMQB, 54191FMQB, DM54191J, DM54191W or DM74191N See NS Package Number J16A, N16E or W16A C1995 National Semiconductor Corporation TL/F/6562 RRD-B30M105/Printed in U. S. A. 54191/DM54191/DM74191 Synchronous Up/Down 4-Bit Binary Counter with Mode Control June 1989 Absolute Maximum Ratings (Note) Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V Input Voltage 5.5V Operating Free Air Temperature Range b 55§ C to a 125§ C DM54 and 54 DM74 0§ C to a 70§ C Storage Temperature Range b 65§ C to a 150§ C Recommended Operating Conditions Symbol DM54191 Parameter VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage IOH High Level Output Current IOL Low Level Output Current fCLK Clock Frequency (Note 4) tW Pulse Width (Note 4) DM74191 Units Min Nom Max Min Nom Max 4.5 5 5.5 4.75 5 5.25 2 2 0.8 0.8 V b 0.8 b 0.8 mA 16 0 V V 20 0 Clock 25 25 Load 35 35 16 mA 20 MHz ns tSU Data Setup Time (Note 4) 28 28 ns tH Hold Time (Note 4) 0 0 ns tREL Load Release Time (Note 4) TA Free Air Operating Temperature Electrical Characteristics Symbol 30 b 55 30 125 ns 0 70 over recommended operating free air temperature range (unless otherwise noted) Conditions VI Input Clamp Voltage VCC e Min, II e b12 mA VOH High Level Output Voltage VCC e Min, IOH e Max VIL e Max, VIH e Min VOL Low Level Output Voltage VCC e Min, IOL e Max VIH e Min, VIL e Max II Input Current @ Max Input Voltage VCC e Max, VI e 5.5V IIH High Level Input Current VCC e Max VI e 2.4V Enable 120 Others 40 Low Level Input Current VCC e Max VI e 0.4V Enable b 4.8 Others b 1.6 Short Circuit Output Current VCC e Max (Note 2) DM54 b 20 b 65 DM74 b 18 b 65 Supply Current VCC e Max (Note 3) DM54 65 99 DM74 65 105 IOS ICC Min Typ (Note 1) Parameter IIL §C Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time. Note 3: ICC is measured with all inputs grounded and all outputs open. Note 4: TA e 25§ C and VCC e 5V. 2 2.4 Max Units b 1.5 V 3.4 0.2 V 0.4 V 1 mA mA mA mA mA Switching Characteristics Symbol at VCC e 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load) Parameter From (Input) To (Output) RL e 400X, CL e 15 pF Max Units 20 MHz Min fMAX Maximum Clock Frequency tPLH Propagation Delay Time Low to High Level Output Load to Any Q 33 ns tPHL Propagation Delay Time High to Low Level Output Load to Any Q 70 ns tPLH Propagation Delay Time Low to High Level Output Data to Any Q 22 ns tPHL Propagation Delay Time High to Low Level Output Data to Any Q 70 ns tPLH Propagation Delay Time Low to High Level Output Clock to Ripple Carry 20 ns tPHL Propagation Delay Time High to Low Level Output Clock to Ripple Carry 24 ns tPLH Propagation Delay Time Low to High Level Output Clock to Any Q 24 ns tPHL Propagation Delay Time High to Low Level Output Clock to Any Q 36 ns tPLH Propagation Delay Time Low to High Level Output Clock to Max/Min 42 ns tPHL Propagation Delay Time High to Low Level Output Clock to Max/Min 52 ns tPLH Propagation Delay Time Low to High Level Output Down/Up to Ripple Carry 45 ns tPHL Propagation Delay Time High to Low Level Output Down/Up to Ripple Carry 45 ns tPLH Propagation Delay Time Low to High Level Output Down/Up to Max/Min 33 ns tPHL Propagation Delay Time High to Low Level Output Down/Up to Max/Min 33 ns tPLH Propagation Delay Time Low to High Level Output Enable G to Ripple Carry 24 ns tPHL Propagation Delay Time High to Low Level Output Enable G to Ripple Carry 24 ns 3 Logic Diagram 191 Binary Counter TL/F/6562 – 2 4 Pin (16) e VCC, Pin (8) e GND Timing Diagrams 191 Decade Counter Typical Load, Count, and Inhibit Sequences TL/F/6562 – 3 Physical Dimensions inches (millimeters) 16-Lead Ceramic Dual-In-Line Package (J) Order Number 54191DMQB or DM54191J NS Package Number J16A 5 54191/DM54191/DM74191 Synchronous Up/Down 4-Bit Binary Counter with Mode Control Physical Dimensions inches (millimeters) (Continued) 16-Lead Molded Dual-In-Line Package (N) Order Number DM74191N NS Package Number N16E 16-Lead Ceramic Flat Package (W) Order Number 54191FMQB or DM54191W NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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