74VCXH16373 LOW VOLTAGE 16-BIT D-TYPE LATCH (3-STATE) WITH 3.6V TOLERANT INPUTS AND OUTPUTS PRELIMINARY DATA ■ ■ ■ ■ ■ ■ ■ ■ 3.6V TOLERANT INPUTS AND OUTPUTS HIGH SPEED: tPD = 3.0 ns (MAX.) at VCC = 3.0 to 3.6V tPD = 3.4 ns (MAX.) at VCC = 2.3 to 2.7V POWER-DOWN PROTECTION ON INPUTS AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24 mA (MIN) at VCC = 3.0V |IOH| = IOL = 18 mA (MIN) at VCC = 2.3V OPERATING VOLTAGE RANGE: VCC (OPR) = 2.3V to 3.6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 16373 LATCH-UP PERFORMANCE EXCEEDS 300mA ESD PERFORMANCE: HBM >2000V; MM > 200V T (TSSOP48 Package) ORDER CODES : 74VCXH16373T PIN CONNECTION DESCRIPTION The VCXH16373 is a low voltage CMOS 16-BIT D-TYPE LATCH with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and five-layer metal wiring C2MOS technology. It is ideal for low power and very high speed 2.3 to 3.6V applications; it can be interfaced to 3.6V signal enviroment for both inputs and outputs. These 16 bit D-Type latchs are byte controlled by two latch enable inputs (nLE) and two output enable inputs (OE). While the nLE input is held at a high level, the nQ outputs will follow the data input precisely. When the nLE is taken low, the nQ outputs will be latched precisely at the logic level of D input data. While the (nOE) input is low, the nQ outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. This device is designed to be used with 3 state memory address drivers, etc. Bus hold on data inputs is provided in order to eliminate te need for external pull-up or pull-down resistor. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. December 1999 1/10 74VCXH16373 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION IEC LOGIC SYMBOLS PIN No SYMBOL NAME AND FUNCT ION 1 1OE 2, 3, 5, 6, 8, 9, 11, 12 1Q0 to 1Q7 3 State Outputs 13, 14, 16, 17, 19, 20, 22, 23 2Q0 to 2Q7 3 State Outputs 24 2OE 3 State Output Enable Input (Active LOW) Latch Enable Input 3 State Output Enable Input (Active LOW) 25 2LE 36, 35, 33, 32, 30, 29, 27, 26 2D0 to 2D7 Data Inputs 47, 46, 44, 43, 41, 40, 38, 37 1D0 to 1D7 Data Inputs 48 1LE Latch Enable Input 4, 10, 15, 21, 28, 34, 39, 45 GND Ground (0V) 7, 18, 31, 42 VCC Positive Supply Voltage TRUTH TABLE INPUT S OUTPUTS OE LE D Q H X X Z L L X NO CHANGE * L H L L L H H H X:Don’t care Z: High impedance * Q output are latched at the timewhen the LE input is taken low level. 2/10 74VCXH16373 LOGIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit Supply Voltage -0.5 to + 4.6 V VI DC Input Voltage -0.5 to + 4.6 V VO DC Output Voltage (OFF state) VO DC Output Voltage (High or Low State) (note1) VCC -0.5 to + 4.6 V -0.5 to VCC + 0.5 V IIK DC Input Diode Current - 50 mA IOK DC Output Diode Current (note2) ± 50 mA IO DC Output Source/Sink Current ± 50 mA DC VCC or Ground Current Per Supply Pin ± 100 mA 400 mW ICC orIGND PD Power Dissipation Tstg Storage Temperature TL Lead Temperature (10 sec) -65 to +150 o 300 o C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. 1) IO absolute maximum rating must be observed 2) VO < GND, VO > VCC RECOMMENDED OPERATING CONDITIONS Symbol VCC Value Unit Supply Voltage Parameter 2.3 to 3.6 V -0.3 to 3.6 V VI Input Voltage VO Output Voltage (OFF state) 0 to 3.6 V VO Output Voltage (High or Low State) 0 to VCC V IOH, IOL High or Low Level Output Current (VCC = 3.0 to 3.6V) ± 24 mA IOH, IOL High or Low Level Output Current (VCC = 2.3 to 2.7V) ± 18 mA Top dt/dv Operating Temperature: Input Transition Rise or Fall Rate (V CC = 3.0V) (note 1) -40 to+85 0 to 10 o C ns/V 1) VIN from0.8V to 2.0V, VCC = 3.0V 3/10 74VCXH16373 DC SPECIFICATIONS (2.7V < VCC ≤ 3.6V unless otherwise specified) Symb ol Parameter Test Co nditi ons VIH High Level Input Voltage VIL Low Level Input Voltage VOH High Level Output Voltage Min. VCC-0.2 IO=-12 mA 2.2 IO=-18 mA 2.4 3.0 IO=-24 mA 2.2 2.7 to 3.6 IO=100 µA 0.2 IO=12 mA 0.4 IO=18 mA 0.4 IO=24 mA 0.55 VI = VIH or VIL 3.0 3.0 II(HOLD) Input Leakage Current Input Hold Current IOZ 3 State Output Leakage Current Ioff Power Off Leakage Current ICC Quiescent Supply Current ∆ICC ICC incr. per input V IO=-100 µA VI = VIH or VIL 2.7 II Max. 0.8 2.7 to 3.6 3.0 Low Level Output Voltage Un it 2.0 2.7 to 3.6 2.7 VOL Value -40 to 85 o C V CC (V) 2.7 to 3.6 3 V ±5 VI = VCC orGND VI = 0.8 V 75 VI = 2 V -75 V V µA µA 3.6 VI = 0 to 3.6 V ±500 2.7 to 3.6 VI = VIH orVIL VO = 0 to 3.6V ±10 µA 0 VI orVO = 0 to 3.6V 10 µA µA 2.7 to 3.6 2.7 to 3.6 VI = VCC orGND 20 VI orVO = VCC to 3.6 V ±20 VIH = VCC -0.6V 750 µA DC SPECIFICATIONS (2.3V < VCC ≤ 2.7V unless otherwise specified) Symb ol Parameter Test Co nditi ons VIH High Level Input Voltage VIL Low Level Input Voltage VOH High Level Output Voltage Min. IO=-100 µA VI = VIH or VIL 2.3 VOL Low Level Output Voltage 2.3 to 2.7 2.3 2.3 II II(HOLD) Input Leakage Current Input Hold Current IOZ 3 State Output Leakage Current Ioff Power Off Leakage Current ICC Quiescent Supply Current 4/10 2.3 to 2.7 2.3 Max. V 0.7 2.3 to 2.7 2.3 Un it 1.6 2.3 to 2.7 2.3 Value -40 to 85 o C V CC (V) VI = VIH or VIL V VCC-0.2 IO=-6 mA 2.0 IO=-12 mA 1.8 IO=-18 mA 1.7 V IO=100 µA 0.2 IO=12 mA 0.4 IO=18 mA 0.6 ±5 VI = VCC orGND VI = 0.7 V 45 VI = 1.7 V -45 V µA µA 2.3 to 2.7 VI = VIH orVIL VO = 0 to 3.6V ±10 µA 0 VI orVO = 0 to 3.6V 10 µA VI = VCC orGND 20 VI orVO = VCC to 3.6 V ±20 µA 2.3 to 2.7 74VCXH16373 DYNAMIC SWITCHING CHARACTERISTICS (Ta = 25oC, Input tr = tf = 2.0ns, CL = 30pF, RL = 500Ω) Symb ol Parameter Test Con dition s Value VOLP VOLV VOHV Dynamic Low Voltage Quiet Output (note 1, 3) 2.5 Dynamic Low Voltage Quiet Output (note 1, 3) 2.5 Dynamic High Voltage Quiet Output (note 2, 3) 2.5 Un it T A = 25 o C V CC (V) Min . 3.3 3.3 3.3 T yp. VIL = 0 V VIH = VCC 0.6 VIL = 0 V VIH = VCC -0.6 VIL = 0 V VIH = VCC 1.9 Max. V 0.8 V -0.8 V 2.2 1) Number ofoutputs defined as ”n”. Measured with”n-1” outputs switching from HIGH to LOW or LOW t o HIGH. The remaining output is measured in the LOW state. 2) Number ofoutputs defined as ”n”. Measured with”n-1” outputs switching from HIGH to LOW or LOW t o HIGH. The remaining output is measured in the HIGH state. 3) Parameters guaranteed by design. AC ELECTRICAL CHARACTERISTICS (CL = 30 pF, RL = 500 Ω, Input tr = tf = 2.0 ns) Symb ol Parameter V CC (V) tPLH tPHL Propagation Delay Time Dn to Qn tPLH tPHL Propagation Delay Time LE to Qn tPZL tPZH Output Enable Time tPLZ tPHZ Output Disable Time ts Setup Time, HIGH or LOW level Dn to LE th Hold Time, HIGH or LOW level Dn to LE tw LE Pulse Width, HIGH tOSLH tOSHL Output to Output Skew Time (note 1, 2) Test Con dition Waveform 2.3 to 2.7 3.0 to 3.6 2.3 to 2.7 3.0 to 3.6 2.3 to 2.7 3.0 to 3.6 2.3 to 2.7 Value -40 to 85 o C Min. Max. 3 1 2 2 3.0 to 3.6 2.3 to 2.7 1 3.0 to 3.6 2.3 to 2.7 3.0 to 3.6 2.3 to 2.7 3.0 to 3.6 1.0 0.8 1.0 0.8 1.0 0.8 1.0 3.4 3.0 3.9 3.0 4.6 3.5 3.8 0.8 1.5 3.5 1.0 1.0 1.5 1.5 1 ns ns ns ns ns 1.5 1 Un it ns ns 2.3 to 2.7 3.0 to 3.6 0.5 0.5 ns 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any twooutputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tpHLn|) 2) Parameter guaranteed by design CAPACITIVE CHARACTERISTICS Symb ol Parameter Test Co nditi ons Valu e Un it T A = 25 oC V CC (V) Min. T yp. Max. Input Capacitance 2.5 or 3.3 VIN = 0V or VCC 6 pF COUT Output Capacitance 2.5 or 3.3 VIN = 0V or VCC 7 pF CPD Power Dissipation Capacitance (note 1) 2.5 or 3.3 fIN = 10MHz VIN = 0V or VCC 20 pF CIN 1) CPD isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. Average operting current can be obtained by the following equation. I CC(opr) = CPD • VCC • fIN + ICC/16 (per circuit) 5/10 74VCXH16373 TEST CIRCUIT T EST SW IT CH tPLH , tPHL Open tPZL , tPLZ (VCC = 3.0 to 3.6V) 6V tPZL , tPLZ (VCC = 2.3 to 2.7V) 2VCC tPZH , tPHZ GND CL = 30 pF or equivalent (includes jigand probe capacitance) RL = R1 = 500Ω orequivalent RT = ZOUT of pulse generator (typically 50Ω) WAVEFORM SYMBOL VALUES Symbo l VIH 6/10 V CC 3.0 to 3.6V 2.3 to 2.7V 2.7V VCC VM 1.5V VCC/2 VX VOL + 0.3V VOL + 0.15V VY VOH - 0.3V VOH - 0.15V 74VCXH16373 WAVEFORM 1: LE TO Qn PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH, Dn TO LE SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) 7/10 74VCXH16373 WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle) WAVEFORM 3: PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle) 8/10 74VCXH16373 TSSOP48 MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. A MIN. TYP. 1.1 MAX. 0.433 A1 0.05 0.10 0.15 0.002 0.004 0.006 A2 0.85 0.9 0.95 0.335 0.354 0.374 b 0.17 0.27 0.0067 0.011 c 0.09 0.20 0.0035 0.0079 D 12.4 12.5 12.6 0.408 0.492 0.496 E 7.95 8.1 8.25 0.313 0.319 0.325 E1 6.0 6.1 6.2 0.236 0.240 0.244 e 0.5 BSC 0.0197 BSC K 0o 4o 8o 0o 4o 8o L 0.50 0.60 0.70 0.020 0.024 0.028 A A2 A1 b K e L E c D E1 PIN 1 IDENTIFICATION 1 9/10 74VCXH16373 Information furnished is believed to be accurate and reliable. However, STMicroelectronic s assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems withoutexpress written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 1999 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com . 10/10