Revised August 2001 74VCX16374 Low Voltage 16-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs General Description Features The VCX16374 contains sixteen non-inverting D-type flipflops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock (CP) and output enable (OE) are common to each byte and can be shorted together for full 16-bit operation. ■ 1.65V–3.6V VCC supply operation The 74VCX16374 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O compatibility up to 3.6V. 3.9 ns max for 2.3V to 2.7V VCC The 74VCX16374 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. ■ 3.6V tolerant inputs and outputs ■ tPD 3.0 ns max for 3.0V to 3.6V VCC 7.8 ns max for 1.65V to 1.95V VCC ■ Power-off high impedance inputs and outputs ■ Supports live insertion and withdrawal (Note 1) ■ Static Drive (IOH/IOL) ±24 mA @ 3.0V VCC ±18 mA @ 2.3V VCC ±6 mA @ 1.65V VCC ■ Uses patented noise/EMI reduction circuitry ■ Latch-up performance exceeds 300 mA ■ ESD performance: Human body model > 2000V Machine model > 200V ■ Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number Package Number 74VCX16374GX (Note 2) 74VCX16374MTD (Note 3) BGA54A MTD48 Package Descriptions 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL] 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Note 2: BGA package available in Tape and Reel only. Note 3: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol © 2001 Fairchild Semiconductor Corporation DS500066 www.fairchildsemi.com 74VCX16374 Low Voltage 16-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs October 1997 74VCX16374 Connection Diagrams Pin Descriptions Pin Assignment for TSSOP Pin Names Description OEn Output Enable Input (Active LOW) CPn Clock Pulse Input I0–I15 Inputs O0–O15 Outputs NC No Connect FBGA Pin Assignments 1 2 3 4 5 A O0 NC OE1 CP1 NC I0 B O2 O1 NC NC I1 I2 C O4 O3 VCC VCC I3 I4 D O6 O5 GND GND I5 I6 E O8 O7 GND GND I7 I8 F O10 O9 GND GND I9 I10 I12 G O12 O11 VCC VCC I11 H O14 O13 NC NC I13 I14 J O15 NC OE2 CP2 NC I15 Truth Tables Pin Assignment for FBGA Inputs CP1 Outputs OE1 I0–I7 O0–O7 L H H L L L L L X O0 X H X Z Inputs CP2 (Top Thru View) Outputs OE2 I8–I15 O8–O15 L H H L L L L L X O0 X H X Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial (HIGH or LOW, inputs may not float) Z = High Impedance O0 = Previous O0 before HIGH-to-LOW of CP www.fairchildsemi.com 6 2 flip-flop will store the state of their individual I inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CPn) transition. With the Output Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operations of the OEn input does not affect the state of the flip-flops. The 74VCX16374 consists of sixteen edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Each clock has a buffered clock and buffered Output Enable common to all flip-flops within that byte. The description which follows applies to each byte. Each Logic Diagram Byte 1 (0:7) Byte 2 (8:15) Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74VCX16374 Functional Description 74VCX16374 Absolute Maximum Ratings(Note 4) Supply Voltage (VCC ) −0.5V to +4.6V DC Input Voltage (VI) −0.5V to +4.6V Recommended Operating Conditions (Note 6) Power Supply Output Voltage (VO) Operating −0.5V to +4.6V Outputs 3-STATED Outputs Active (Note 5) DC Input Diode Current (IIK) VI < 0V 1.65V to 3.6V Data Retention Only −0.5V to VCC +0.5V −50 mA Output Voltage (VO) DC Output Diode Current (IOK) Output in Active States VO < 0V −50 mA Output in “OFF” State VO > VCC +50 mA Output Current in IOH/IOL DC Output Source/Sink Current ±50 mA (IOH/IOL) Storage Temperature Range (TSTG) 0V to VCC 0.0V to 3.6V VCC = 3.0V to 3.6V ±24 mA VCC = 2.3V to 2.7V ±18 mA VCC = 1.65V to 2.3V DC VCC or GND Current per Supply Pin (ICC or GND) 1.2V to 3.6V −0.3V to +3.6V Input Voltage ±100 mA ±6 mA Free Air Operating Temperature (TA) −65°C to +150 °C −40°C to +85°C Minimum Input Edge Rate (∆t/∆V) VIN = 0.8V to 2.0V, VCC = 3.0V 10 ns/V Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 5: IO Absolute Maximum Rating must be observed. Note 6: Floating or unused inputs must be held HIGH or LOW. DC Electrical Characteristics (2.7V < VCC ≤ 3.6V) Symbol Parameter Conditions VCC (V) Min 2.0 VIH HIGH Level Input Voltage 2.7 − 3.6 VIL LOW Level Input Voltage 2.7 − 3.6 VOH HIGH Level Output Voltage VOL LOW Level Output Voltage II Input Leakage Current IOZ 3-STATE Output Leakage Max Units 0.8 V V IOH = −100 µA 2.7 − 3.6 VCC − 0.2 V IOH = −12 mA 2.7 2.2 V IOH = −18 mA 3.0 2.4 V IOH = −24 mA 3.0 2.2 IOL = 100 µA 2.7 − 3.6 0.2 V IOL = 12 mA 2.7 0.4 V IOL = 18 mA 3.0 0.4 V IOL = 24 mA 3.0 0.55 V 0 ≤ VI ≤ 3.6V 2.7 − 3.6 ±5.0 µA 2.7 − 3.6 ±10 µA µA 0 ≤ VO ≤ 3.6V VI = VIH or VIL V IOFF Power-OFF Leakage Current 0 ≤ (VI, VO) ≤ 3.6V 0 10 ICC Quiescent Supply Current VI = VCC or GND 2.7 − 3.6 20 µA VCC ≤ (VI, VO) ≤ 3.6V (Note 7) 2.7 − 3.6 ±20 µA VIH = VCC −0.6V 2.7 − 3.6 750 µA ∆ICC Increase in ICC per Input Note 7: Outputs disabled or 3-STATE only. www.fairchildsemi.com 4 Symbol Parameter Conditions V CC (V) Min 1.6 VIH HIGH Level Input Voltage 2.3 − 2.7 VIL LOW Level Input Voltage 2.3 − 2.7 VOH HIGH Level Output Voltage VOL LOW Level Output Voltage II Input Leakage Current IOZ 3-STATE Output Leakage IOH = −100 µA 2.3 − 2.7 Max Units V 0.7 VCC − 0.2 V V IOH = −6 mA 2.3 2.0 V IOH = −12 mA 2.3 1.8 V 1.7 IOH = −18 mA 2.3 IOL = 100 µA 2.3 − 2.7 0.2 V IOL = 12 mA 2.3 0.4 V V IOL = 18 mA 2.3 0.6 V 0 ≤ VI ≤ 3.6V 2.3 − 2.7 ±5.0 µA 2.3 − 2.7 ±10 µA 0 ≤ VO ≤ 3.6V VI = V IH or VIL IOFF Power-OFF Leakage Current 0 ≤ (VI, VO) ≤ 3.6V 0 10 µA ICC Quiescent Supply Current VI = V CC or GND 2.3 − 2.7 20 µA VCC ≤ (VI, VO) ≤ 3.6V (Note 8) 2.3 − 2.7 ±20 µA Max Units Note 8: Outputs disabled or 3-STATE only. DC Electrical Characteristics (1.65V ≤ VCC < 2.3V) Symbol Parameter Conditions VCC (V) Min 0.65 × VCC VIH HIGH Level Input Voltage 1.65 - 2.3 VIL LOW Level Input Voltage 1.65 - 2.3 VOH HIGH Level Output Voltage VOL LOW Level Output Voltage II Input Leakage Current 0 ≤ VI ≤ 3.6V IOZ 3-STATE Output Leakage 0 ≤ VO ≤ 3.6V IOH = −100 µA 1.65 - 2.3 VCC − 0.2 IOH = −6 mA 1.65 1.25 IOL = 100 µA 1.65 - 2.3 IOL = 6 mA VI = V IH or VIL V 0.35 × VCC V V V 0.2 V 1.65 0.3 V 1.65 - 2.3 ±5.0 µA 1.65 - 2.3 ±10 µA IOFF Power-OFF Leakage Current 0 ≤ (VI, VO) ≤ 3.6V 0 10 µA ICC Quiescent Supply Current VI = V CC or GND 1.65 - 2.3 20 µA VCC ≤ (VI, VO) ≤ 3.6V (Note 9) 1.65 - 2.3 ±20 µA Note 9: Outputs disabled or 3-STATE only. 5 www.fairchildsemi.com 74VCX16374 DC Electrical Characteristics (2.3V ≤ VCC ≤ 2.7V) 74VCX16374 AC Electrical Characteristics (Note 10) TA = −40°C to +85°C, CL = 30 pF, RL = 500Ω Symbol Parameter VCC = 3.3V ± 0.3V Min VCC = 2.5V ± 0.2V Max Min Max 200 VCC = 1.8V ± 0.15V Min Max 100 Units fMAX Maximum Clock Frequency 250 tPHL, tPLH Propagation Delay CP to On 0.8 3.0 1.0 3.9 1.5 7.8 ns tPZL, tPZH Output Enable Time 0.8 3.5 1.0 4.6 1.5 9.2 ns tPLZ, tPHZ Output Disable Time 0.8 3.5 1.0 3.8 1.5 6.8 ns tS Setup Time 1.5 1.5 2.5 ns tH Hold Time 1.0 1.0 1.0 ns tW Pulse Width 1.5 1.5 4.0 ns tOSHL Output to Output Skew tOSLH (Note 11) 0.5 MHz 0.5 0.75 ns Note 10: For CL = 50PF, add approximately 300 ps to the AC maximum specification. Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Dynamic Switching Characteristics Symbol VOLP VOLV VOHV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL Quiet Output Dynamic Valley VOH Conditions CL = 30 pF, VIH = VCC, VIL = 0V CL = 30 pF, VIH = VCC, VIL = 0V CL = 30 pF, VIH = VCC, VIL = 0V V CC (V) TA = +25°C Typical 1.8 0.25 2.5 0.6 3.3 0.8 1.8 −0.25 2.5 −0.6 3.3 −0.8 1.8 1.5 2.5 1.9 3.3 2.2 Units V V V Capacitance Symbol Parameter Conditions TA = +25°C Typical Units CIN Input Capacitance VCC = 1.8V, 2.5V or 3.3V, VI = 0V or VCC 6 pF COUT Output Capacitance VI = 0V or VCC, VCC = 1.8V, 2.5V or 3.3V 7 pF CPD Power Dissipation Capacitance 20 pF VI = 0V or VCC, f = 10 MHz, VCC = 1.8V, 2.5V or 3.3V www.fairchildsemi.com 6 74VCX16374 AC Loading and Waveforms TEST SWITCH tPLH, tPHL Open tPZL, tPLZ 6V at VCC = 3.3 ± 0.3V; VCC x 2 at VCC = 2.5 ± 0.2V; 1.8V ± 0.15V tPZH, tPHZ GND FIGURE 1. AC Test Circuit FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic FIGURE 2. Waveform for Inverting and Non-Inverting Functions FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic FIGURE 6. Setup Time, Hold Time and Recovery Time for Low Voltage Logic FIGURE 5. Propagation Delay, Pulse Width and trec Waveforms Symbol VCC 3.3V ± 0.3V 2.5V ± 0.2V 1.8V ± 0.15V Vmi 1.5V VCC/2 VCC/2 Vmo 1.5V VCC/2 VCC/2 VX VOL +0.3V VOL +0.15V VOL +0.15V VY VOH −0.3V VOH −0.15V VOH −0.15V 7 www.fairchildsemi.com 74VCX16374 Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A www.fairchildsemi.com 8 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Body Width Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 9 www.fairchildsemi.com 74VCX16374 Low Voltage 16-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued)