Revised March 1999 74VHC240 Octal Buffer/Line Driver with 3-STATE Outputs General Description The VHC240 is an advanced high speed CMOS octal bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The VHC240 is an inverting 3-STATE buffer having two active-LOW output enables. This device is designed to drive buslines or buffer memory address registers. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This cir- cuit prevents device destruction due to mismatched supply and input voltages. Features ■ High Speed: tPD = 3.6ns (typ) at TA = 25°C ■ Low power dissipation: ICC = 4 µA (max) @ TA = 25°C ■ High noise immunity: VNIH = VNIL = 28% VCC (min) ■ Power down protection is provided on all inputs ■ Low noise: VOLP = 0.9V (max) ■ Pin and function compatible with 74HC240 Ordering Code: Order Number Package Number 74VHC240M 74VHC240SJ 74VHC240MTC 74VHC240N M20B M20D MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description OE1, OE2 3-STATE Output Enable Inputs I0–I7 Inputs O0–O7 Outputs 3-STATE Outputs © 1999 Fairchild Semiconductor Corporation DS011506.prf www.fairchildsemi.com 74VHC240 Octal Buffer/Line Driver with 3-STATE Outputs October 1992 74VHC240 Truth Tables Inputs Outputs OE1 In (Pins 12, 14, 16, 18) L L H L H L H X Z OE1 In (Pins 3, 5, 7, 9) L L H L H L H X Z Inputs Outputs H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance www.fairchildsemi.com 2 Supply Voltage (VCC) −0.5V to +7.0V DC Input Voltage (VIN) −0.5V to +7.0V Recommended Operating Conditions (Note 2) −0.5V to VCC + 0.5V DC Output Voltage (VOUT) Supply Voltage (VCC) 2.0V to 5.5V Input Voltage (VIN) 0V to +5.5V Input Diode Current (IIK) −20 mA Output Voltage (VOUT) Output Diode Current (IOK) ±20 mA Operating Temperature (TOPR) DC Output Current (IOUT) ±25 mA Input Rise and Fall Time (tr, tf) DC VCC /GND Current (ICC ) ±75 mA VCC = 3.3V ± 0.3V 0 ns/V ∼ 100 ns/V −65°C to +150°C VCC = 5.0V ± 0.5V 0 ns/V ∼ 20 ns/V Storage Temperature (TSTG) Lead Temperature (TL) (Soldering, 10 seconds) 0V to VCC −40°C to +85°C Note 1: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables.Fairchild does not recommend operation outside databook specifications. 260°C Note 2: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH HIGH Level Input Voltage VIL VOL Typ TA = −40°C to +85°C Max Min 2.0 1.50 1.50 0.7 VCC 0.7 VCC Max 2.0 0.50 0.50 0.3 VCC 0.3 VCC HIGH Level 2.0 1.9 2.0 1.9 Output Voltage 3.0 2.9 3.0 2.9 4.5 4.4 4.5 4.4 3.0 2.58 2.48 4.5 3.94 3.80 LOW Level Output 2.0 0.0 0.1 Units Conditions V 3.0 − 5.5 Voltage IOZ TA = 25°C Min 3.0 − 5.5 LOW Level Input Voltage VOH VCC (V) Parameter V VIN = VIH IOH = −50 µA V or VIL IOH = −4 mA V 3.0 0.0 0.1 0.1 4.5 0.0 0.1 0.1 IOH = −8 mA VIN = VIH IOL = 50 µA 0.1 V or VIL IOL = 4 mA 3.0 0.36 0.44 4.5 0.36 0.44 5.5 ±0.25 ±2.5 µA VIN = VIH or VIL 0 − 5.5 ±0.1 ±1.0 µA VIN = 5.5V or GND 5.5 4.0 40.0 µA VIN = VCC or GND 3-STATE Output V IOL = 8 mA VOUT = VCC or GND Off-State Current IIN Input Leakage Current ICC Quiescent Supply Current Noise Characteristics Symbol Parameter TA = 25°C VCC (V) Typ Limits VOLP (Note 3) Quiet Output Maximum Dynamic VOL 5.0 0.6 0.9 VOLV (Note 3) Quiet Output Minimum Dynamic VOL 5.0 −0.6 −0.9 VIHD (Note 3) Minimum HIGH Level Dynamic Input Voltage VILD (Note 3) Maximum LOW Level Dynamic Input Voltage 5.0 3.5 5.0 1.5 Units Conditions V CL = 50 pF V CL = 50 pF V CL = 50 pF V CL = 50 pF Note 3: Parameter guaranteed by design. 3 www.fairchildsemi.com 74VHC240 Absolute Maximum Ratings(Note 1) 74VHC240 AC Electrical Characteristics Symbol Parameter tPLH Propagation tPHL Delay Time VCC (V) TA = 25°C Min 3.3 ± 0.3 5.0 ± 0.5 tPZL 3-STATE tPZH Output Enable Time 3.3 ± 0.3 5.0 ± 0.5 TA = −40°C to +85°C Typ Max Min Max 5.3 7.5 1.0 9.0 7.8 11.0 1.0 12.5 3.6 5.5 1.0 6.5 5.1 7.5 1.0 8.5 6.6 10.6 1.0 12.5 9.1 14.1 1.0 16.0 4.7 7.3 1.0 8.5 6.2 9.3 1.0 10.5 10.3 14.0 1.0 16.0 9.2 1.0 10.5 tPLZ 3-STATE 3.3 ± 0.3 tPHZ Output Disable Time 5.0 ± 0.5 tOSLH Output to 3.3 ± 0.3 1.5 1.5 tOSHL Output Skew 5.0 ± 0.5 1.0 1.0 10 10 6.7 Units Conditions CL = 15 pF ns CL = 50 pF CL = 15 pF ns ns CL = 50 pF RL = 1 kΩ CL = 50 pF CL = 15 pF ns ns ns CL = 15 pF CL = 50 pF RL = 1 kΩ CL = 50 pF CL = 50 pF (Note 4) CL = 50 pF CL = 50 pF CIN Input Capacitance 4 pF VCC = Open COUT Output Capacitance 6 pF VCC = 5.0V CPD Power Dissipation 17 pF (Note 5) Capacitance Note 4: Parameter guaranteed by design. tOSLH = |tPLHmax − tPLHmin|; tOSHL = |tPHLmax − tPHLmin| Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr.) = CPD * VCC * fIN + ICC/8 (per bit). www.fairchildsemi.com 4 74VHC240 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Package Number M20B 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 5 www.fairchildsemi.com 74VHC240 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 www.fairchildsemi.com 6 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N20A LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 74VHC240 Octal Buffer/Line Driver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued)