BB XTR111

XTR111
XRT1
11
SBOS375 − NOVEMBER 2006
Precision Voltage-to-Current
Converter/Transmitter
FEATURES
DESCRIPTION
D EASY-TO-DESIGN INPUT/OUTPUT RANGES:
The XTR111 is a precision voltage-to-current converter
designed for the standard 0mA−20mA or 4mA−20mA
analog signals, and can source up to 36mA. The ratio
between input voltage and output current is set by the
single resistor RSET. The circuit can also be modified for
voltage output.
0mA−20mA, 4mA−20mA, 5mA−25mA
AND VOLTAGE OUTPUTS
NONLINEARITY: 0.002%
LOW OFFSET DRIFT: 1µV/5C
ACCURACY: 0.015%
SINGLE-SUPPLY OPERATION
WIDE SUPPLY RANGE: 7V TO 44V
OUTPUT ERROR FLAG (EF)
D
D
D
D
D
D
D OUTPUT DISABLE (OD)
D ADJUSTABLE VOLTAGE REGULATOR:
3V TO 15V
An external P-MOSFET transistor ensures high output
resistance and a broad compliance voltage range
extending from 2V below the supply voltage, VVSP, to
voltages well below GND.
The adjustable 3V to 15V sub-regulator output provides
the supply voltage for additional circuitry.
The XTR111 is available in a DFN surface-mount package.
APPLICATIONS
D UNIVERSAL VOLTAGE-CONTROLLED
24V
CURRENT SOURCE
1
D CURRENT OR VOLTAGE OUTPUT FOR
3-WIRE SENSOR SYSTEMS
PLC OUTPUT PROGRAMMABLE DRIVER
D
D CURRENT-MODE SENSOR EXCITATION
VSP
XTR111
REGF
5
Regulator
Out
I−Mirror
OD
9
EF
8
IS
2
VG
3
G
Output Disable
Output Failure
REGS
4
3V
S
D
ISET
Signal
Input 6
Load
IOUT
0mA to 20mA
4mA to 20mA
VIN
(± Load Ground)
GND
10
SET
7
RSET
IOUT = 10
( RV )
VIN
SET
IOUT = 10 • ISET
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All other trademarks are the property of their respective owners.
Copyright  2006, Texas Instruments Incorporated
! ! www.ti.com
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SBOS375 − NOVEMBER 2006
ABSOLUTE MAXIMUM RATINGS(1)(2)
Power Supply Voltage, VVSP . . . . . . . . . . . . . . . . . . . . . . . . . . +44V
Voltage at SET(3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5V to +14V
Voltage at IS(3, 5) . . . . . . . . . . . . . . (VVSP) − 5.5V to (VVSP) + 0.5V
Voltage at REGS, REGF, VIN, OD, EF . . −0.5V to (VVSP) + 0.5V
Voltage at REGF, VG . . . . . . . . . . . . . . . . . −0.5V to (VVSP) + 0.5V
Current into any pin(3, 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25mA
Output Short-Circuit Duration(5):
VG . . . . . . . . . . . . . . . . . . . . . Continuous to common and VVSP
REGF . . . . . . . . . . . . . . . . . . . Continuous to common and VVSP
Operating Temperature Range . . . . . . . . . . . . . . . −55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . . . . . −65°C to +150°C
Electrostatic Discharge Rating (HBM) . . . . . . . . . . . . . . . . . 2000V
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not supported.
(2) Refer to the Package Option Addendum at the end of this
document for lead temperature ratings.
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
PACKAGE
MARKING
XTR111
DFN-10
DRC
BSV
(1) For the most current package and ordering information, see the
Package Option Addendum at the end of this document, or see
the TI web site at www.ti.com.
PIN DESCRIPTIONS
PIN
(3) Input terminals are diode-clamped to the power-supply rails.
Input signals that can swing more than 0.5V beyond the supply
rails must be current limited.
NAME
FUNCTION
1
VSP
2
IS
Positive Supply
Source Connection
Gate Drive
(4) The IS pin can source up to the output current-limit under normal
operating conditions.
3
VG
4
REGS
Regulator Sense
(5) See text in Application Section regarding safe voltage ranges
and currents.
5
REGF
Regulator Force
6
VIN
Input Voltage
7
SET
Transconductance Set
8
EF
Error Flag (Active Low)
9
OD
Output Disable (Active High)
10
GND
Negative Supply
Pad
Pad
Exposed Thermal Pad must be connected
to GND
PIN CONFIGURATIONS
TOP VIEW
DFN
VSP
1
IS
2
VG
3
REGS
4
REGF
5
Exposed
Thermal
Die Pad
on
Underside.
(Must be
connected
to GND)
DFN−10
Pad
2
10
GND
9
OD
8
EF
7
SET
6
VIN
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SBOS375 − NOVEMBER 2006
ELECTRICAL CHARACTERISTICS
Boldface limits apply over the temperature range, TA = −40°C to +85°C.
All specifications at TA = +25°C, VVSP = +24V, RSET = 2.0kΩ; REGF connected to REGS; OD = Low, External FET connected, unless otherwise noted.
XTR111
PARAMETER
TRANSMITTER
Transfer Function
Specified Output Current
Input Impedance (VIN)
Input Bias Current (VIN)
Input Offset Voltage(2)
vs Temperature
Input Voltage Range(5)
Noise, Referred to Input(2)
Dynamic Response
IOS
Specified Performance(1)
Derated Performance(2)
0.1
From Drain of QEXT(4)
OD = high
VVIN = 20mV
2.4/30
15
0.3
0.1 to 25mA
0.1 to 36mA
IOUT = 4mA(1)
(1)
(1)
IB
VOS
MAX
UNITS
25
mA
mA
mA
% of Span
% of Span
% of Span
% of Span/°C
% of Span/V
% of Span
ppm/°C
% of Span/V
GΩ
µA
0.02
0.02
0.001
0.005
0.1
25
1.5
1
VVIN
0.1Hz to 10Hz; IOUT = 4mA
RLOAD = 5kΩ
0 to 12
2.5
See Dynamic Performance Section
2.85
0.6mA to 5mA
RLOAD = 5kΩ
3.0
30
0.1
0.8
3
0.01
3.15
5
5
21
DIGITAL INPUT (OD)
VIL Low-Level Threshold
VIH High-Level Threshold
Internal Pull-up Current
0.6
1.8
VOD < 5.5V
DIGITAL OUTPUT (EF)
IOH Leakage Current (Open Drain)
VOL Low-Level Output Voltage
IOL Current to 400mV Level
4
1
IEF = 2.2mA
VEF = 400mV
0.8
2
+8
IQ
+40
+7 to +44
450
IOUT = 0mA
TEMPERATURE RANGE
Specified Range
Operating Range
Package Thermal Impedance, qJA
DFN
(1)
(2)
(3)
(4)
(5)
TYP
0 to 36
42 ± 6
0.002
0.004
0.002
0.0002
0.0001
0.015
5
0.0001
>1
<1
8 to 40V Supply
0.1mA to 25mA
V-Regulator Output (REGF)
Voltage Reference(2)
vs Temperature(2)
vs Supply(2)
Bias Current into REGS(2)
Load Regulation
Supply Regulation(2)
Output Current
Short-Circuit Output Current
POWER SUPPLY
Specified Voltage Range
Operating Voltage
Quiescent Current(2)
MIN
IOUT = 10 • VVIN/RSET
IOUT
Current Limit for Output Current
Nonlinearity, IOUT/ISET(2, 3)
Offset Current
vs Temperature
vs Supply, VVSP
Span Error, IOUT/ISET(2)
vs Temperature(2)
vs Supply
Output Resistance
Output Leakage
CONDITION
−40
−55
70
GΩ/pF
nA
mV
µV/°C
V
µVPP
V
ppm/5C
mV/V
µA
mV/mA
mV/V
mA
mA
V
V
µA
µA
V
mA
550
V
V
µA
+85
+125
°C
°C
°C/W
Includes input amplifier, but excludes RSET tolerance.
See Typical Characteristics.
Span is the change in output current resulting from a full−scale change in input voltage.
Within compliance range limited by (+VVSP − 2V) +VDS required for linear operation of QEXT.
See Application Information, Input Voltage section.
3
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SBOS375 − NOVEMBER 2006
TYPICAL CHARACTERISTICS
At TA = +25°C and VVSP = +24V, unless otherwise noted.
QUIESCENT CURRENT vs TEMPERATURE
700
530
650
510
Quiescent Current (µA)
Quiescent Current (µA)
QUIESCENT CURRENT vs SUPPLY VOLTAGE
550
490
470
450
430
410
390
600
550
500
450
400
350
370
300
350
5
10
15
20
25
30
35
40
−75
45
−50
−25
See Applications Information,
Dynamic Performance
75
100
125
RSET = 2kΩ, RLOAD = 2kΩ
RSET = 2kΩ, No Bypass Cap
120
20
100
RSET = 2kΩ, RLOAD = 600Ω
10
PSRR (dB)
Gain (dB)
50
140
30
RSET = 2kΩ, RLOAD = 200Ω
−10
80
60
40
−20
20
−30
−40
25
POWER−SUPPLY REJECTION RATIO vs FREQUENCY
GAIN vs FREQUENCY
40
0
0
Temperature (_C)
Supply Voltage (V)
Gain = VLOAD/VVIN
1k
10k
0
100k
1M
10
10M
100
0.1Hz to 10Hz NOISE, RTI
10k
100k
1M
INPUT−REFERRED NOISE SPECTRUM
100µ
IOUT = 4mA
I OUT = 2mA
IR Noise (VRMS /√Hz)
1µV/div
1k
Frequency (Hz)
Frequency (Hz)
10µ
1µ
100n
10n
1s/div
1
10
100
1k
Frequency (Hz)
4
10k
100k
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SBOS375 − NOVEMBER 2006
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C and VVSP = +24V, unless otherwise noted.
NONLINEARITY DISTRIBUTION
0.1
0 .0 9
0 .0 8
0 .0 7
0 .0 6
0 .0 5
0 .0 4
0 .0 3
0 .0 2
0
0 .0 1
− 0.01
− 0.02
− 0.03
− 0.04
− 0.05
− 0.06
− 0.07
− 0.08
− 0.09
− 0 .1
0 .01
0.009
0.008
0.007
0.006
0.005
0.004
0.003
0.002
0
0.001
− 0 .0 01
− 0 .0 02
− 0 .0 03
− 0 .0 04
− 0 .0 05
− 0 .0 06
− 0 .0 07
− 0 .0 08
− 0 .0 09
− 0.01
Population
Population
GAIN ERROR DISTRIBUTION
Gain Error (%)
Nonlinearity (%)
NONLINEARITY DRIFT DISTRIBUTION
(IOUT = 0.1mA to 25mA; T = −55_C to +125_C)
NONLINEARITY vs TEMPERATURE
0.03
0.02
Population
Nonlinearity (%)
0.1mA to 25mA
0.01
0
4mA to 20mA
−0.01
−0.02
−0.03
−75
−50
−25
0
25
50
75
100
0
125
0.5
1.0
Temperature (_C)
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Nonlinearity Drift (ppm/_C)
GAIN ERROR DRIFT DISTRIBUTION
(IOUT = 0.1mA to 25mA; T = −55_C to +125_ C)
GAIN ERROR vs TEMPERATURE
0.15
0.05
Population
Gain Error (%)
0.10
4mA to 20mA
0
−0.05
0.1mA to 25mA
−0.10
−0.15
−75
−50
−25
0
25
50
Temperature (_C)
75
100
125
− 10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
Gain Error Drift (ppm/_ C)
5
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SBOS375 − NOVEMBER 2006
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C and VVSP = +24V, unless otherwise noted.
TYPICAL NONLINEARITY
(2pt Calibration at 0.1mA and 25mA)
0.0020
0.0020
0.0015
0.0015
0.0010
0.0010
Nonlinearity (%)
Nonlinearity (%)
TYPICAL NONLINEARITY
(2pt Calibration at 4mA and 20mA)
0.0005
0.000
−0.0005
0.0005
0.000
−0.0005
−0.0010
−0.0010
−0.0015
−0.0015
−0.0020
−0.0020
4
8
12
16
0
20
25
20
INPUT VOLTAGE RANGE LIMIT TO THE
POSITIVE SUPPLY vs TEMPERATURE
3.0
Seven Typical Units Shown
2.9
Input Voltage Range Limit
VVSP − VVIN (V)
0.004
0.002
0.000
−0.002
−0.004
−0.006
−0.008
VVSP = 12V
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
−0.010
2.0
0
5
10
15
20
25
30
35
40
−75
−50
−25
0
IOUT (mA)
25
50
75
100
125
Temperature (_ C)
OUTPUT SWING OF THE VOLTAGE ON IS PIN (VIS)
vs OUTPUT CURRENT
OUTPUT SWING OF THE VOLTAGE ON IS PIN (VIS)
vs TEMPERATURE
1.8
3.0
1.7
2.5
20mA
1.6
2.0
VVSP − VIS (V)
VVSP − VIS (V)
15
TYPICAL NONLINEARITY
(2pt Calibration at 0.1mA and 36mA)
0.006
Nonlinearity (%)
10
IOUT (mA)
0.010
0.008
5
IOUT (mA)
1.5
1.0
1.5
10mA
1.4
1.3
4mA
1.2
0.5
1.1
0
1.0
0
5
10
15
20
25
Output Current (mA)
6
30
35
40
−75
−50
−25
0
25
50
Temperature (_ C)
75
100
125
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SBOS375 − NOVEMBER 2006
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C and VVSP = +24V, unless otherwise noted.
INPUT OFFSET VOLTAGE DISTRIBUTION
0.7
0.8
0.9
1
M ore
0
0.1
0.2
0.3
0.4
0.5
0.6
− 0.2
− 0.1
− 0.7
− 0.6
− 0.5
− 0.4
− 0.3
− 0.9
− 0.8
−1
Population
Population
INPUT OFFSET VOLTAGE DRIFT DISTRIBUTION
−5
−4
−3
−2
0
1
2
3
4
5
6
VOS Drift (µV/_ C)
Input Offset Voltage (mV)
INPUT OFFSET VOLTAGE vs SUPPLY VOLTAGE
AMPLIFIER INPUT BIAS CURRENT vs TEMPERATURE
30
80
28
60
26
Input Bias Current (nA)
100
40
20
0
−20
−40
−60
−80
24
22
20
18
16
14
12
−100
10
0
10
20
30
−75
50
40
−50
−25
Supply Voltage (V)
0
25
50
75
100
125
Temperature (_ C)
OUTPUT CURRENT LIMIT DISTRIBUTION
OUTPUT CURRENT LIMIT vs TEMPERATURE
50
49
Population
Current Limit (mA)
48
47
46
45
44
43
42
41
Current Limit (mA)
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
40
36
Input Offset Voltage (µV)
−1
−75
−50
−25
0
25
50
75
100
125
Temperature (_ C)
7
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SBOS375 − NOVEMBER 2006
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C and VVSP = +24V, unless otherwise noted.
REGULATOR VOLTAGE DRIFT DISTRIBUTION
REGULATOR VOLTAGE DISTRIBUTION
ILOAD = 0.6mA
3.15 0
3.13 5
3.12 0
3.10 5
3.09 0
3.07 5
3.06 0
3.04 5
3.03 0
3
3.01 5
2.98 5
2.97 0
2.95 5
2.94 0
2.92 5
2.91 0
2.89 5
2.88 0
2.86 5
2.85 0
Population
Population
ILOAD = 0.6mA
0
10
20
30
40
50
60
70
80
More
Regulator Voltage Drift (ppm/_C)
Regulator Voltage (V)
REGULATOR INPUT BIAS CURRENT DISTRIBUTION
(Current into REGS Pin)
4.0
3.6
3.2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0
− 0.4
− 0.8
− 1.6
− 1.2
− 2.0
− 2.4
− 2.8
− 3.2
− 3.6
− 4.0
Population
Population
REGULATOR INPUT BIAS CURRENT
DRIFT DISTRIBUTION (Drift of Current into REGS Pin)
0
0.5
REGULATOR VOLTAGE vs SUPPLY VOLTAGE
2.0
2.5
3.0
3.5
4.0
4.5
5.0
3.05
ILOAD = 0.6mA
3.04
ILOAD = 0.6mA
3.04
3.03
Regulator Voltage (V)
3.03
Regulator Voltage (V)
1.5
REGULATOR VOLTAGE vs TEMPERATURE
3.05
3.02
3.01
3.00
2.99
2.98
3.02
3.01
3.00
2.99
2.98
2.97
2.97
2.96
2.96
2.95
2.95
0
5
10
15
20
25
30
Supply Voltage (V)
8
1.0
VREGS Input Bias Current Drift (nA/_ C)
VREGS Input Bias Current (µA)
35
40
45
50
−75
−50
−25
0
25
50
Temperature (_C)
75
100
125
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SBOS375 − NOVEMBER 2006
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C and VVSP = +24V, unless otherwise noted.
STEP RESPONSE: VFS = 4V, RSET = 2kΩ, RLD = 600Ω
(Rising Edge Depends on CGATE at VG Pin)
STEP RESPONSE: VFS = 2.5V, RSET = 1.25kΩ, RLD = 600Ω
(Rising Edge Depends on CGATE at VG Pin)
Photo taken with CGATE = 130pF
Photo taken with C GATE = 130pF
5V/div
10V/div
5V/div
2V/div
10µs/div
10µs/div
REGULATOR LOAD TRANSIENT
(VREG Gain = 1V, VREGF = 3V, CL = 470nF
ILOAD = 3mA ±0.3mA)
REGULATOR LOAD TRANSIENT
(VREG Gain = 4V, VREGF = 12V, CL = 470nF,
I LOAD = 3mA ±0.3mA)
2V/div
10mV/div
10mV/div
1V/div
40µs/div
40µs/div
Maximum Regulator Output Current (mA)
MAXIMUM REGULATOR CURRENT vs TEMPERATURE
29
27
25
23
21
19
17
15
−75
−50
−25
0
25
50
75
100
125
Temperature (_C)
9
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SBOS375 − NOVEMBER 2006
APPLICATION INFORMATION
The output disable (OD) provided can be used during power-on, multiplexing and other conditions where the output
should present no current. It has an internal pull-up that
causes the XTR111 to come up in output disable mode unless the OD pin is tied low.
The XTR111 is a voltage-controlled current source capable of delivering currents from 0mA to 36mA. The primary
intent of the device is to source the commonly-used industrial current ranges of 0mA−20mA or 4mA−20mA. The performance is specified for a supply voltage of up to 40V. The
maximum supply voltage is 44V. The voltage-to-current ratio is defined by an external resistor, RSET; therefore, the input voltage range can be freely set in accordance with the
application requirement. The output current is cascoded
by an external P-Channel MOSFET transistor for large
voltage compliance extending below ground, and for easy
power dissipation. This arrangement ensures excellent
suppression of typical interference signals from the industrial environment because of the extremely high output impedance and wide voltage compliance.
The onboard voltage regulator can be adjusted between
3V to 15V and delivers up to 5mA load current. It is intended to supply signal conditioning and sensor excitation
in 3-wire sensor systems. Voltages above 3V can be set
by a resistive divider.
Figure 1 shows a basic connection for the XTR111. The input voltage VVIN reappears across RSET and controls 1/10
of the output current. The I-Mirror has a precise current
gain of 10. This configuration leads to the transfer function:
IOUT = 10 • (VVIN/RSET)
The output of the voltage regulator can be set over the
range of 3V to 12V by selecting R1 and R2 using the following equation.
An error detection circuit activates a logic output (error
flag) in case the output current cannot correctly flow. It indicates a wire break, high load resistor, or loss of headroom
for the current output to the positive supply.
VREGF = 3V • (R1 + R2)/R2
VVSP = 24V Supply
C1
1
VSP
REGF
I−Mirror
5
R1
5.6kΩ
REGS
OD
EF
9
(Pull Low for Normal Operation)
8
IS
2
VG
3
S
G
4
D
QEXT
P−Channel
MOSFET
0mA or 4mA to 20mA
3V
VOUT
R2
8.2kΩ
IOUT
5V
6
Load
VIN
Signal
Source
(Sensor or
DAC, for
example)
(± Load Ground)
GND
10
SET
7
RSET
IOUT = 10
( RV )
VIN
SET
Figure 1. Basic Connection for 0mA to 20mA Related to 0V to 5V Signal Input. The Voltage Regulator is
Set to 5V Output.
10
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SBOS375 − NOVEMBER 2006
EXPLANATION OF PIN FUNCTIONS
VIN: This input is a conventional, noninverting, highimpedance input of the internal operational amplifier
(OPA). The internal circuitry is protected by clamp diodes
to supplies. An additional clamp connected to
approximately 18V protects internal circuitry. Place a small
resistor in series with the input to limit the current into the
protection if voltage can be present without the XTR111
being powered. Consider a resistor value equal to RSET for
bias current cancellation.
REGF: The output of the regulator buffer can source up to
5mA current, but has very limited (less than 50µA) sinking
capability. The maximum short-circuit current is in the
range of 15mA to 25mA, changing over temperature.
REGS: This pin is the sense input of the voltage regulator.
It is referenced to an internal 3V reference circuit. The input
bias current can be up to 2µA. Avoid capacitive loading of
REGS that may compromise the loop stability of the
voltage regulator.
SET: The total resistance connected between this pin and
VIN reference sets the transconductance. Additional
series resistance can degrade accuracy and drift. The
voltage on this pin must not exceed 14V because this pin
is not protected to voltages above this level.
VSP: The supply voltage of up to a maximum of 44V allows
operation in harsh industrial environment and provides
headroom for easy protection against over-voltage. Use a
large enough bypass capacitor (> 100nF) and eventually
a damping inductor or a small resistor (5Ω) to decouple the
XTR111 supply from the noise typically found on the 24V
supplies.
IS: This output pin is connected to the transistor source of
the external FET. The accuracy of the output current to IS
is achieved by dynamic error correction in the current
mirror. This pin should never be pulled more than 6.5V
below the positive supply. An internal clamp is provided to
protect the circuit, but it must be current-limited externally
to less than 25mA.
EF: The active low error flag (logic output) is intended for
use with an external pull-up to logic-high for reliable
operation when this output is used. However, it has a weak
internal pull-up to 5V and can be left unconnected if not
used.
VG: The gate drive for the external FET is protected
against shorts to the supply and GND. The circuit is
clamped so that it will not drive more than 18V below the
positive supply. The external FET should be protected if its
gate could be externally pulled beyond its ratings.
OD: This control input has a 4µA internal pull-up disabling
the output. A pull-down or short to GND is required to
activate the output. Controlling OD reduces output glitches
during power-on and power-off. This logic input controls
the output. If not used, connect to GND.
The regulator is not affected by OD.
11
"###
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SBOS375 − NOVEMBER 2006
EXTERNAL MOSFET
to IS; however, this compensation may slow the output
down.
The XTR 111 delivers the precise output current to the IS
pin. The voltage at this pin is normally 1.4V below VVSP. It
must not fall more than 5.5V below VVSP.
The drain-to-source breakdown voltage should be selected high enough for the application. Surge voltage
protection might be required for negative over-voltages.
For positive over-voltages, a clamp diode to the 24V supply is recommended, protecting the FET from reversing.
This output requires an external transistor (QEXT) that
forms a cascode for the current output. The resistor must
be rated for the maximum possible voltage on VOUT and
must dissipate the power generated by the current and the
voltage across it.
The gate drive (VG) can drive from close to the positive
supply rail to 16V below the positive supply voltage (VVSP).
Most modern MOSFETs accept a maximum VGS of 20V. A
protection clamp is only required if a large drain gate capacitance can pulse the gate beyond the rating of the
MOSFET. Pulling the OD pin high disables the gate driver
and closes a switch connecting an internal 3kΩ resistor
from the VSP pin to the VG pin. This resistor discharges
the gate of the external FET and closes the channel; see
Figure 2.
VSP
16V
OD
Switch
3kΩ
VG
Table 1 lists some example devices in SO-compatible
packages, but other devices can be used as well. Avoid external capacitance from IS. This capacitance could be
compensated by adding additional capacitance from VG
GND
Figure 2. Equivalent Circuit for Gate Drive and
Disable Switch
Table 1. P-Channel MOSFET (Examples)(1)
MANUFACTURER
PART NO.
BREAKDOWN VGS
PACKAGE
C-GATE
Infineon
BSP170P
−60V
SOT-223
328pF
International Rectifier
IRFL9014
−60V
SOT-223
270pF
NEC
2SJ326-Z
−60V
Spec.
320pF
ON Semiconductor
NTF2955
−60V
SOT-223
492pF
Supertex Inc.
TP2510
−100V
TO-243AA
80pF
(1) Data from published product data sheet; not ensured.
12
"###
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SBOS375 − NOVEMBER 2006
DYNAMIC PERFORMANCE
The rise time of the output current is dominated by the gate
capacitance of the external FET.
The accuracy of the current mirror relies on the dynamic
matching of multiple individual current sources. Settling to
full resolution may require a complete cycle lasting around
100µs. Figure 3 shows an example of the ripple generated
from the individual current source values that average to
the specified accuracy over the full cycle.
The output glitch magnitude depends on the mismatch of
the internal current sources. It is approximately
proportional to the output current level and scales directly
with the load resistor value. It will slightly differ from part to
part.
External FET
50mV/div
No Filter
500Ω
20µs/div
Figure 3. Output Noise without Filter into 500Ω
External FET
50mV/div
Load Capacitor
CF
10nF
500Ω
20µs/div
Figure 4. Output with 10nF Parallel to 500Ω
External FET
NOTE: Scale has been changed
from Figure 3 and Figure 4.
5mV/div
Typical Filter
RF
10kΩ
500Ω
CF
10nF
20µs/div
Figure 5. Output with Additional Filter
13
"###
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SBOS375 − NOVEMBER 2006
OUTPUT ERROR FLAG AND DISABLE INPUT
The XTR111 has additional internal circuitry to detect an
error in the output current. In case the controlled output
current cannot flow due to a wire break, high load
resistance or the output voltage level approaching the
positive supply, the error flag (EF), an open drain logic
output, pulls low. When used, this digital output requires
external pull-up to logic high (the internal pull-up current is
2µA).
The output disable (OD) is a logic input with approximately
4µA of internal pull-up to 5V. The XTR111 comes up with
the output disabled until the OD pin is pulled low. Logic
high disables the output to zero output current. It can be
used for calibration, power-on and power-off glitch
reduction and for output multiplexing with other outputs
connected to the same terminal pin.
Power-on while the output is disabled (OD = high) cannot
fully suppress output glitching. While the supply voltage
passes through the range of 3V to 4V, internal circuits turn
on. Additional capacitance between pins VG and IS can
suppress the glitch. The smallest glitch energy appears
with the OD pin left open; for practical use, however, this
pin can be driven high through a 10kΩ resistor before the
24V supply is applied, if logic voltage is available earlier.
Alternatively, an open drain driver can control this pin using
the internal pull-up current. Pull-up to the internal regulator
tends to increase the energy because of the delay of the
regulator voltage increase, again depending on the supply
voltage rise time for the first few volts.
INPUT VOLTAGE
The input voltage range for a given output current span is
set by RSET according to the transfer function. Select a
precise and low drift resistor for best performance,
because resistor drift directly converts into drift of the
output current. Careful layout must also minimize any
series resistance with RSET and the VIN reference point.
The input voltage is referred to the grounding point of RSET.
Therefore, this point should not be distorted from other
currents. Assuming a 5V full-scale input signal for a 20mA
output current, RSET is 2.5kΩ. A resistance uncertainty of
just 2.5Ω already degrades the accuracy to below 0.1%.
The linear input voltage range extends from 0V to 12V, or
2.3V below the positive supply voltage (whichever is
smaller). The lowest rated supply voltage accomodates
an input voltage range of up to 5V. Potential clipping is not
detected by an error signal; therefore, safe design guard
banding is recommended.
14
Do not drive the input negative (referred to GND) more
than 300mV. Higher negative voltages turn on the internal
protection diodes. Insert a resistor in series with the input
if negative signals can occur eventually during power-on
or -off or during other transient conditions. Select a resistor
value limiting the possible current to 0.3mA. Higher
currents are non-destructive (see Absolute Maximum
Ratings), but they can produce output current glitches
unless in disable mode.
More protection against negative input signals is provided
using a standard diode and a 2.2kΩ resistor, as shown in
Figure 6.
2.2kΩ
V−Signal
VIN
1N4148
Figure 6. Enhanced Protection Against Negative
Overload of VIN
4mA−20mA OUTPUT
The XTR111 does not provide internal circuits to generate
4mA with 0V input signal. The most common way to shift
the input signal is a two resistor network connected to a
voltage reference and the signal source, as shown in
Figure 7. This arrangement allows easy adjustment for
over-and under-range. The example assumes a 5V
reference (VREF) that equals the full-scale signal voltage
and a signal span of 0V to 5V for 4mA to 20mA (IMIN to IMAX)
output.
Reference
Voltage
5V
Input Voltage
0V to 5V
R1
40kΩ
R2
10kΩ
VIN
1V to 5V
Figure 7. Resistive Divider for IMIN to IMAX Output
(4mA to 20mA) with 0 to VFS Signal Source
The voltage regulator output or a more precise reference
can be used as VREF. Observe the potential drift added by
the drift of the resistors and the voltage reference.
"###
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SBOS375 − NOVEMBER 2006
LEVEL SHIFT OF 0V INPUT AND
TRANSCONDUCTANCE TRIM
Table 2 provides example values for the regulator
adjustment resistors.
The XTR111 offers low offset voltage error at the input,
which normally does not require cancellation. If the signal
source cannot deliver 0V in a single-supply circuit, an
additional resistor from the SET pin to a positive reference
voltage or the regulator output (Figure 8) can shift the zero
level for the input (VIN) to a positive voltage. Therefore, the
signal source can drive this value within a positive voltage
range. The example shows a +100mV (102.04mV) offset
generated to the signal input. The larger this offset,
however, the more influence of its drift and inaccuracy is
seen in the output signal. The voltage at SET should not
be larger than 12V for linear operation
Table 2. Examples for the Resistor Values Setting
the Regulator Voltage
VREGF(1)
R1
3V
0

3.3V
3.3kΩ
33kΩ
5V
5.6kΩ
8.2kΩ
12.4V
27kΩ
8.6kΩ
R2
(1) Values have been rounded.
XTR111
I−V Amp
Transconductance (the input voltage to output current
ratio) is set by RSET. The desired resistor value may be
found by choosing a combination of two resistors.
VIN
VOLTAGE REGULATOR
The externally adjustable voltage regulator provides up to
5mA of current. It offers drive (REGF) and sense (REGS)
to allow external setting of the output voltage as shown in
Figure 9. The sense input (REGS) is referenced to 3.0V
representing the lowest adjustable voltage level. An
external resistor divider sets VREGF.
VREGF = VREGS • (R1 + R2)/R2
REGF
3V
120kΩ
5V
Reference
SET
+100mV
Offset
R SET
2kΩ
Figure 8. Input Voltage Level Shift for 0mA
Output Current
REGF
VREG
470nF
REGS
R1
5.6kΩ
REG
REGS
470nF
R2
8.2kΩ
3V
3V
(a)
(b)
VSP
220Ω
1kΩ
REGF
REGF
1kΩ
5V
Source
VREG
470nF
R3
47kΩ
REGS
R1
5.6kΩ
REGS
3V
R2
8.2kΩ
3V
(c)
(d)
Figure 9. Basic Connections of the Voltage Regulator
15
"###
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SBOS375 − NOVEMBER 2006
The voltage at REGF is limited by the supply voltage. If the
supply voltage drops close to the set voltage, the driver
output saturates and follows the supply with a voltage drop
of less than 1V (depending on load current and
temperature).
For good stability and transient response, use a load
capacitance of 470nF or larger. The bias current into the
sense input (REGS) is typically less than 1µA. This current
should be considered when selecting high resistance
values for the voltage setting because it lowers the voltage
and produces additional temperature dependence.
The REGF output cannot sink current. In case of supply
voltage loss, the output is protected against the discharge
currents from load capacitors by internal protection
diodes; the peak current should not exceed 25mA.
If the voltage regulator output is not used, connect REGF
to REGS (the 3V mode) loaded with a 2.2nF capacitor.
Alternatively, overdrive the loop pulling REGS high (see
Figure 9d).
APPLICATION BLOCK DIAGRAMS
1
VSP
5
5V
C2
470nF
Current
Mirror
REGF
R1
2kΩ
4
OD
9
EF
8
IS
2
VG
3
G
REGS
R2
3kΩ
S
Q1
D
3V
Digital I/O
12−Bit Digital−to−Analog
Converter
DAC7551
R3
2.5kΩ
6
VIN
GND
10
SET
7
SW1
R S ET
2.5kΩ
0mA to 20mA or
0V to 5V Output
CL O A D
R LO AD
Switch for current
or voltage output
Figure 10. Current or Voltage Output (SW1) Using 0V to 5V Input from a 12-Bit Digital-to-Analog
Converter DAC7551
16
"###
www.ti.com
SBOS375 − NOVEMBER 2006
1
VSP
5V
C2
470nF
REF3040
4096mV
Voltage Reference
5
REGF
4
REGS
Current
Mirror
R1
2kΩ
R2
3kΩ
OD
9
EF
8
IS
2
VG
3
G
S
Q1
D
3V
Digital I/O
16−Bit Digital−to−Analog
Converter
DAC8551
R3
2kΩ
6
VIN
SET
GND
7
R4
817.2kΩ
10
Load
C LO AD
RL OA D
0mA to 20mA output
for 10mV to 4096mV input
or a code of 160b to 65536b
R SE T
2kΩ
(1.995kΩ)
NOTE: Calculate R SE T for R 4 Parallel to R S ET .
Figure 11. Precision Current Output with Signal from 16-Bit DAC. Input Offset Shifted (R4) by 10mV for
Zero Adjustment Range
1
VSP
5
4
Current
Mirror
REGF
OD
9
EF
8
IS
2
VG
3
G
REGS
S
Q1
D
3V
0V to 10V
Signal Input
6
VIN
GND
10
SET
7
Load
SW1
RS E T
5kΩ
C LO AD
R LO A D
Current (open) or
Voltage (close) Output
Figure 12. 0V to 10V or 0mA to 20mA Output Selected by Jumper (SW1)
17
"###
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SBOS375 − NOVEMBER 2006
1
VSP
3V Supply
Output
5
REGF
4
REGS
Current
Mirror
OD
9
EF
8
IS
2
VG
3
G
GI
S
Q1
D
2−Wire
4mA to 20mA
3V
0.4V to 2V
Input
R5
20kΩ
6
VIN
R4
10kΩ
GND
SET
10
7
R S ET
50.251Ω
GI
NOTE: The input voltage contains the signal offset: for example 0.4V to 2V input
signal. The input signal and supply output are referenced to GND (pin10).
Figure 13. 2-Wire 4mA to 20mA Current Loop Driver with Adjustable Voltage Regulator
1
VSP
3V Supply
5
REGF
4
REGS
Current
Mirror
OD
9
EF
8
IS
2
VG
3
GI
Q1
R4
150kΩ
0V to 2V
Input
R3
25kΩ
6
S
G
D
3V
2−Wire
4mA to 20mA
Output
VIN
GI
R5
10kΩ
SET
7
GND
10
R SE T
50.251Ω
GI
NOTE: Input voltage range is set by the four external resistors. Q 1 can be a FET or a PNP transistor. Internal GND reference is GI.
Figure 14. 2-Wire 4mA to 20mA Current Loop Driver for 0V to 2V Signal Input
18
"###
www.ti.com
SBOS375 − NOVEMBER 2006
(a)
(b)
R4(1)
100Ω
+24V
Q2
NPN
Q2
NPN
R3
1kΩ
R3
1kΩ
REGF
REGF
R1
10kΩ
REGS
3V
C2
470nF
REGS
6V
C2
470nF
R2
10kΩ
NOTE: (1) Resistor R4 can be calculated to protect Q2
from overcurrent in fault conditions.
Figure 15. Voltage Regulator Current Boost Using a Standard NPN Transistor
PACKAGE AND HEAT SINKING
The dominant portion of power dissipation for the current
output is in the external FET.
The XTR111 only generates heat from the supply voltage
with the quiescent current, the internal signal current that
is 1/10 of the output current and the current and internal
voltage drop of the regulator.
The exposed thermal pad on the bottom of the XTR111
package allows excellent heat dissipation of the device
into the printed circuit board (PCB).
THERMAL PAD
The thermal pad must be connected to the same voltage
potential as the device GND pin.
Packages with an exposed thermal pad are specifically
designed to provide excellent power dissipation, but board
layout greatly influences overall heat dissipation. The
thermal resistance from junction-to-ambient (TJA) is
specified for the packages with the exposed thermal pad
soldered to a normalized PCB, as described in Technical
Brief SLMA002, PowerPAD Thermally-Enhanced
Package. See also EIA/JEDEC Specifications JESD51-0
to 7, QFN/SON PCB Attachment (SLUA271), and Quad
Flatpack No-Lead Logic Packages (SCBA017). These
documents are available for download at www.ti.com.
Component population, layout of traces, layers, and air
flow strongly influence heat dissipation. Worst-case load
conditions should be tested in the real environment to
ensure proper thermal conditions. Minimize thermal stress
for proper long-term operation with a junction temperature
well below +125°C.
LAYOUT GUIDELINES
The leadframe die pad should be soldered to a thermal pad
on the PCB. A mechanical data sheet showing an example
layout is attached at the end of this data sheet.
Refinements to this layout may be required based on
assembly process requirements. Mechanical drawings
located at the end of this data sheet list the physical
dimensions for the package and pad. The five holes in the
landing pattern are optional, and are intended for use with
thermal vias that connect the leadframe die pad to the
heatsink area on the PCB.
Soldering the exposed pad significantly improves
board-level reliability during temperature cycling, key
push, package shear, and similar board-level tests. Even
with applications that have low-power dissipation, the
exposed pad must be soldered to the PCB to provide
structural integrity and long-term reliability.
NOTE: All thermal models have an accuracy 20%.
19
PACKAGE OPTION ADDENDUM
www.ti.com
5-Feb-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
XTR111AIDRCR
ACTIVE
SON
DRC
10
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
XTR111AIDRCRG4
ACTIVE
SON
DRC
10
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
XTR111AIDRCT
ACTIVE
SON
DRC
10
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
XTR111AIDRCTG4
ACTIVE
SON
DRC
10
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
Device
17-May-2007
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
XTR111AIDRCR
DRC
10
MLA
330
12
3.3
3.3
1.1
8
12
PKGORN
T2TR-MS
P
XTR111AIDRCT
DRC
10
MLA
180
12
3.3
3.3
1.1
8
12
PKGORN
T2TR-MS
P
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm)
Width (mm)
XTR111AIDRCR
DRC
10
MLA
346.0
346.0
29.0
XTR111AIDRCT
DRC
10
MLA
190.0
212.7
31.75
Pack Materials-Page 2
Height (mm)
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
Pack Materials-Page 3
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Wireless
www.ti.com/wireless
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